2 # Copyright 2007-2020 The OpenSSL Project Authors. All Rights Reserved.
4 # Licensed under the Apache License 2.0 (the "License"). You may not use
5 # this file except in compliance with the License. You can obtain a copy
6 # in the file LICENSE in the source distribution or at
7 # https://www.openssl.org/source/license.html
10 # ====================================================================
11 # Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
12 # project. The module is, however, dual licensed under OpenSSL and
13 # CRYPTOGAMS licenses depending on where you obtain it. For further
14 # details see http://www.openssl.org/~appro/cryptogams/.
15 # ====================================================================
17 # sha1_block procedure for ARMv4.
21 # Size/performance trade-off
22 # ====================================================================
23 # impl size in bytes comp cycles[*] measured performance
24 # ====================================================================
26 # armv4-small 392/+29% 1958/+64% 2250/+96%
27 # armv4-compact 740/+89% 1552/+26% 1840/+22%
28 # armv4-large 1420/+92% 1307/+19% 1370/+34%[***]
29 # full unroll ~5100/+260% ~1260/+4% ~1300/+5%
30 # ====================================================================
31 # thumb = same as 'small' but in Thumb instructions[**] and
32 # with recurring code in two private functions;
33 # small = detached Xload/update, loops are folded;
34 # compact = detached Xload/update, 5x unroll;
35 # large = interleaved Xload/update, 5x unroll;
36 # full unroll = interleaved Xload/update, full unroll, estimated[!];
38 # [*] Manually counted instructions in "grand" loop body. Measured
39 # performance is affected by prologue and epilogue overhead,
40 # i-cache availability, branch penalties, etc.
41 # [**] While each Thumb instruction is twice smaller, they are not as
42 # diverse as ARM ones: e.g., there are only two arithmetic
43 # instructions with 3 arguments, no [fixed] rotate, addressing
44 # modes are limited. As result it takes more instructions to do
45 # the same job in Thumb, therefore the code is never twice as
46 # small and always slower.
47 # [***] which is also ~35% better than compiler generated code. Dual-
48 # issue Cortex A8 core was measured to process input block in
53 # Rescheduling for dual-issue pipeline resulted in 13% improvement on
54 # Cortex A8 core and in absolute terms ~870 cycles per input block
55 # [or 13.6 cycles per byte].
59 # Profiler-assisted and platform-specific optimization resulted in 10%
60 # improvement on Cortex A8 core and 12.2 cycles per byte.
64 # Add NEON implementation (see sha1-586.pl for background info). On
65 # Cortex A8 it was measured to process one byte in 6.7 cycles or >80%
66 # faster than integer-only code. Because [fully unrolled] NEON code
67 # is ~2.5x larger and there are some redundant instructions executed
68 # when processing last block, improvement is not as big for smallest
69 # blocks, only ~30%. Snapdragon S4 is a tad faster, 6.4 cycles per
70 # byte, which is also >80% faster than integer-only code. Cortex-A15
71 # is even faster spending 5.6 cycles per byte outperforming integer-
72 # only code by factor of 2.
76 # Add ARMv8 code path performing at 2.35 cpb on Apple A7.
78 # $output is the last argument if it looks like a file (it has an extension)
79 # $flavour is the first argument if it doesn't look like a file
80 $output = $#ARGV >= 0 && $ARGV[$#ARGV] =~ m|\.\w+$| ? pop : undef;
81 $flavour = $#ARGV >= 0 && $ARGV[0] !~ m|\.| ? shift : undef;
83 if ($flavour && $flavour ne "void") {
84 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
85 ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
86 ( $xlate="${dir}../../perlasm/arm-xlate.pl" and -f $xlate) or
87 die "can't locate arm-xlate.pl";
89 open STDOUT,"| \"$^X\" $xlate $flavour \"$output\""
90 or die "can't call $xlate: $!";
92 $output and open STDOUT,">$output";
112 my ($a,$b,$c,$d,$e,$opt1,$opt2)=@_;
117 add $e,$K,$e,ror#2 @ E+=K_xx_xx
120 eor $t2,$t2,$t3 @ 1 cycle stall
121 eor $t1,$c,$d @ F_xx_xx
123 add $e,$e,$a,ror#27 @ E+=ROR(A,27)
124 eor $t0,$t0,$t2,ror#31
128 add $e,$e,$t0 @ E+=X[i]
133 my ($a,$b,$c,$d,$e)=@_;
139 add $e,$K,$e,ror#2 @ E+=K_00_19
141 orr $t0,$t0,$t1,lsl#8
142 eor $t1,$c,$d @ F_xx_xx
143 orr $t0,$t0,$t2,lsl#16
144 add $e,$e,$a,ror#27 @ E+=ROR(A,27)
145 orr $t0,$t0,$t3,lsl#24
147 ldr $t0,[$inp],#4 @ handles unaligned
148 add $e,$K,$e,ror#2 @ E+=K_00_19
149 eor $t1,$c,$d @ F_xx_xx
150 add $e,$e,$a,ror#27 @ E+=ROR(A,27)
152 rev $t0,$t0 @ byte swap
156 add $e,$e,$t0 @ E+=X[i]
157 eor $t1,$t1,$d,ror#2 @ F_00_19(B,C,D)
159 add $e,$e,$t1 @ E+=F_00_19(B,C,D)
164 my ($a,$b,$c,$d,$e)=@_;
165 &Xupdate(@_,"and $t1,$b,$t1,ror#2");
167 eor $t1,$t1,$d,ror#2 @ F_00_19(B,C,D)
168 add $e,$e,$t1 @ E+=F_00_19(B,C,D)
173 my ($a,$b,$c,$d,$e)=@_;
174 &Xupdate(@_,"eor $t1,$b,$t1,ror#2");
176 add $e,$e,$t1 @ E+=F_20_39(B,C,D)
181 my ($a,$b,$c,$d,$e)=@_;
182 &Xupdate(@_,"and $t1,$b,$t1,ror#2","and $t2,$c,$d");
184 add $e,$e,$t1 @ E+=F_40_59(B,C,D)
190 #include "arm_arch.h"
192 #if defined(__thumb2__)
201 .global sha1_block_data_order
202 .type sha1_block_data_order,%function
205 sha1_block_data_order:
206 #if __ARM_MAX_ARCH__>=7
208 ldr r12,.LOPENSSL_armcap
209 # if !defined(_WIN32)
211 ldr r12,[r3,r12] @ OPENSSL_armcap_P
213 # if defined(__APPLE__) || defined(_WIN32)
221 stmdb sp!,{r4-r12,lr}
222 add $len,$inp,$len,lsl#6 @ $len to point at the end of $inp
223 ldmia $ctx,{$a,$b,$c,$d,$e}
230 mov $e,$e,ror#30 @ [6]
233 for($i=0;$i<5;$i++) {
234 &BODY_00_15(@V); unshift(@V,pop(@V));
237 #if defined(__thumb2__)
243 bne .L_00_15 @ [((11+4)*5+2)*3]
246 &BODY_00_15(@V); unshift(@V,pop(@V));
247 &BODY_16_19(@V); unshift(@V,pop(@V));
248 &BODY_16_19(@V); unshift(@V,pop(@V));
249 &BODY_16_19(@V); unshift(@V,pop(@V));
250 &BODY_16_19(@V); unshift(@V,pop(@V));
253 ldr $K,.LK_20_39 @ [+15+16*4]
254 cmn sp,#0 @ [+3], clear carry to denote 20_39
257 for($i=0;$i<5;$i++) {
258 &BODY_20_39(@V); unshift(@V,pop(@V));
261 #if defined(__thumb2__)
265 teq $Xi,sp @ preserve carry
267 bne .L_20_39_or_60_79 @ [+((12+3)*5+2)*4]
268 bcs .L_done @ [+((12+3)*5+2)*4], spare 300 bytes
271 sub sp,sp,#20*4 @ [+2]
274 for($i=0;$i<5;$i++) {
275 &BODY_40_59(@V); unshift(@V,pop(@V));
278 #if defined(__thumb2__)
284 bne .L_40_59 @ [+((12+5)*5+2)*4]
288 cmp sp,#0 @ set carry to denote 60_79
289 b .L_20_39_or_60_79 @ [+4], spare 300 bytes
291 add sp,sp,#80*4 @ "deallocate" stack frame
292 ldmia $ctx,{$K,$t0,$t1,$t2,$t3}
298 stmia $ctx,{$a,$b,$c,$d,$e}
300 bne .Lloop @ [+18], total 1307
303 ldmia sp!,{r4-r12,pc}
305 ldmia sp!,{r4-r12,lr}
307 moveq pc,lr @ be binary compatible with V4, yet
308 bx lr @ interoperable with Thumb ISA:-)
310 .size sha1_block_data_order,.-sha1_block_data_order
313 .LK_00_19: .word 0x5a827999
314 .LK_20_39: .word 0x6ed9eba1
315 .LK_40_59: .word 0x8f1bbcdc
316 .LK_60_79: .word 0xca62c1d6
317 #if __ARM_MAX_ARCH__>=7
320 .word OPENSSL_armcap_P
322 .word OPENSSL_armcap_P-.Lsha1_block
325 .asciz "SHA1 block transform for ARMv4/NEON/ARMv8, CRYPTOGAMS by <appro\@openssl.org>"
328 #####################################################################
332 my @V=($a,$b,$c,$d,$e);
333 my ($K_XX_XX,$Ki,$t0,$t1,$Xfer,$saved_sp)=map("r$_",(8..12,14));
335 my @X=map("q$_",(8..11,0..3));
336 my @Tx=("q12","q13");
337 my ($K,$zero)=("q14","q15");
340 sub AUTOLOAD() # thunk [simplified] x86-style perlasm
341 { my $opcode = $AUTOLOAD; $opcode =~ s/.*:://; $opcode =~ s/_/\./;
343 $arg = "#$arg" if ($arg*1 eq $arg);
344 $code .= "\t$opcode\t".join(',',@_,$arg)."\n";
349 '($a,$b,$c,$d,$e)=@V;'. # '$code.="@ $j\n";'.
351 '&add ($e,$e,$Ki)', # e+=X[i]+K
353 '&ldr ($Ki,sprintf "[sp,#%d]",4*(($j+1)&15))',
354 '&add ($e,$e,$a,"ror#27")', # e+=ROR(A,27)
355 '&eor ($t1,$t1,$t0)', # F_00_19
356 '&mov ($b,$b,"ror#2")', # b=ROR(b,2)
357 '&add ($e,$e,$t1);'. # e+=F_00_19
358 '$j++; unshift(@V,pop(@V));'
363 '($a,$b,$c,$d,$e)=@V;'. # '$code.="@ $j\n";'.
365 '&add ($e,$e,$Ki)', # e+=X[i]+K
366 '&ldr ($Ki,sprintf "[sp,#%d]",4*(($j+1)&15)) if ($j<79)',
367 '&eor ($t1,$t0,$c)', # F_20_39
368 '&add ($e,$e,$a,"ror#27")', # e+=ROR(A,27)
369 '&mov ($b,$b,"ror#2")', # b=ROR(b,2)
370 '&add ($e,$e,$t1);'. # e+=F_20_39
371 '$j++; unshift(@V,pop(@V));'
376 '($a,$b,$c,$d,$e)=@V;'. # '$code.="@ $j\n";'.
377 '&add ($e,$e,$Ki)', # e+=X[i]+K
379 '&ldr ($Ki,sprintf "[sp,#%d]",4*(($j+1)&15))',
380 '&add ($e,$e,$a,"ror#27")', # e+=ROR(A,27)
384 '&mov ($b,$b,"ror#2")', # b=ROR(b,2)
385 '&add ($e,$e,$t1);'. # e+=F_40_59
386 '$j++; unshift(@V,pop(@V));'
393 my @insns = (&$body,&$body,&$body,&$body);
396 &vext_8 (@X[0],@X[-4&7],@X[-3&7],8); # compose "X[-14]" in "X[0]"
400 &vadd_i32 (@Tx[1],@X[-1&7],$K);
402 &vld1_32 ("{$K\[]}","[$K_XX_XX,:32]!") if ($Xi%5==0);
404 &vext_8 (@Tx[0],@X[-1&7],$zero,4); # "X[-3]", 3 words
408 &veor (@X[0],@X[0],@X[-4&7]); # "X[0]"^="X[-16]"
411 &veor (@Tx[0],@Tx[0],@X[-2&7]); # "X[-3]"^"X[-8]"
414 &veor (@Tx[0],@Tx[0],@X[0]); # "X[0]"^="X[-3]"^"X[-8]
417 &vst1_32 ("{@Tx[1]}","[$Xfer,:128]!"); # X[]+K xfer
418 &sub ($Xfer,$Xfer,64) if ($Xi%4==0);
421 &vext_8 (@Tx[1],$zero,@Tx[0],4); # "X[0]"<<96, extract one dword
424 &vadd_i32 (@X[0],@Tx[0],@Tx[0]);
427 &vsri_32 (@X[0],@Tx[0],31); # "X[0]"<<<=1
431 &vshr_u32 (@Tx[0],@Tx[1],30);
434 &vshl_u32 (@Tx[1],@Tx[1],2);
437 &veor (@X[0],@X[0],@Tx[0]);
440 &veor (@X[0],@X[0],@Tx[1]); # "X[0]"^=("X[0]">>96)<<<2
442 foreach (@insns) { eval; } # remaining instructions [if any]
444 $Xi++; push(@X,shift(@X)); # "rotate" X[]
450 my @insns = (&$body,&$body,&$body,&$body);
453 &vext_8 (@Tx[0],@X[-2&7],@X[-1&7],8); # compose "X[-6]"
457 &veor (@X[0],@X[0],@X[-4&7]); # "X[0]"="X[-32]"^"X[-16]"
460 &veor (@X[0],@X[0],@X[-7&7]); # "X[0]"^="X[-28]"
463 &vadd_i32 (@Tx[1],@X[-1&7],$K);
465 &vld1_32 ("{$K\[]}","[$K_XX_XX,:32]!") if ($Xi%5==0);
467 &veor (@Tx[0],@Tx[0],@X[0]); # "X[-6]"^="X[0]"
470 &vshr_u32 (@X[0],@Tx[0],30);
473 &vst1_32 ("{@Tx[1]}","[$Xfer,:128]!"); # X[]+K xfer
474 &sub ($Xfer,$Xfer,64) if ($Xi%4==0);
477 &vsli_32 (@X[0],@Tx[0],2); # "X[0]"="X[-6]"<<<2
479 foreach (@insns) { eval; } # remaining instructions [if any]
481 $Xi++; push(@X,shift(@X)); # "rotate" X[]
487 my @insns = (&$body,&$body,&$body,&$body);
490 &vadd_i32 (@Tx[1],@X[-1&7],$K);
493 &vst1_32 ("{@Tx[1]}","[$Xfer,:128]!");
494 &sub ($Xfer,$Xfer,64);
497 &sub ($K_XX_XX,$K_XX_XX,16); # rewind $K_XX_XX
499 &subeq ($inp,$inp,64); # reload last block to avoid SEGV
500 &vld1_8 ("{@X[-4&7]-@X[-3&7]}","[$inp]!");
503 &vld1_8 ("{@X[-2&7]-@X[-1&7]}","[$inp]!");
506 &vld1_32 ("{$K\[]}","[$K_XX_XX,:32]!"); # load K_00_19
509 &vrev32_8 (@X[-4&7],@X[-4&7]);
511 foreach (@insns) { eval; } # remaining instructions
519 my @insns = (&$body,&$body,&$body,&$body);
522 &vrev32_8 (@X[($Xi-3)&7],@X[($Xi-3)&7]);
525 &vadd_i32 (@X[$Xi&7],@X[($Xi-4)&7],$K);
528 &vst1_32 ("{@X[$Xi&7]}","[$Xfer,:128]!");# X[]+K xfer to IALU
530 foreach (@insns) { eval; }
536 #if __ARM_MAX_ARCH__>=7
540 .type sha1_block_data_order_neon,%function
542 sha1_block_data_order_neon:
544 stmdb sp!,{r4-r12,lr}
545 add $len,$inp,$len,lsl#6 @ $len to point at the end of $inp
546 @ dmb @ errata #451034 on early Cortex A8
547 @ vstmdb sp!,{d8-d15} @ ABI specification says so
550 adr $K_XX_XX,.LK_00_19
551 bic $Xfer,$Xfer,#15 @ align for 128-bit stores
553 ldmia $ctx,{$a,$b,$c,$d,$e} @ load context
554 mov sp,$Xfer @ alloca
556 vld1.8 {@X[-4&7]-@X[-3&7]},[$inp]! @ handles unaligned
557 veor $zero,$zero,$zero
558 vld1.8 {@X[-2&7]-@X[-1&7]},[$inp]!
559 vld1.32 {${K}\[]},[$K_XX_XX,:32]! @ load K_00_19
560 vrev32.8 @X[-4&7],@X[-4&7] @ yes, even on
561 vrev32.8 @X[-3&7],@X[-3&7] @ big-endian...
562 vrev32.8 @X[-2&7],@X[-2&7]
563 vadd.i32 @X[0],@X[-4&7],$K
564 vrev32.8 @X[-1&7],@X[-1&7]
565 vadd.i32 @X[1],@X[-3&7],$K
566 vst1.32 {@X[0]},[$Xfer,:128]!
567 vadd.i32 @X[2],@X[-2&7],$K
568 vst1.32 {@X[1]},[$Xfer,:128]!
569 vst1.32 {@X[2]},[$Xfer,:128]!
570 ldr $Ki,[sp] @ big RAW stall
574 &Xupdate_16_31(\&body_00_19);
575 &Xupdate_16_31(\&body_00_19);
576 &Xupdate_16_31(\&body_00_19);
577 &Xupdate_16_31(\&body_00_19);
578 &Xupdate_32_79(\&body_00_19);
579 &Xupdate_32_79(\&body_20_39);
580 &Xupdate_32_79(\&body_20_39);
581 &Xupdate_32_79(\&body_20_39);
582 &Xupdate_32_79(\&body_20_39);
583 &Xupdate_32_79(\&body_20_39);
584 &Xupdate_32_79(\&body_40_59);
585 &Xupdate_32_79(\&body_40_59);
586 &Xupdate_32_79(\&body_40_59);
587 &Xupdate_32_79(\&body_40_59);
588 &Xupdate_32_79(\&body_40_59);
589 &Xupdate_32_79(\&body_20_39);
590 &Xuplast_80(\&body_20_39);
591 &Xloop(\&body_20_39);
592 &Xloop(\&body_20_39);
593 &Xloop(\&body_20_39);
595 ldmia $ctx,{$Ki,$t0,$t1,$Xfer} @ accumulate context
606 stmia $ctx,{$a,$b,$c,$d,$e}
611 @ vldmia sp!,{d8-d15}
612 ldmia sp!,{r4-r12,pc}
613 .size sha1_block_data_order_neon,.-sha1_block_data_order_neon
617 #####################################################################
621 my ($ABCD,$E,$E0,$E1)=map("q$_",(0..3));
622 my @MSG=map("q$_",(4..7));
623 my @Kxx=map("q$_",(8..11));
624 my ($W0,$W1,$ABCD_SAVE)=map("q$_",(12..14));
625 my $_byte = ($flavour =~ /win/ ? "DCB" : ".byte");
628 #if __ARM_MAX_ARCH__>=7
630 # if defined(__thumb2__)
631 # define INST(a,b,c,d) $_byte c,d|0xf,a,b
633 # define INST(a,b,c,d) $_byte a,b,c,d|0x10
636 .type sha1_block_data_order_armv8,%function
638 sha1_block_data_order_armv8:
640 vstmdb sp!,{d8-d15} @ ABI specification says so
644 vld1.32 {$ABCD},[$ctx]!
645 vld1.32 {$E\[0]},[$ctx]
647 vld1.32 {@Kxx[0]\[]},[r3,:32]!
648 vld1.32 {@Kxx[1]\[]},[r3,:32]!
649 vld1.32 {@Kxx[2]\[]},[r3,:32]!
650 vld1.32 {@Kxx[3]\[]},[r3,:32]
653 vld1.8 {@MSG[0]-@MSG[1]},[$inp]!
654 vld1.8 {@MSG[2]-@MSG[3]},[$inp]!
655 vrev32.8 @MSG[0],@MSG[0]
656 vrev32.8 @MSG[1],@MSG[1]
658 vadd.i32 $W0,@Kxx[0],@MSG[0]
659 vrev32.8 @MSG[2],@MSG[2]
660 vmov $ABCD_SAVE,$ABCD @ offload
663 vadd.i32 $W1,@Kxx[0],@MSG[1]
664 vrev32.8 @MSG[3],@MSG[3]
667 vadd.i32 $W0,@Kxx[$j],@MSG[2]
668 sha1su0 @MSG[0],@MSG[1],@MSG[2]
670 for ($j=0,$i=1;$i<20-3;$i++) {
671 my $f=("c","p","m","p")[$i/5];
675 vadd.i32 $W1,@Kxx[$j],@MSG[3]
676 sha1su1 @MSG[0],@MSG[3]
678 $code.=<<___ if ($i<20-4);
679 sha1su0 @MSG[1],@MSG[2],@MSG[3]
681 ($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0);
682 push(@MSG,shift(@MSG)); $j++ if ((($i+3)%5)==0);
687 vadd.i32 $W1,@Kxx[$j],@MSG[3]
696 vadd.i32 $ABCD,$ABCD,$ABCD_SAVE
699 vst1.32 {$ABCD},[$ctx]!
700 vst1.32 {$E\[0]},[$ctx]
704 .size sha1_block_data_order_armv8,.-sha1_block_data_order_armv8
709 #if __ARM_MAX_ARCH__>=7
710 .comm OPENSSL_armcap_P,4,4
715 "sha1c" => 0xf2000c40, "sha1p" => 0xf2100c40,
716 "sha1m" => 0xf2200c40, "sha1su0" => 0xf2300c40,
717 "sha1h" => 0xf3b902c0, "sha1su1" => 0xf3ba0380 );
720 my ($mnemonic,$arg)=@_;
722 if ($arg =~ m/q([0-9]+)(?:,\s*q([0-9]+))?,\s*q([0-9]+)/o) {
723 my $word = $opcode{$mnemonic}|(($1&7)<<13)|(($1&8)<<19)
724 |(($2&7)<<17)|(($2&8)<<4)
725 |(($3&7)<<1) |(($3&8)<<2);
726 # since ARMv7 instructions are always encoded little-endian.
727 # correct solution is to use .inst directive, but older
728 # assemblers don't implement it:-(
730 # this fix-up provides Thumb encoding in conjunction with INST
731 $word &= ~0x10000000 if (($word & 0x0f000000) == 0x02000000);
732 sprintf "INST(0x%02x,0x%02x,0x%02x,0x%02x)\t@ %s %s",
733 $word&0xff,($word>>8)&0xff,
734 ($word>>16)&0xff,($word>>24)&0xff,
740 foreach (split($/,$code)) {
741 s/{q([0-9]+)\[\]}/sprintf "{d%d[],d%d[]}",2*$1,2*$1+1/eo or
742 s/{q([0-9]+)\[0\]}/sprintf "{d%d[0]}",2*$1/eo;
744 s/\b(sha1\w+)\s+(q.*)/unsha1($1,$2)/geo;
747 s/\bbx\s+lr\b/.word\t0xe12fff1e/o; # make it possible to compile with -march=armv4
752 close STDOUT or die "error closing STDOUT: $!"; # enforce flush