3 # ====================================================================
4 # Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
5 # project. The module is, however, dual licensed under OpenSSL and
6 # CRYPTOGAMS licenses depending on where you obtain it. For further
7 # details see http://www.openssl.org/~appro/cryptogams/.
8 # ====================================================================
10 # 2.22x RC4 tune-up:-) It should be noted though that my hand [as in
11 # "hand-coded assembler"] doesn't stand for the whole improvement
12 # coefficient. It turned out that eliminating RC4_CHAR from config
13 # line results in ~40% improvement (yes, even for C implementation).
14 # Presumably it has everything to do with AMD cache architecture and
15 # RAW or whatever penalties. Once again! The module *requires* config
16 # line *without* RC4_CHAR! As for coding "secret," I bet on partial
17 # register arithmetics. For example instead of 'inc %r8; and $255,%r8'
18 # I simply 'inc %r8b'. Even though optimization manual discourages
19 # to operate on partial registers, it turned out to be the best bet.
20 # At least for AMD... How IA32E would perform remains to be seen...
22 # As was shown by Marc Bevand reordering of couple of load operations
23 # results in even higher performance gain of 3.3x:-) At least on
24 # Opteron... For reference, 1x in this case is RC4_CHAR C-code
25 # compiled with gcc 3.3.2, which performs at ~54MBps per 1GHz clock.
26 # Latter means that if you want to *estimate* what to expect from
27 # *your* Opteron, then multiply 54 by 3.3 and clock frequency in GHz.
29 # Intel P4 EM64T core was found to run the AMD64 code really slow...
30 # The only way to achieve comparable performance on P4 was to keep
31 # RC4_CHAR. Kind of ironic, huh? As it's apparently impossible to
32 # compose blended code, which would perform even within 30% marginal
33 # on either AMD and Intel platforms, I implement both cases. See
34 # rc4_skey.c for further details...
36 # P4 EM64T core appears to be "allergic" to 64-bit inc/dec. Replacing
37 # those with add/sub results in 50% performance improvement of folded
40 # As was shown by Zou Nanhai loop unrolling can improve Intel EM64T
41 # performance by >30% [unlike P4 32-bit case that is]. But this is
42 # provided that loads are reordered even more aggressively! Both code
43 # pathes, AMD64 and EM64T, reorder loads in essentially same manner
44 # as my IA-64 implementation. On Opteron this resulted in modest 5%
45 # improvement [I had to test it], while final Intel P4 performance
46 # achieves respectful 432MBps on 2.8GHz processor now. For reference.
47 # If executed on Xeon, current RC4_CHAR code-path is 2.7x faster than
48 # RC4_INT code-path. While if executed on Opteron, it's only 25%
49 # slower than the RC4_INT one [meaning that if CPU ยต-arch detection
50 # is not implemented, then this final RC4_CHAR code-path should be
51 # preferred, as it provides better *all-round* performance].
53 # Intel Core2 was observed to perform poorly on both code paths:-( It
54 # apparently suffers from some kind of partial register stall, which
55 # occurs in 64-bit mode only [as virtually identical 32-bit loop was
56 # observed to outperform 64-bit one by almost 50%]. Adding two movzb to
57 # cloop1 boosts its performance by 80%! This loop appears to be optimal
58 # fit for Core2 and therefore the code was modified to skip cloop8 on
61 # Intel Westmere was observed to perform suboptimally. Adding yet
62 # another movzb to cloop1 improved performance by almost 50%! Core2
63 # performance is improved too, but nominally...
67 if ($flavour =~ /\./) { $output = $flavour; undef $flavour; }
69 $win64=0; $win64=1 if ($flavour =~ /[nm]asm|mingw64/ || $output =~ /\.asm$/);
71 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
72 ( $xlate="${dir}x86_64-xlate.pl" and -f $xlate ) or
73 ( $xlate="${dir}../../perlasm/x86_64-xlate.pl" and -f $xlate) or
74 die "can't locate x86_64-xlate.pl";
76 open STDOUT,"| $^X $xlate $flavour $output";
92 .type RC4,\@function,4
104 movl -8($dat),$XX[0]#d
109 movl ($dat,$XX[0],4),$TX[0]#d
116 for ($i=0;$i<8;$i++) {
120 movl ($dat,$YY,4),$TY#d
121 ror \$8,%rax # ror is redundant when $i=0
123 movl ($dat,$XX[1],4),$TX[1]#d
125 movl $TX[0]#d,($dat,$YY,4)
127 movl $TY#d,($dat,$XX[0],4)
129 movb ($dat,$TY,4),%al
131 push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers
151 movl ($dat,$YY,4),$TY#d
152 movl $TX[0]#d,($dat,$YY,4)
153 movl $TY#d,($dat,$XX[0],4)
156 movl ($dat,$TX[0],4),$TY#d
157 movl ($dat,$XX[0],4),$TX[0]#d
169 movzb ($dat,$XX[0]),$TX[0]#d
180 # unroll 2x4-wise, because 64-bit rotates kill Intel P4...
181 for ($i=0;$i<4;$i++) {
185 movzb ($dat,$YY),$TY#d
186 movzb $XX[1]#b,$XX[1]#d
187 movzb ($dat,$XX[1]),$TX[1]#d
188 movb $TX[0]#b,($dat,$YY)
190 movb $TY#b,($dat,$XX[0])
191 jne .Lcmov$i # Intel cmov is sloooow...
198 push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers
200 for ($i=4;$i<8;$i++) {
204 movzb ($dat,$YY),$TY#d
205 movzb $XX[1]#b,$XX[1]#d
206 movzb ($dat,$XX[1]),$TX[1]#d
207 movb $TX[0]#b,($dat,$YY)
209 movb $TY#b,($dat,$XX[0])
210 jne .Lcmov$i # Intel cmov is sloooow...
217 push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers
237 movzb ($dat,$YY),$TY#d
238 movb $TX[0]#b,($dat,$YY)
239 movb $TY#b,($dat,$XX[0])
243 movzb $XX[0]#b,$XX[0]#d
244 movzb ($dat,$TY),$TY#d
245 movzb ($dat,$XX[0]),$TX[0]#d
257 movl $XX[0]#d,-8($dat)
273 .extern OPENSSL_ia32cap_P
275 .type RC4_set_key,\@function,3
287 mov OPENSSL_ia32cap_P(%rip),$idx#d
297 mov %eax,($dat,%rax,4)
305 mov ($dat,$ido,4),%r10d
306 add ($inp,$len,1),$idx#b
309 mov ($dat,$idx,4),%r11d
311 mov %r10d,($dat,$idx,4)
312 mov %r11d,($dat,$ido,4)
327 mov ($dat,$ido),%r10b
328 add ($inp,$len),$idx#b
331 mov ($dat,$idx),%r11b
335 mov %r10b,($dat,$idx)
336 mov %r11b,($dat,$ido)
347 .size RC4_set_key,.-RC4_set_key
350 .type RC4_options,\@abi-omnipotent
353 lea .Lopts(%rip),%rax
354 mov OPENSSL_ia32cap_P(%rip),%edx
366 .asciz "rc4(8x,char)"
367 .asciz "rc4(1x,char)"
368 .asciz "RC4 for x86_64, CRYPTOGAMS by <appro\@openssl.org>"
370 .size RC4_options,.-RC4_options
373 # EXCEPTION_DISPOSITION handler (EXCEPTION_RECORD *rec,ULONG64 frame,
374 # CONTEXT *context,DISPATCHER_CONTEXT *disp)
382 .extern __imp_RtlVirtualUnwind
383 .type stream_se_handler,\@abi-omnipotent
397 mov 120($context),%rax # pull context->Rax
398 mov 248($context),%rbx # pull context->Rip
400 lea .Lprologue(%rip),%r10
401 cmp %r10,%rbx # context->Rip<prologue label
404 mov 152($context),%rax # pull context->Rsp
406 lea .Lepilogue(%rip),%r10
407 cmp %r10,%rbx # context->Rip>=epilogue label
415 mov %rbx,144($context) # restore context->Rbx
416 mov %r12,216($context) # restore context->R12
417 mov %r13,224($context) # restore context->R13
422 mov %rax,152($context) # restore context->Rsp
423 mov %rsi,168($context) # restore context->Rsi
424 mov %rdi,176($context) # restore context->Rdi
426 jmp .Lcommon_seh_exit
427 .size stream_se_handler,.-stream_se_handler
429 .type key_se_handler,\@abi-omnipotent
443 mov 152($context),%rax # pull context->Rsp
446 mov %rsi,168($context) # restore context->Rsi
447 mov %rdi,176($context) # restore context->Rdi
451 mov 40($disp),%rdi # disp->ContextRecord
452 mov $context,%rsi # context
453 mov \$154,%ecx # sizeof(CONTEXT)
454 .long 0xa548f3fc # cld; rep movsq
457 xor %rcx,%rcx # arg1, UNW_FLAG_NHANDLER
458 mov 8(%rsi),%rdx # arg2, disp->ImageBase
459 mov 0(%rsi),%r8 # arg3, disp->ControlPc
460 mov 16(%rsi),%r9 # arg4, disp->FunctionEntry
461 mov 40(%rsi),%r10 # disp->ContextRecord
462 lea 56(%rsi),%r11 # &disp->HandlerData
463 lea 24(%rsi),%r12 # &disp->EstablisherFrame
464 mov %r10,32(%rsp) # arg5
465 mov %r11,40(%rsp) # arg6
466 mov %r12,48(%rsp) # arg7
467 mov %rcx,56(%rsp) # arg8, (NULL)
468 call *__imp_RtlVirtualUnwind(%rip)
470 mov \$1,%eax # ExceptionContinueSearch
482 .size key_se_handler,.-key_se_handler
490 .rva .LSEH_begin_RC4_set_key
491 .rva .LSEH_end_RC4_set_key
492 .rva .LSEH_info_RC4_set_key
498 .rva stream_se_handler
499 .LSEH_info_RC4_set_key:
505 $code =~ s/#([bwd])/$1/gm;