3 # ====================================================================
4 # Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
5 # project. The module is, however, dual licensed under OpenSSL and
6 # CRYPTOGAMS licenses depending on where you obtain it. For further
7 # details see http://www.openssl.org/~appro/cryptogams/.
8 # ====================================================================
12 # 2.22x RC4 tune-up:-) It should be noted though that my hand [as in
13 # "hand-coded assembler"] doesn't stand for the whole improvement
14 # coefficient. It turned out that eliminating RC4_CHAR from config
15 # line results in ~40% improvement (yes, even for C implementation).
16 # Presumably it has everything to do with AMD cache architecture and
17 # RAW or whatever penalties. Once again! The module *requires* config
18 # line *without* RC4_CHAR! As for coding "secret," I bet on partial
19 # register arithmetics. For example instead of 'inc %r8; and $255,%r8'
20 # I simply 'inc %r8b'. Even though optimization manual discourages
21 # to operate on partial registers, it turned out to be the best bet.
22 # At least for AMD... How IA32E would perform remains to be seen...
26 # As was shown by Marc Bevand reordering of couple of load operations
27 # results in even higher performance gain of 3.3x:-) At least on
28 # Opteron... For reference, 1x in this case is RC4_CHAR C-code
29 # compiled with gcc 3.3.2, which performs at ~54MBps per 1GHz clock.
30 # Latter means that if you want to *estimate* what to expect from
31 # *your* Opteron, then multiply 54 by 3.3 and clock frequency in GHz.
35 # Intel P4 EM64T core was found to run the AMD64 code really slow...
36 # The only way to achieve comparable performance on P4 was to keep
37 # RC4_CHAR. Kind of ironic, huh? As it's apparently impossible to
38 # compose blended code, which would perform even within 30% marginal
39 # on either AMD and Intel platforms, I implement both cases. See
40 # rc4_skey.c for further details...
44 # P4 EM64T core appears to be "allergic" to 64-bit inc/dec. Replacing
45 # those with add/sub results in 50% performance improvement of folded
50 # As was shown by Zou Nanhai loop unrolling can improve Intel EM64T
51 # performance by >30% [unlike P4 32-bit case that is]. But this is
52 # provided that loads are reordered even more aggressively! Both code
53 # pathes, AMD64 and EM64T, reorder loads in essentially same manner
54 # as my IA-64 implementation. On Opteron this resulted in modest 5%
55 # improvement [I had to test it], while final Intel P4 performance
56 # achieves respectful 432MBps on 2.8GHz processor now. For reference.
57 # If executed on Xeon, current RC4_CHAR code-path is 2.7x faster than
58 # RC4_INT code-path. While if executed on Opteron, it's only 25%
59 # slower than the RC4_INT one [meaning that if CPU ยต-arch detection
60 # is not implemented, then this final RC4_CHAR code-path should be
61 # preferred, as it provides better *all-round* performance].
65 # Intel Core2 was observed to perform poorly on both code paths:-( It
66 # apparently suffers from some kind of partial register stall, which
67 # occurs in 64-bit mode only [as virtually identical 32-bit loop was
68 # observed to outperform 64-bit one by almost 50%]. Adding two movzb to
69 # cloop1 boosts its performance by 80%! This loop appears to be optimal
70 # fit for Core2 and therefore the code was modified to skip cloop8 on
75 # Intel Westmere was observed to perform suboptimally. Adding yet
76 # another movzb to cloop1 improved performance by almost 50%! Core2
77 # performance is improved too, but nominally...
81 # The only code path that was not modified is P4-specific one. Non-P4
82 # Intel code path optimization is heavily based on submission by Maxim
83 # Perminov, Maxim Locktyukhin and Jim Guilford of Intel. I've used
84 # some of the ideas even in attempt to optmize the original RC4_INT
85 # code path... Current performance in cycles per processed byte (less
86 # is better) and improvement coefficients relative to previous
87 # version of this module are:
93 # Sandy Bridge 4.2/+120%
97 # Bulldozer 4.5/+30%(*)
99 # (*) But corresponding loop has less instructions, which should have
100 # positive effect on upcoming Bulldozer, which has one less ALU.
101 # For reference, Intel code runs at 6.8 cpb rate on Opteron.
102 # (**) Note that Core2 result is ~15% lower than corresponding result
103 # for 32-bit code, meaning that it's possible to improve it,
104 # but more than likely at the cost of the others (see rc4-586.pl
105 # to get the idea)...
109 if ($flavour =~ /\./) { $output = $flavour; undef $flavour; }
111 $win64=0; $win64=1 if ($flavour =~ /[nm]asm|mingw64/ || $output =~ /\.asm$/);
113 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
114 ( $xlate="${dir}x86_64-xlate.pl" and -f $xlate ) or
115 ( $xlate="${dir}../../perlasm/x86_64-xlate.pl" and -f $xlate) or
116 die "can't locate x86_64-xlate.pl";
118 open STDOUT,"| \"$^X\" $xlate $flavour $output";
128 .extern OPENSSL_ia32cap_P
131 .type RC4,\@function,4
145 my $len="%r11"; # reassign input arguments
149 my @XX=("%r10","%rsi");
150 my @TX=("%rax","%rbx");
159 mov -8($dat),$XX[0]#b
163 mov OPENSSL_ia32cap_P(%rip),%r8d
168 movl ($dat,$XX[0],4),$TX[0]#d
171 bt \$30,%r8d # Intel CPU?
179 movl ($dat,$YY,4),$TY#d
180 movl $TX[0]#d,($dat,$YY,4)
181 movl $TY#d,($dat,$XX[0],4)
184 movl ($dat,$TX[0],4),$TY#d
185 movl ($dat,$XX[0],4),$TX[0]#d
187 movb $TY#b,($out,$inp)
197 for ($i=0;$i<8;$i++) {
198 $code.=<<___ if ($i==7);
203 movl ($dat,$YY,4),$TY#d
204 movl $TX[0]#d,($dat,$YY,4)
205 movl `4*($i==7?-1:$i)`($dat,$XX[1],4),$TX[1]#d
206 ror \$8,%r8 # ror is redundant when $i=0
207 movl $TY#d,4*$i($dat,$XX[0],4)
209 movb ($dat,$TY,4),%r8b
211 push(@TX,shift(@TX)); #push(@XX,shift(@XX)); # "rotate" registers
237 movl ($dat,$YY,4),$TY#d
238 movl $TX[0]#d,($dat,$YY,4)
239 movl $TY#d,($dat,$XX[0],4)
242 movl ($dat,$TX[0],4),$TY#d
243 movl ($dat,$XX[0],4),$TX[0]#d
245 movb $TY#b,($out,$inp)
255 lea ($dat,$XX[0],4),$XX[1]
260 my $xmm="%xmm".($j&1);
262 $code.=" add \$16,$XX[0]#b\n" if ($i==15);
263 $code.=" movdqu ($inp),%xmm2\n" if ($i==15);
264 $code.=" add $TX[0]#b,$YY#b\n" if ($i<=0);
265 $code.=" movl ($dat,$YY,4),$TY#d\n";
266 $code.=" pxor %xmm0,%xmm2\n" if ($i==0);
267 $code.=" psllq \$8,%xmm1\n" if ($i==0);
268 $code.=" pxor $xmm,$xmm\n" if ($i<=1);
269 $code.=" movl $TX[0]#d,($dat,$YY,4)\n";
270 $code.=" add $TY#b,$TX[0]#b\n";
271 $code.=" movl `4*($j+1)`($XX[1]),$TX[1]#d\n" if ($i<15);
272 $code.=" movz $TX[0]#b,$TX[0]#d\n";
273 $code.=" movl $TY#d,4*$j($XX[1])\n";
274 $code.=" pxor %xmm1,%xmm2\n" if ($i==0);
275 $code.=" lea ($dat,$XX[0],4),$XX[1]\n" if ($i==15);
276 $code.=" add $TX[1]#b,$YY#b\n" if ($i<15);
277 $code.=" pinsrw \$`($j>>1)&7`,($dat,$TX[0],4),$xmm\n";
278 $code.=" movdqu %xmm2,($out,$inp)\n" if ($i==0);
279 $code.=" lea 16($inp),$inp\n" if ($i==0);
280 $code.=" movl ($XX[1]),$TX[1]#d\n" if ($i==15);
289 for ($i=0;$i<16;$i++) {
290 $code.=".Loop16_enter:\n" if ($i==1);
292 push(@TX,shift(@TX)); # "rotate" registers
296 xor $YY,$YY # keyword to partial register
305 movdqu %xmm2,($out,$inp)
315 movl ($dat,$YY,4),$TY#d
316 movl $TX[0]#d,($dat,$YY,4)
317 movl $TY#d,($dat,$XX[0],4)
320 movl ($dat,$TX[0],4),$TY#d
321 movl ($dat,$XX[0],4),$TX[0]#d
323 movb $TY#b,($out,$inp)
332 movzb ($dat,$XX[0]),$TX[0]#d
341 # unroll 2x4-wise, because 64-bit rotates kill Intel P4...
342 for ($i=0;$i<4;$i++) {
346 movzb ($dat,$YY),$TY#d
347 movzb $XX[1]#b,$XX[1]#d
348 movzb ($dat,$XX[1]),$TX[1]#d
349 movb $TX[0]#b,($dat,$YY)
351 movb $TY#b,($dat,$XX[0])
352 jne .Lcmov$i # Intel cmov is sloooow...
359 push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers
361 for ($i=4;$i<8;$i++) {
365 movzb ($dat,$YY),$TY#d
366 movzb $XX[1]#b,$XX[1]#d
367 movzb ($dat,$XX[1]),$TX[1]#d
368 movb $TX[0]#b,($dat,$YY)
370 movb $TY#b,($dat,$XX[0])
371 jne .Lcmov$i # Intel cmov is sloooow...
378 push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers
398 movzb ($dat,$YY),$TY#d
399 movb $TX[0]#b,($dat,$YY)
400 movb $TY#b,($dat,$XX[0])
404 movzb $XX[0]#b,$XX[0]#d
405 movzb ($dat,$TY),$TY#d
406 movzb ($dat,$XX[0]),$TX[0]#d
418 movl $XX[0]#d,-8($dat)
436 .type RC4_set_key,\@function,3
448 mov OPENSSL_ia32cap_P(%rip),$idx#d
449 bt \$20,$idx#d # RC4_CHAR?
455 mov %eax,($dat,%rax,4)
463 mov ($dat,$ido,4),%r10d
464 add ($inp,$len,1),$idx#b
467 mov ($dat,$idx,4),%r11d
469 mov %r10d,($dat,$idx,4)
470 mov %r11d,($dat,$ido,4)
485 mov ($dat,$ido),%r10b
486 add ($inp,$len),$idx#b
489 mov ($dat,$idx),%r11b
493 mov %r10b,($dat,$idx)
494 mov %r11b,($dat,$ido)
505 .size RC4_set_key,.-RC4_set_key
508 .type RC4_options,\@abi-omnipotent
511 lea .Lopts(%rip),%rax
512 mov OPENSSL_ia32cap_P(%rip),%edx
526 .asciz "rc4(8x,char)"
527 .asciz "rc4(16x,int)"
528 .asciz "RC4 for x86_64, CRYPTOGAMS by <appro\@openssl.org>"
530 .size RC4_options,.-RC4_options
533 # EXCEPTION_DISPOSITION handler (EXCEPTION_RECORD *rec,ULONG64 frame,
534 # CONTEXT *context,DISPATCHER_CONTEXT *disp)
542 .extern __imp_RtlVirtualUnwind
543 .type stream_se_handler,\@abi-omnipotent
557 mov 120($context),%rax # pull context->Rax
558 mov 248($context),%rbx # pull context->Rip
560 lea .Lprologue(%rip),%r10
561 cmp %r10,%rbx # context->Rip<prologue label
564 mov 152($context),%rax # pull context->Rsp
566 lea .Lepilogue(%rip),%r10
567 cmp %r10,%rbx # context->Rip>=epilogue label
575 mov %rbx,144($context) # restore context->Rbx
576 mov %r12,216($context) # restore context->R12
577 mov %r13,224($context) # restore context->R13
582 mov %rax,152($context) # restore context->Rsp
583 mov %rsi,168($context) # restore context->Rsi
584 mov %rdi,176($context) # restore context->Rdi
586 jmp .Lcommon_seh_exit
587 .size stream_se_handler,.-stream_se_handler
589 .type key_se_handler,\@abi-omnipotent
603 mov 152($context),%rax # pull context->Rsp
606 mov %rsi,168($context) # restore context->Rsi
607 mov %rdi,176($context) # restore context->Rdi
611 mov 40($disp),%rdi # disp->ContextRecord
612 mov $context,%rsi # context
613 mov \$154,%ecx # sizeof(CONTEXT)
614 .long 0xa548f3fc # cld; rep movsq
617 xor %rcx,%rcx # arg1, UNW_FLAG_NHANDLER
618 mov 8(%rsi),%rdx # arg2, disp->ImageBase
619 mov 0(%rsi),%r8 # arg3, disp->ControlPc
620 mov 16(%rsi),%r9 # arg4, disp->FunctionEntry
621 mov 40(%rsi),%r10 # disp->ContextRecord
622 lea 56(%rsi),%r11 # &disp->HandlerData
623 lea 24(%rsi),%r12 # &disp->EstablisherFrame
624 mov %r10,32(%rsp) # arg5
625 mov %r11,40(%rsp) # arg6
626 mov %r12,48(%rsp) # arg7
627 mov %rcx,56(%rsp) # arg8, (NULL)
628 call *__imp_RtlVirtualUnwind(%rip)
630 mov \$1,%eax # ExceptionContinueSearch
642 .size key_se_handler,.-key_se_handler
650 .rva .LSEH_begin_RC4_set_key
651 .rva .LSEH_end_RC4_set_key
652 .rva .LSEH_info_RC4_set_key
658 .rva stream_se_handler
659 .LSEH_info_RC4_set_key:
667 if ($reg =~ /%r[0-9]+/) { $reg .= $conv; }
668 elsif ($conv eq "b") { $reg =~ s/%[er]([^x]+)x?/%$1l/; }
669 elsif ($conv eq "w") { $reg =~ s/%[er](.+)/%$1/; }
670 elsif ($conv eq "d") { $reg =~ s/%[er](.+)/%e$1/; }
674 $code =~ s/(%[a-z0-9]+)#([bwd])/reg_part($1,$2)/gem;
675 $code =~ s/\`([^\`]*)\`/eval $1/gem;