3 # ====================================================================
4 # [Re]written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
5 # project. The module is, however, dual licensed under OpenSSL and
6 # CRYPTOGAMS licenses depending on where you obtain it. For further
7 # details see http://www.openssl.org/~appro/cryptogams/.
8 # ====================================================================
10 # At some point it became apparent that the original SSLeay RC4
11 # assembler implementation performs suboptimally on latest IA-32
12 # microarchitectures. After re-tuning performance has changed as
20 # (*) This number is actually a trade-off:-) It's possible to
21 # achieve +72%, but at the cost of -48% off PIII performance.
22 # In other words code performing further 13% faster on AMD
23 # would perform almost 2 times slower on Intel PIII...
24 # For reference! This code delivers ~80% of rc4-amd64.pl
25 # performance on the same Opteron machine.
26 # (**) This number requires compressed key schedule set up by
27 # RC4_set_key [see commentary below for further details].
29 # <appro@fy.chalmers.se>
33 # Optimize for Core2 and Westmere [and incidentally Opteron]. Current
34 # performance in cycles per processed byte (less is better) is:
36 # Pentium 10.2 # original numbers
40 # Opteron 6.4/+14% # new MMX numbers
42 # Westmere 5.5/+80%(**)
45 # (*) PIII can actually deliver 6.6 cycles per byte with MMX code,
46 # but this specific code performs poorly on Core2. And vice
47 # versa, below MMX/SSE code delivering 5.8/7.1 on Core2 performs
48 # poorly on PIII, at 8.0/14.5:-( As PIII is not a "hot" CPU
49 # [anymore], I chose to discard PIII-specific code path and opt
50 # for original IALU-only code, which is why MMX/SSE code path
51 # is guarded by SSE2 bit (see below), not MMX/SSE.
52 # (**) Performance vs. block size on Core2 and Westmere had a maximum
53 # at ... 64 bytes block size. And it was quite a maximum, 40-60%
54 # in comparison to largest 8KB block size. Above improvement
55 # coefficients are for the largest block size.
57 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
58 push(@INC,"${dir}","${dir}../../perlasm");
61 &asm_init($ARGV[0],"rc4-586.pl");
73 my $func = ($i==0)?*mov:*or;
75 &add (&LB($yy),&LB($tx));
76 &mov ($ty,&DWP(0,$dat,$yy,4));
77 &mov (&DWP(0,$dat,$yy,4),$tx);
78 &mov (&DWP(0,$dat,$xx,4),$ty);
82 &ror ($out,8) if ($i!=0);
84 &mov ($tx,&DWP(0,$dat,$xx,4));
86 &mov ($tx,&wparam(3)); # reload [re-biased] out
88 &$func ($out,&DWP(0,$dat,$ty,4));
92 # >20% faster on Atom and Sandy Bridge[!], 8% faster on Opteron,
93 # but ~40% slower on Core2 and Westmere... Attempt to add movz
94 # brings down Opteron by 25%, Atom and Sandy Bridge by 15%, yet
95 # on Core2 with movz it's almost 20% slower than below alternative
96 # code... Yes, it's a total mess...
98 $RC4_loop_mmx = sub { # SSE actually...
101 my $mm=$i<=0?"mm0":"mm".($i&1);
103 &add (&LB($yy),&LB($tx));
104 &lea (@XX[1],&DWP(1,@XX[0]));
105 &pxor ("mm2","mm0") if ($i==0);
106 &psllq ("mm1",8) if ($i==0);
108 &pxor ("mm0","mm0") if ($i<=0);
109 &mov ($ty,&DWP(0,$dat,$yy,4));
110 &mov (&DWP(0,$dat,$yy,4),$tx);
111 &pxor ("mm1","mm2") if ($i==0);
112 &mov (&DWP(0,$dat,$XX[0],4),$ty);
113 &add (&LB($ty),&LB($tx));
114 &movd (@XX[0],"mm7") if ($i==0);
115 &mov ($tx,&DWP(0,$dat,@XX[1],4));
116 &pxor ("mm1","mm1") if ($i==1);
117 &movq ("mm2",&QWP(0,$inp)) if ($i==1);
118 &movq (&QWP(-8,(@XX[0],$inp)),"mm1") if ($i==0);
119 &pinsrw ($mm,&DWP(0,$dat,$ty,4),$j);
121 push (@XX,shift(@XX)) if ($i>=0);
124 # Using pinsrw here improves performane on Intel CPUs by 2-3%, but
125 # brings down AMD by 7%...
126 $RC4_loop_mmx = sub {
130 &movz ($yy,&LB($yy)); # (*)
131 &psllq ("mm1",8*(($i-1)&7)) if (abs($i)!=1);
132 &mov ($ty,&DWP(0,$dat,$yy,4));
133 &mov (&DWP(0,$dat,$yy,4),$tx);
134 &mov (&DWP(0,$dat,$xx,4),$ty);
137 &movz ($xx,&LB($xx)); # (*)
138 &movz ($ty,&LB($ty)); # (*)
139 &pxor ("mm2",$i==1?"mm0":"mm1") if ($i>=0);
140 &movq ("mm0",&QWP(0,$inp)) if ($i<=0);
141 &movq (&QWP(-8,($out,$inp)),"mm2") if ($i==0);
142 &mov ($tx,&DWP(0,$dat,$xx,4));
143 &movd ($i>0?"mm1":"mm2",&DWP(0,$dat,$ty,4));
145 # (*) This is the key to Core2 and Westmere performance.
146 # Whithout movz out-of-order execution logic confuses
147 # itself and fails to reorder loads and stores. Problem
148 # appears to be fixed in Sandy Bridge...
152 &external_label("OPENSSL_ia32cap_P");
154 # void RC4(RC4_KEY *key,size_t len,const unsigned char *inp,unsigned char *out);
155 &function_begin("RC4");
156 &mov ($dat,&wparam(0)); # load key schedule pointer
157 &mov ($ty, &wparam(1)); # load len
158 &mov ($inp,&wparam(2)); # load inp
159 &mov ($out,&wparam(3)); # load out
161 &xor ($xx,$xx); # avoid partial register stalls
164 &cmp ($ty,0); # safety net
165 &je (&label("abort"));
167 &mov (&LB($xx),&BP(0,$dat)); # load key->x
168 &mov (&LB($yy),&BP(4,$dat)); # load key->y
171 &lea ($tx,&DWP(0,$inp,$ty));
172 &sub ($out,$inp); # re-bias out
173 &mov (&wparam(1),$tx); # save input+len
177 # detect compressed key schedule...
178 &cmp (&DWP(256,$dat),-1);
179 &je (&label("RC4_CHAR"));
181 &mov ($tx,&DWP(0,$dat,$xx,4));
183 &and ($ty,-4); # how many 4-byte chunks?
184 &jz (&label("loop1"));
187 &mov (&wparam(3),$out); # $out as accumulator in these loops
188 &jz (&label("go4loop4"));
190 &picmeup($out,"OPENSSL_ia32cap_P");
191 &bt (&DWP(0,$out),26); # check SSE2 bit [could have been MMX]
192 &jnc (&label("go4loop4"));
194 &mov ($out,&wparam(3)) if (!$alt);
195 &movd ("mm7",&wparam(3)) if ($alt);
197 &lea ($ty,&DWP(-8,$inp,$ty));
198 &mov (&DWP(-4,$dat),$ty); # save input+(len/8)*8-8
201 &jmp(&label("loop_mmx_enter"));
203 &set_label("loop_mmx",16);
205 &set_label("loop_mmx_enter");
206 for ($i=1;$i<8;$i++) { &$RC4_loop_mmx($i); }
207 &cmp ($inp,&DWP(-4,$dat));
208 &lea ($inp,&DWP(8,$inp));
209 &jb (&label("loop_mmx"));
216 &movq (&QWP(-8,$out,$inp),"mm1");
220 &movq (&QWP(-8,$out,$inp),"mm2");
224 &cmp ($inp,&wparam(1)); # compare to input+len
225 &je (&label("done"));
226 &jmp (&label("loop1"));
228 &set_label("go4loop4",16);
229 &lea ($ty,&DWP(-4,$inp,$ty));
230 &mov (&wparam(2),$ty); # save input+(len/4)*4-4
233 for ($i=0;$i<4;$i++) { RC4_loop($i); }
235 &xor ($out,&DWP(0,$inp));
236 &cmp ($inp,&wparam(2)); # compare to input+(len/4)*4-4
237 &mov (&DWP(0,$tx,$inp),$out);# $tx holds re-biased out here
238 &lea ($inp,&DWP(4,$inp));
239 &mov ($tx,&DWP(0,$dat,$xx,4));
240 &jb (&label("loop4"));
242 &cmp ($inp,&wparam(1)); # compare to input+len
243 &je (&label("done"));
244 &mov ($out,&wparam(3)); # restore $out
246 &set_label("loop1",16);
247 &add (&LB($yy),&LB($tx));
248 &mov ($ty,&DWP(0,$dat,$yy,4));
249 &mov (&DWP(0,$dat,$yy,4),$tx);
250 &mov (&DWP(0,$dat,$xx,4),$ty);
254 &mov ($ty,&DWP(0,$dat,$ty,4));
255 &xor (&LB($ty),&BP(0,$inp));
256 &lea ($inp,&DWP(1,$inp));
257 &mov ($tx,&DWP(0,$dat,$xx,4));
258 &cmp ($inp,&wparam(1)); # compare to input+len
259 &mov (&BP(-1,$out,$inp),&LB($ty));
260 &jb (&label("loop1"));
262 &jmp (&label("done"));
264 # this is essentially Intel P4 specific codepath...
265 &set_label("RC4_CHAR",16);
266 &movz ($tx,&BP(0,$dat,$xx));
267 # strangely enough unrolled loop performs over 20% slower...
268 &set_label("cloop1");
269 &add (&LB($yy),&LB($tx));
270 &movz ($ty,&BP(0,$dat,$yy));
271 &mov (&BP(0,$dat,$yy),&LB($tx));
272 &mov (&BP(0,$dat,$xx),&LB($ty));
273 &add (&LB($ty),&LB($tx));
274 &movz ($ty,&BP(0,$dat,$ty));
276 &xor (&LB($ty),&BP(0,$inp));
277 &lea ($inp,&DWP(1,$inp));
278 &movz ($tx,&BP(0,$dat,$xx));
279 &cmp ($inp,&wparam(1));
280 &mov (&BP(-1,$out,$inp),&LB($ty));
281 &jb (&label("cloop1"));
285 &mov (&DWP(-4,$dat),$yy); # save key->y
286 &mov (&BP(-8,$dat),&LB($xx)); # save key->x
288 &function_end("RC4");
290 ########################################################################
298 # void RC4_set_key(RC4_KEY *key,int len,const unsigned char *data);
299 &function_begin("RC4_set_key");
300 &mov ($out,&wparam(0)); # load key
301 &mov ($idi,&wparam(1)); # load len
302 &mov ($inp,&wparam(2)); # load data
303 &picmeup($idx,"OPENSSL_ia32cap_P");
305 &lea ($out,&DWP(2*4,$out)); # &key->data
306 &lea ($inp,&DWP(0,$inp,$idi)); # $inp to point at the end
309 &mov (&DWP(-4,$out),$idi); # borrow key->y
311 &bt (&DWP(0,$idx),20); # check for bit#20
312 &jc (&label("c1stloop"));
314 &set_label("w1stloop",16);
315 &mov (&DWP(0,$out,"eax",4),"eax"); # key->data[i]=i;
316 &add (&LB("eax"),1); # i++;
317 &jnc (&label("w1stloop"));
322 &set_label("w2ndloop",16);
323 &mov ("eax",&DWP(0,$out,$ido,4));
324 &add (&LB($idx),&BP(0,$inp,$idi));
325 &add (&LB($idx),&LB("eax"));
327 &mov ("ebx",&DWP(0,$out,$idx,4));
328 &jnz (&label("wnowrap"));
329 &mov ($idi,&DWP(-4,$out));
330 &set_label("wnowrap");
331 &mov (&DWP(0,$out,$idx,4),"eax");
332 &mov (&DWP(0,$out,$ido,4),"ebx");
334 &jnc (&label("w2ndloop"));
335 &jmp (&label("exit"));
337 # Unlike all other x86 [and x86_64] implementations, Intel P4 core
338 # [including EM64T] was found to perform poorly with above "32-bit" key
339 # schedule, a.k.a. RC4_INT. Performance improvement for IA-32 hand-coded
340 # assembler turned out to be 3.5x if re-coded for compressed 8-bit one,
341 # a.k.a. RC4_CHAR! It's however inappropriate to just switch to 8-bit
342 # schedule for x86[_64], because non-P4 implementations suffer from
343 # significant performance losses then, e.g. PIII exhibits >2x
344 # deterioration, and so does Opteron. In order to assure optimal
345 # all-round performance, we detect P4 at run-time and set up compressed
346 # key schedule, which is recognized by RC4 procedure.
348 &set_label("c1stloop",16);
349 &mov (&BP(0,$out,"eax"),&LB("eax")); # key->data[i]=i;
350 &add (&LB("eax"),1); # i++;
351 &jnc (&label("c1stloop"));
357 &set_label("c2ndloop",16);
358 &mov (&LB("eax"),&BP(0,$out,$ido));
359 &add (&LB($idx),&BP(0,$inp,$idi));
360 &add (&LB($idx),&LB("eax"));
362 &mov (&LB("ebx"),&BP(0,$out,$idx));
363 &jnz (&label("cnowrap"));
364 &mov ($idi,&DWP(-4,$out));
365 &set_label("cnowrap");
366 &mov (&BP(0,$out,$idx),&LB("eax"));
367 &mov (&BP(0,$out,$ido),&LB("ebx"));
369 &jnc (&label("c2ndloop"));
371 &mov (&DWP(256,$out),-1); # mark schedule as compressed
375 &mov (&DWP(-8,$out),"eax"); # key->x=0;
376 &mov (&DWP(-4,$out),"eax"); # key->y=0;
377 &function_end("RC4_set_key");
379 # const char *RC4_options(void);
380 &function_begin_B("RC4_options");
381 &call (&label("pic_point"));
382 &set_label("pic_point");
384 &lea ("eax",&DWP(&label("opts")."-".&label("pic_point"),"eax"));
385 &picmeup("edx","OPENSSL_ia32cap_P");
386 &mov ("edx",&DWP(0,"edx"));
388 &jc (&label("1xchar"));
390 &jnc (&label("ret"));
393 &set_label("1xchar");
397 &set_label("opts",64);
398 &asciz ("rc4(4x,int)");
399 &asciz ("rc4(1x,char)");
400 &asciz ("rc4(8x,mmx)");
401 &asciz ("RC4 for x86, CRYPTOGAMS by <appro\@openssl.org>");
403 &function_end_B("RC4_options");