3 # ====================================================================
4 # [Re]written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
5 # project. The module is, however, dual licensed under OpenSSL and
6 # CRYPTOGAMS licenses depending on where you obtain it. For further
7 # details see http://www.openssl.org/~appro/cryptogams/.
8 # ====================================================================
10 # At some point it became apparent that the original SSLeay RC4
11 # assembler implementation performs suboptimally on latest IA-32
12 # microarchitectures. After re-tuning performance has changed as
20 # (*) This number is actually a trade-off:-) It's possible to
21 # achieve +72%, but at the cost of -48% off PIII performance.
22 # In other words code performing further 13% faster on AMD
23 # would perform almost 2 times slower on Intel PIII...
24 # For reference! This code delivers ~80% of rc4-amd64.pl
25 # performance on the same Opteron machine.
26 # (**) This number requires compressed key schedule set up by
27 # RC4_set_key [see commentary below for further details].
29 # <appro@fy.chalmers.se>
33 # Optimize for Core2 and Westmere [and incidentally Opteron]. Current
34 # performance in cycles per processed byte (less is better) and
35 # improvement relative to previous version of this module is:
37 # Pentium 10.2 # original numbers
41 # Opteron 6.1/+20% # new MMX numbers
43 # Westmere 5.1/+94%(**)
44 # Sandy Bridge 5.0/+8%
50 # (*) PIII can actually deliver 6.6 cycles per byte with MMX code,
51 # but this specific code performs poorly on Core2. And vice
52 # versa, below MMX/SSE code delivering 5.8/7.1 on Core2 performs
53 # poorly on PIII, at 8.0/14.5:-( As PIII is not a "hot" CPU
54 # [anymore], I chose to discard PIII-specific code path and opt
55 # for original IALU-only code, which is why MMX/SSE code path
56 # is guarded by SSE2 bit (see below), not MMX/SSE.
57 # (**) Performance vs. block size on Core2 and Westmere had a maximum
58 # at ... 64 bytes block size. And it was quite a maximum, 40-60%
59 # in comparison to largest 8KB block size. Above improvement
60 # coefficients are for the largest block size.
62 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
63 push(@INC,"${dir}","${dir}../../perlasm");
66 &asm_init($ARGV[0],"rc4-586.pl",$x86only = $ARGV[$#ARGV] eq "386");
78 my $func = ($i==0)?*mov:*or;
80 &add (&LB($yy),&LB($tx));
81 &mov ($ty,&DWP(0,$dat,$yy,4));
82 &mov (&DWP(0,$dat,$yy,4),$tx);
83 &mov (&DWP(0,$dat,$xx,4),$ty);
87 &ror ($out,8) if ($i!=0);
89 &mov ($tx,&DWP(0,$dat,$xx,4));
91 &mov ($tx,&wparam(3)); # reload [re-biased] out
93 &$func ($out,&DWP(0,$dat,$ty,4));
97 # >20% faster on Atom and Sandy Bridge[!], 8% faster on Opteron,
98 # but ~40% slower on Core2 and Westmere... Attempt to add movz
99 # brings down Opteron by 25%, Atom and Sandy Bridge by 15%, yet
100 # on Core2 with movz it's almost 20% slower than below alternative
101 # code... Yes, it's a total mess...
103 $RC4_loop_mmx = sub { # SSE actually...
106 my $mm=$i<=0?"mm0":"mm".($i&1);
108 &add (&LB($yy),&LB($tx));
109 &lea (@XX[1],&DWP(1,@XX[0]));
110 &pxor ("mm2","mm0") if ($i==0);
111 &psllq ("mm1",8) if ($i==0);
113 &pxor ("mm0","mm0") if ($i<=0);
114 &mov ($ty,&DWP(0,$dat,$yy,4));
115 &mov (&DWP(0,$dat,$yy,4),$tx);
116 &pxor ("mm1","mm2") if ($i==0);
117 &mov (&DWP(0,$dat,$XX[0],4),$ty);
118 &add (&LB($ty),&LB($tx));
119 &movd (@XX[0],"mm7") if ($i==0);
120 &mov ($tx,&DWP(0,$dat,@XX[1],4));
121 &pxor ("mm1","mm1") if ($i==1);
122 &movq ("mm2",&QWP(0,$inp)) if ($i==1);
123 &movq (&QWP(-8,(@XX[0],$inp)),"mm1") if ($i==0);
124 &pinsrw ($mm,&DWP(0,$dat,$ty,4),$j);
126 push (@XX,shift(@XX)) if ($i>=0);
129 # Using pinsrw here improves performane on Intel CPUs by 2-3%, but
130 # brings down AMD by 7%...
131 $RC4_loop_mmx = sub {
134 &add (&LB($yy),&LB($tx));
135 &psllq ("mm1",8*(($i-1)&7)) if (abs($i)!=1);
136 &mov ($ty,&DWP(0,$dat,$yy,4));
137 &mov (&DWP(0,$dat,$yy,4),$tx);
138 &mov (&DWP(0,$dat,$xx,4),$ty);
141 &movz ($xx,&LB($xx)); # (*)
142 &movz ($ty,&LB($ty)); # (*)
143 &pxor ("mm2",$i==1?"mm0":"mm1") if ($i>=0);
144 &movq ("mm0",&QWP(0,$inp)) if ($i<=0);
145 &movq (&QWP(-8,($out,$inp)),"mm2") if ($i==0);
146 &mov ($tx,&DWP(0,$dat,$xx,4));
147 &movd ($i>0?"mm1":"mm2",&DWP(0,$dat,$ty,4));
149 # (*) This is the key to Core2 and Westmere performance.
150 # Whithout movz out-of-order execution logic confuses
151 # itself and fails to reorder loads and stores. Problem
152 # appears to be fixed in Sandy Bridge...
156 &external_label("OPENSSL_ia32cap_P");
158 # void RC4(RC4_KEY *key,size_t len,const unsigned char *inp,unsigned char *out);
159 &function_begin("RC4");
160 &mov ($dat,&wparam(0)); # load key schedule pointer
161 &mov ($ty, &wparam(1)); # load len
162 &mov ($inp,&wparam(2)); # load inp
163 &mov ($out,&wparam(3)); # load out
165 &xor ($xx,$xx); # avoid partial register stalls
168 &cmp ($ty,0); # safety net
169 &je (&label("abort"));
171 &mov (&LB($xx),&BP(0,$dat)); # load key->x
172 &mov (&LB($yy),&BP(4,$dat)); # load key->y
175 &lea ($tx,&DWP(0,$inp,$ty));
176 &sub ($out,$inp); # re-bias out
177 &mov (&wparam(1),$tx); # save input+len
181 # detect compressed key schedule...
182 &cmp (&DWP(256,$dat),-1);
183 &je (&label("RC4_CHAR"));
185 &mov ($tx,&DWP(0,$dat,$xx,4));
187 &and ($ty,-4); # how many 4-byte chunks?
188 &jz (&label("loop1"));
190 &mov (&wparam(3),$out); # $out as accumulator in these loops
192 &jmp (&label("go4loop4"));
195 &jz (&label("go4loop4"));
197 &picmeup($out,"OPENSSL_ia32cap_P");
198 &bt (&DWP(0,$out),26); # check SSE2 bit [could have been MMX]
199 &jnc (&label("go4loop4"));
201 &mov ($out,&wparam(3)) if (!$alt);
202 &movd ("mm7",&wparam(3)) if ($alt);
204 &lea ($ty,&DWP(-8,$inp,$ty));
205 &mov (&DWP(-4,$dat),$ty); # save input+(len/8)*8-8
208 &jmp(&label("loop_mmx_enter"));
210 &set_label("loop_mmx",16);
212 &set_label("loop_mmx_enter");
213 for ($i=1;$i<8;$i++) { &$RC4_loop_mmx($i); }
215 &xor ($yy,$yy); # this is second key to Core2
216 &mov (&LB($yy),&LB($ty)); # and Westmere performance...
217 &cmp ($inp,&DWP(-4,$dat));
218 &lea ($inp,&DWP(8,$inp));
219 &jb (&label("loop_mmx"));
226 &movq (&QWP(-8,$out,$inp),"mm1");
230 &movq (&QWP(-8,$out,$inp),"mm2");
234 &cmp ($inp,&wparam(1)); # compare to input+len
235 &je (&label("done"));
236 &jmp (&label("loop1"));
239 &set_label("go4loop4",16);
240 &lea ($ty,&DWP(-4,$inp,$ty));
241 &mov (&wparam(2),$ty); # save input+(len/4)*4-4
244 for ($i=0;$i<4;$i++) { RC4_loop($i); }
246 &xor ($out,&DWP(0,$inp));
247 &cmp ($inp,&wparam(2)); # compare to input+(len/4)*4-4
248 &mov (&DWP(0,$tx,$inp),$out);# $tx holds re-biased out here
249 &lea ($inp,&DWP(4,$inp));
250 &mov ($tx,&DWP(0,$dat,$xx,4));
251 &jb (&label("loop4"));
253 &cmp ($inp,&wparam(1)); # compare to input+len
254 &je (&label("done"));
255 &mov ($out,&wparam(3)); # restore $out
257 &set_label("loop1",16);
258 &add (&LB($yy),&LB($tx));
259 &mov ($ty,&DWP(0,$dat,$yy,4));
260 &mov (&DWP(0,$dat,$yy,4),$tx);
261 &mov (&DWP(0,$dat,$xx,4),$ty);
265 &mov ($ty,&DWP(0,$dat,$ty,4));
266 &xor (&LB($ty),&BP(0,$inp));
267 &lea ($inp,&DWP(1,$inp));
268 &mov ($tx,&DWP(0,$dat,$xx,4));
269 &cmp ($inp,&wparam(1)); # compare to input+len
270 &mov (&BP(-1,$out,$inp),&LB($ty));
271 &jb (&label("loop1"));
273 &jmp (&label("done"));
275 # this is essentially Intel P4 specific codepath...
276 &set_label("RC4_CHAR",16);
277 &movz ($tx,&BP(0,$dat,$xx));
278 # strangely enough unrolled loop performs over 20% slower...
279 &set_label("cloop1");
280 &add (&LB($yy),&LB($tx));
281 &movz ($ty,&BP(0,$dat,$yy));
282 &mov (&BP(0,$dat,$yy),&LB($tx));
283 &mov (&BP(0,$dat,$xx),&LB($ty));
284 &add (&LB($ty),&LB($tx));
285 &movz ($ty,&BP(0,$dat,$ty));
287 &xor (&LB($ty),&BP(0,$inp));
288 &lea ($inp,&DWP(1,$inp));
289 &movz ($tx,&BP(0,$dat,$xx));
290 &cmp ($inp,&wparam(1));
291 &mov (&BP(-1,$out,$inp),&LB($ty));
292 &jb (&label("cloop1"));
296 &mov (&DWP(-4,$dat),$yy); # save key->y
297 &mov (&BP(-8,$dat),&LB($xx)); # save key->x
299 &function_end("RC4");
301 ########################################################################
309 # void RC4_set_key(RC4_KEY *key,int len,const unsigned char *data);
310 &function_begin("RC4_set_key");
311 &mov ($out,&wparam(0)); # load key
312 &mov ($idi,&wparam(1)); # load len
313 &mov ($inp,&wparam(2)); # load data
314 &picmeup($idx,"OPENSSL_ia32cap_P");
316 &lea ($out,&DWP(2*4,$out)); # &key->data
317 &lea ($inp,&DWP(0,$inp,$idi)); # $inp to point at the end
320 &mov (&DWP(-4,$out),$idi); # borrow key->y
322 &bt (&DWP(0,$idx),20); # check for bit#20
323 &jc (&label("c1stloop"));
325 &set_label("w1stloop",16);
326 &mov (&DWP(0,$out,"eax",4),"eax"); # key->data[i]=i;
327 &add (&LB("eax"),1); # i++;
328 &jnc (&label("w1stloop"));
333 &set_label("w2ndloop",16);
334 &mov ("eax",&DWP(0,$out,$ido,4));
335 &add (&LB($idx),&BP(0,$inp,$idi));
336 &add (&LB($idx),&LB("eax"));
338 &mov ("ebx",&DWP(0,$out,$idx,4));
339 &jnz (&label("wnowrap"));
340 &mov ($idi,&DWP(-4,$out));
341 &set_label("wnowrap");
342 &mov (&DWP(0,$out,$idx,4),"eax");
343 &mov (&DWP(0,$out,$ido,4),"ebx");
345 &jnc (&label("w2ndloop"));
346 &jmp (&label("exit"));
348 # Unlike all other x86 [and x86_64] implementations, Intel P4 core
349 # [including EM64T] was found to perform poorly with above "32-bit" key
350 # schedule, a.k.a. RC4_INT. Performance improvement for IA-32 hand-coded
351 # assembler turned out to be 3.5x if re-coded for compressed 8-bit one,
352 # a.k.a. RC4_CHAR! It's however inappropriate to just switch to 8-bit
353 # schedule for x86[_64], because non-P4 implementations suffer from
354 # significant performance losses then, e.g. PIII exhibits >2x
355 # deterioration, and so does Opteron. In order to assure optimal
356 # all-round performance, we detect P4 at run-time and set up compressed
357 # key schedule, which is recognized by RC4 procedure.
359 &set_label("c1stloop",16);
360 &mov (&BP(0,$out,"eax"),&LB("eax")); # key->data[i]=i;
361 &add (&LB("eax"),1); # i++;
362 &jnc (&label("c1stloop"));
368 &set_label("c2ndloop",16);
369 &mov (&LB("eax"),&BP(0,$out,$ido));
370 &add (&LB($idx),&BP(0,$inp,$idi));
371 &add (&LB($idx),&LB("eax"));
373 &mov (&LB("ebx"),&BP(0,$out,$idx));
374 &jnz (&label("cnowrap"));
375 &mov ($idi,&DWP(-4,$out));
376 &set_label("cnowrap");
377 &mov (&BP(0,$out,$idx),&LB("eax"));
378 &mov (&BP(0,$out,$ido),&LB("ebx"));
380 &jnc (&label("c2ndloop"));
382 &mov (&DWP(256,$out),-1); # mark schedule as compressed
386 &mov (&DWP(-8,$out),"eax"); # key->x=0;
387 &mov (&DWP(-4,$out),"eax"); # key->y=0;
388 &function_end("RC4_set_key");
390 # const char *RC4_options(void);
391 &function_begin_B("RC4_options");
392 &call (&label("pic_point"));
393 &set_label("pic_point");
395 &lea ("eax",&DWP(&label("opts")."-".&label("pic_point"),"eax"));
396 &picmeup("edx","OPENSSL_ia32cap_P");
397 &mov ("edx",&DWP(0,"edx"));
399 &jc (&label("1xchar"));
401 &jnc (&label("ret"));
404 &set_label("1xchar");
408 &set_label("opts",64);
409 &asciz ("rc4(4x,int)");
410 &asciz ("rc4(1x,char)");
411 &asciz ("rc4(8x,mmx)");
412 &asciz ("RC4 for x86, CRYPTOGAMS by <appro\@openssl.org>");
414 &function_end_B("RC4_options");