1 /* ====================================================================
2 * Copyright (c) 2015 The OpenSSL Project. All rights reserved.
4 * Rights for redistribution and usage in source and binary
5 * forms are granted according to the OpenSSL license.
9 * This module is meant to be used as template for non-x87 floating-
10 * point assembly modules. The template itself is x86_64-specific
11 * though, as it was debugged on x86_64. So that implementor would
12 * have to recognize platform-specific parts, UxTOy and inline asm,
13 * and act accordingly.
15 * Huh? x86_64-specific code as template for non-x87? Note seven, which
16 * is not a typo, but reference to 80-bit precision. This module on the
17 * other hand relies on 64-bit precision operations, which are default
18 * for x86_64 code. And since we are at it, just for sense of it,
19 * large-block performance in cycles per processed byte for *this* code
21 * gcc-4.8 icc-15.0 clang-3.4(*)
23 * Westmere 4.96 5.09 4.37
24 * Sandy Bridge 4.95 4.90 4.17
25 * Haswell 4.92 4.87 3.78
26 * Bulldozer 4.67 4.49 4.68
27 * VIA Nano 7.07 7.05 5.98
28 * Silvermont 10.6 9.61 12.6
30 * (*) clang managed to discover parallelism and deployed SIMD;
32 * And for range of other platforms with unspecified gcc versions:
47 #if !(defined(__GNUC__) && __GNUC__>=2)
48 # error "this is gcc-specific template"
53 typedef unsigned char u8;
54 typedef unsigned int u32;
55 typedef unsigned long long u64;
56 typedef union { double d; u64 u; } elem64;
58 #define TWO(p) ((double)(1ULL<<(p)))
61 #define TWO64 (TWO32*TWO(32))
62 #define TWO96 (TWO64*TWO(32))
63 #define TWO130 (TWO96*TWO(34))
65 #define EXP(p) ((1023ULL+(p))<<52)
67 #if defined(__x86_64__) || (defined(__PPC__) && defined(__LITTLE_ENDIAN__))
68 # define U8TOU32(p) (*(const u32 *)(p))
69 # define U32TO8(p,v) (*(u32 *)(p) = (v))
70 #elif defined(__PPC__)
71 # define U8TOU32(p) ({u32 ret; asm ("lwbrx %0,0,%1":"=r"(ret):"b"(p)); ret; })
72 # define U32TO8(p,v) asm ("stwbrx %0,0,%1"::"r"(v),"b"(p):"memory")
73 #elif defined(__s390x__)
74 # define U8TOU32(p) ({u32 ret; asm ("lrv %0,%1":"=d"(ret):"m"(*(u32 *)(p))); ret; })
75 # define U32TO8(p,v) asm ("strv %1,%0":"=m"(*(u32 *)(p)):"d"(v))
79 # define U8TOU32(p) ((u32)(p)[0] | (u32)(p)[1]<<8 | \
80 (u32)(p)[2]<<16 | (u32)(p)[3]<<24 )
83 # define U32TO8(p,v) ((p)[0] = (u8)(v), (p)[1] = (u8)((v)>>8), \
84 (p)[2] = (u8)((v)>>16), (p)[3] = (u8)((v)>>24) )
93 /* "round toward zero (truncate), mask all exceptions" */
94 #if defined(__x86_64__)
95 static const u32 mxcsr = 0x7f80;
96 #elif defined(__PPC__)
97 static const u64 one = 1;
98 #elif defined(__s390x__)
99 static const u32 fpc = 1;
100 #elif defined(__sparc__)
101 static const u64 fsr = 1ULL<<30;
103 #error "unrecognized platform"
106 int poly1305_init(void *ctx, const unsigned char key[16])
108 poly1305_internal *st = (poly1305_internal *) ctx;
109 elem64 r0, r1, r2, r3;
113 st->h[0].d = TWO(52)*TWO0;
114 st->h[1].d = TWO(52)*TWO32;
115 st->h[2].d = TWO(52)*TWO64;
116 st->h[3].d = TWO(52)*TWO96;
118 st->h[0].u = EXP(52+0);
119 st->h[1].u = EXP(52+32);
120 st->h[2].u = EXP(52+64);
121 st->h[3].u = EXP(52+96);
126 * set "truncate" rounding mode
128 #if defined(__x86_64__)
131 asm volatile ("stmxcsr %0":"=m"(mxcsr_orig));
132 asm volatile ("ldmxcsr %0"::"m"(mxcsr));
133 #elif defined(__PPC__)
134 double fpscr_orig, fpscr = *(double *)&one;
136 asm volatile ("mffs %0":"=f"(fpscr_orig));
137 asm volatile ("mtfsf 255,%0"::"f"(fpscr));
138 #elif defined(__s390x__)
141 asm volatile ("stfpc %0":"=m"(fpc_orig));
142 asm volatile ("lfpc %0"::"m"(fpc));
143 #elif defined(__sparc__)
146 asm volatile ("stx %%fsr,%0":"=m"(fsr_orig));
147 asm volatile ("ldx %0,%%fsr"::"m"(fsr));
150 /* r &= 0xffffffc0ffffffc0ffffffc0fffffff */
151 r0.u = EXP(52+0) | (U8TOU32(&key[0]) & 0x0fffffff);
152 r1.u = EXP(52+32) | (U8TOU32(&key[4]) & 0x0ffffffc);
153 r2.u = EXP(52+64) | (U8TOU32(&key[8]) & 0x0ffffffc);
154 r3.u = EXP(52+96) | (U8TOU32(&key[12]) & 0x0ffffffc);
156 st->r[0] = r0.d - TWO(52)*TWO0;
157 st->r[2] = r1.d - TWO(52)*TWO32;
158 st->r[4] = r2.d - TWO(52)*TWO64;
159 st->r[6] = r3.d - TWO(52)*TWO96;
161 st->s[0] = st->r[2] * (5.0/TWO130);
162 st->s[2] = st->r[4] * (5.0/TWO130);
163 st->s[4] = st->r[6] * (5.0/TWO130);
166 * base 2^32 -> base 2^16
168 st->r[1] = (st->r[0] + TWO(52)*TWO(16)*TWO0) -
169 TWO(52)*TWO(16)*TWO0;
170 st->r[0] -= st->r[1];
172 st->r[3] = (st->r[2] + TWO(52)*TWO(16)*TWO32) -
173 TWO(52)*TWO(16)*TWO32;
174 st->r[2] -= st->r[3];
176 st->r[5] = (st->r[4] + TWO(52)*TWO(16)*TWO64) -
177 TWO(52)*TWO(16)*TWO64;
178 st->r[4] -= st->r[5];
180 st->r[7] = (st->r[6] + TWO(52)*TWO(16)*TWO96) -
181 TWO(52)*TWO(16)*TWO96;
182 st->r[6] -= st->r[7];
184 st->s[1] = (st->s[0] + TWO(52)*TWO(16)*TWO0/TWO96) -
185 TWO(52)*TWO(16)*TWO0/TWO96;
186 st->s[0] -= st->s[1];
188 st->s[3] = (st->s[2] + TWO(52)*TWO(16)*TWO32/TWO96) -
189 TWO(52)*TWO(16)*TWO32/TWO96;
190 st->s[2] -= st->s[3];
192 st->s[5] = (st->s[4] + TWO(52)*TWO(16)*TWO64/TWO96) -
193 TWO(52)*TWO(16)*TWO64/TWO96;
194 st->s[4] -= st->s[5];
197 * restore original FPU control register
199 #if defined(__x86_64__)
200 asm volatile ("ldmxcsr %0"::"m"(mxcsr_orig));
201 #elif defined(__PPC__)
202 asm volatile ("mtfsf 255,%0"::"f"(fpscr_orig));
203 #elif defined(__s390x__)
204 asm volatile ("lfpc %0"::"m"(fpc_orig));
205 #elif defined(__sparc__)
206 asm volatile ("ldx %0,%%fsr"::"m"(fsr_orig));
213 void poly1305_blocks(void *ctx, const unsigned char *inp, size_t len,
216 poly1305_internal *st = (poly1305_internal *)ctx;
217 elem64 in0, in1, in2, in3;
218 u64 pad = (u64)padbit<<32;
220 double x0, x1, x2, x3;
221 double h0lo, h0hi, h1lo, h1hi, h2lo, h2hi, h3lo, h3hi;
222 double c0lo, c0hi, c1lo, c1hi, c2lo, c2hi, c3lo, c3hi;
224 const double r0lo = st->r[0];
225 const double r0hi = st->r[1];
226 const double r1lo = st->r[2];
227 const double r1hi = st->r[3];
228 const double r2lo = st->r[4];
229 const double r2hi = st->r[5];
230 const double r3lo = st->r[6];
231 const double r3hi = st->r[7];
233 const double s1lo = st->s[0];
234 const double s1hi = st->s[1];
235 const double s2lo = st->s[2];
236 const double s2hi = st->s[3];
237 const double s3lo = st->s[4];
238 const double s3hi = st->s[5];
241 * set "truncate" rounding mode
243 #if defined(__x86_64__)
246 asm volatile ("stmxcsr %0":"=m"(mxcsr_orig));
247 asm volatile ("ldmxcsr %0"::"m"(mxcsr));
248 #elif defined(__PPC__)
249 double fpscr_orig, fpscr = *(double *)&one;
251 asm volatile ("mffs %0":"=f"(fpscr_orig));
252 asm volatile ("mtfsf 255,%0"::"f"(fpscr));
253 #elif defined(__s390x__)
256 asm volatile ("stfpc %0":"=m"(fpc_orig));
257 asm volatile ("lfpc %0"::"m"(fpc));
258 #elif defined(__sparc__)
261 asm volatile ("stx %%fsr,%0":"=m"(fsr_orig));
262 asm volatile ("ldx %0,%%fsr"::"m"(fsr));
266 * load base 2^32 and de-bias
268 h0lo = st->h[0].d - TWO(52)*TWO0;
269 h1lo = st->h[1].d - TWO(52)*TWO32;
270 h2lo = st->h[2].d - TWO(52)*TWO64;
271 h3lo = st->h[3].d - TWO(52)*TWO96;
279 in0.u = EXP(52+0) | U8TOU32(&inp[0]);
280 in1.u = EXP(52+32) | U8TOU32(&inp[4]);
281 in2.u = EXP(52+64) | U8TOU32(&inp[8]);
282 in3.u = EXP(52+96) | U8TOU32(&inp[12]) | pad;
284 x0 = in0.d - TWO(52)*TWO0;
285 x1 = in1.d - TWO(52)*TWO32;
286 x2 = in2.d - TWO(52)*TWO64;
287 x3 = in3.d - TWO(52)*TWO96;
298 in0.u = EXP(52+0) | U8TOU32(&inp[0]);
299 in1.u = EXP(52+32) | U8TOU32(&inp[4]);
300 in2.u = EXP(52+64) | U8TOU32(&inp[8]);
301 in3.u = EXP(52+96) | U8TOU32(&inp[12]) | pad;
303 x0 = in0.d - TWO(52)*TWO0;
304 x1 = in1.d - TWO(52)*TWO32;
305 x2 = in2.d - TWO(52)*TWO64;
306 x3 = in3.d - TWO(52)*TWO96;
309 * note that there are multiple ways to accumulate input, e.g.
310 * one can as well accumulate to h0lo-h1lo-h1hi-h2hi...
318 * carries that cross 32n-bit (and 130-bit) boundaries
320 c0lo = (h0lo + TWO(52)*TWO32) - TWO(52)*TWO32;
321 c1lo = (h1lo + TWO(52)*TWO64) - TWO(52)*TWO64;
322 c2lo = (h2lo + TWO(52)*TWO96) - TWO(52)*TWO96;
323 c3lo = (h3lo + TWO(52)*TWO130) - TWO(52)*TWO130;
325 c0hi = (h0hi + TWO(52)*TWO32) - TWO(52)*TWO32;
326 c1hi = (h1hi + TWO(52)*TWO64) - TWO(52)*TWO64;
327 c2hi = (h2hi + TWO(52)*TWO96) - TWO(52)*TWO96;
328 c3hi = (h3hi + TWO(52)*TWO130) - TWO(52)*TWO130;
331 * base 2^48 -> base 2^32 with last reduction step
333 x1 = (h1lo - c1lo) + c0lo;
334 x2 = (h2lo - c2lo) + c1lo;
335 x3 = (h3lo - c3lo) + c2lo;
336 x0 = (h0lo - c0lo) + c3lo * (5.0/TWO130);
338 x1 += (h1hi - c1hi) + c0hi;
339 x2 += (h2hi - c2hi) + c1hi;
340 x3 += (h3hi - c3hi) + c2hi;
341 x0 += (h0hi - c0hi) + c3hi * (5.0/TWO130);
347 * base 2^32 * base 2^16 = base 2^48
349 h0lo = s3lo * x1 + s2lo * x2 + s1lo * x3 + r0lo * x0;
350 h1lo = r0lo * x1 + s3lo * x2 + s2lo * x3 + r1lo * x0;
351 h2lo = r1lo * x1 + r0lo * x2 + s3lo * x3 + r2lo * x0;
352 h3lo = r2lo * x1 + r1lo * x2 + r0lo * x3 + r3lo * x0;
354 h0hi = s3hi * x1 + s2hi * x2 + s1hi * x3 + r0hi * x0;
355 h1hi = r0hi * x1 + s3hi * x2 + s2hi * x3 + r1hi * x0;
356 h2hi = r1hi * x1 + r0hi * x2 + s3hi * x3 + r2hi * x0;
357 h3hi = r2hi * x1 + r1hi * x2 + r0hi * x3 + r3hi * x0;
365 * carries that cross 32n-bit (and 130-bit) boundaries
367 c0lo = (h0lo + TWO(52)*TWO32) - TWO(52)*TWO32;
368 c1lo = (h1lo + TWO(52)*TWO64) - TWO(52)*TWO64;
369 c2lo = (h2lo + TWO(52)*TWO96) - TWO(52)*TWO96;
370 c3lo = (h3lo + TWO(52)*TWO130) - TWO(52)*TWO130;
372 c0hi = (h0hi + TWO(52)*TWO32) - TWO(52)*TWO32;
373 c1hi = (h1hi + TWO(52)*TWO64) - TWO(52)*TWO64;
374 c2hi = (h2hi + TWO(52)*TWO96) - TWO(52)*TWO96;
375 c3hi = (h3hi + TWO(52)*TWO130) - TWO(52)*TWO130;
378 * base 2^48 -> base 2^32 with last reduction step
380 x1 = (h1lo - c1lo) + c0lo;
381 x2 = (h2lo - c2lo) + c1lo;
382 x3 = (h3lo - c3lo) + c2lo;
383 x0 = (h0lo - c0lo) + c3lo * (5.0/TWO130);
385 x1 += (h1hi - c1hi) + c0hi;
386 x2 += (h2hi - c2hi) + c1hi;
387 x3 += (h3hi - c3hi) + c2hi;
388 x0 += (h0hi - c0hi) + c3hi * (5.0/TWO130);
391 * store base 2^32, with bias
393 st->h[1].d = x1 + TWO(52)*TWO32;
394 st->h[2].d = x2 + TWO(52)*TWO64;
395 st->h[3].d = x3 + TWO(52)*TWO96;
396 st->h[0].d = x0 + TWO(52)*TWO0;
399 * restore original FPU control register
401 #if defined(__x86_64__)
402 asm volatile ("ldmxcsr %0"::"m"(mxcsr_orig));
403 #elif defined(__PPC__)
404 asm volatile ("mtfsf 255,%0"::"f"(fpscr_orig));
405 #elif defined(__s390x__)
406 asm volatile ("lfpc %0"::"m"(fpc_orig));
407 #elif defined(__sparc__)
408 asm volatile ("ldx %0,%%fsr"::"m"(fsr_orig));
412 void poly1305_emit(void *ctx, unsigned char mac[16], const u32 nonce[4])
414 poly1305_internal *st = (poly1305_internal *) ctx;
415 u64 h0, h1, h2, h3, h4;
416 u32 g0, g1, g2, g3, g4;
421 * thanks to bias masking exponent gives integer result
423 h0 = st->h[0].u & 0x000fffffffffffffULL;
424 h1 = st->h[1].u & 0x000fffffffffffffULL;
425 h2 = st->h[2].u & 0x000fffffffffffffULL;
426 h3 = st->h[3].u & 0x000fffffffffffffULL;
429 * can be partially reduced, so reduce...
431 h4 = h3>>32; h3 &= 0xffffffffU;
437 h1 += h0>>32; h0 &= 0xffffffffU;
438 h2 += h1>>32; h1 &= 0xffffffffU;
439 h3 += h2>>32; h2 &= 0xffffffffU;
442 g0 = (u32)(t = h0 + 5);
443 g1 = (u32)(t = h1 + (t >> 32));
444 g2 = (u32)(t = h2 + (t >> 32));
445 g3 = (u32)(t = h3 + (t >> 32));
446 g4 = h4 + (u32)(t >> 32);
448 /* if there was carry, select g0-g3 */
449 mask = 0 - (g4 >> 2);
460 /* mac = (h + nonce) % (2^128) */
461 g0 = (u32)(t = (u64)g0 + nonce[0]);
462 g1 = (u32)(t = (u64)g1 + (t >> 32) + nonce[1]);
463 g2 = (u32)(t = (u64)g2 + (t >> 32) + nonce[2]);
464 g3 = (u32)(t = (u64)g3 + (t >> 32) + nonce[3]);
469 U32TO8(mac + 12, g3);