3 # ====================================================================
4 # Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
5 # project. The module is, however, dual licensed under OpenSSL and
6 # CRYPTOGAMS licenses depending on where you obtain it. For further
7 # details see http://www.openssl.org/~appro/cryptogams/.
8 # ====================================================================
10 # IALU(*)/gcc-4.4 NEON
12 # ARM11xx(ARMv6) 7.78/+100% -
13 # Cortex-A5 6.35/+130% 3.00
14 # Cortex-A8 6.25/+115% 2.36
15 # Cortex-A9 5.10/+95% 2.55
16 # Cortex-A15 3.85/+85% 1.25(**)
17 # Snapdragon S4 5.70/+100% 1.48(**)
19 # (*) this is for -march=armv6, i.e. with bunch of ldrb loading data;
20 # (**) these are trade-off results, they can be improved by ~8% but at
21 # the cost of 15/12% regression on Cortex-A5/A7, it's even possible
22 # to improve Cortex-A9 result, but then A5/A7 loose more than 20%;
25 if ($flavour=~/\w[\w\-]*\.\w+$/) { $output=$flavour; undef $flavour; }
26 else { while (($output=shift) && ($output!~/\w[\w\-]*\.\w+$/)) {} }
28 if ($flavour && $flavour ne "void") {
29 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
30 ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
31 ( $xlate="${dir}../../perlasm/arm-xlate.pl" and -f $xlate) or
32 die "can't locate arm-xlate.pl";
34 open STDOUT,"| \"$^X\" $xlate $flavour $output";
36 open STDOUT,">$output";
39 ($ctx,$inp,$len,$padbit)=map("r$_",(0..3));
45 #if defined(__thumb2__)
53 .globl poly1305_blocks
55 .type poly1305_init,%function
63 str r3,[$ctx,#0] @ zero hash value
68 str r3,[$ctx,#36] @ is_base2_26
77 #if __ARM_MAX_ARCH__>=7
78 adr r11,.Lpoly1305_init
79 ldr r12,.LOPENSSL_armcap
84 and r3,r10,#-4 @ 0x0ffffffc
95 #if __ARM_MAX_ARCH__>=7
96 ldr r12,[r11,r12] @ OPENSSL_armcap_P
110 #if __ARM_MAX_ARCH__>=7
111 tst r12,#ARMV7_NEON @ check for NEON
113 adr r9,poly1305_blocks_neon
114 adr r11,poly1305_blocks
119 adr r12,poly1305_emit
120 adr r10,poly1305_emit_neon
129 addeq r12,r11,#(poly1305_emit-.Lpoly1305_init)
130 addne r12,r11,#(poly1305_emit_neon-.Lpoly1305_init)
131 addeq r11,r11,#(poly1305_blocks-.Lpoly1305_init)
132 addne r11,r11,#(poly1305_blocks_neon-.Lpoly1305_init)
135 orr r12,r12,#1 @ thumb-ify address
157 #if __ARM_MAX_ARCH__>=7
158 stmia r2,{r11,r12} @ fill functions table
169 moveq pc,lr @ be binary compatible with V4, yet
170 bx lr @ interoperable with Thumb ISA:-)
172 .size poly1305_init,.-poly1305_init
175 my ($h0,$h1,$h2,$h3,$h4,$r0,$r1,$r2,$r3)=map("r$_",(4..12));
176 my ($s1,$s2,$s3)=($r1,$r2,$r3);
179 .type poly1305_blocks,%function
182 stmdb sp!,{r3-r11,lr}
188 add $len,$len,$inp @ end pointer
191 ldmia $ctx,{$h0-$r3} @ load context
193 str $ctx,[sp,#12] @ offload stuff
203 ldrb r0,[lr],#16 @ load input
207 addhi $h4,$h4,#1 @ 1<<128
217 adds $h0,$h0,r3 @ accumulate input
239 str lr,[sp,#8] @ offload input pointer
241 add $s1,$r1,$r1,lsr#2
244 ldr r0,[lr],#16 @ load input
248 addhi $h4,$h4,#1 @ padbit
258 adds $h0,$h0,r0 @ accumulate input
259 str lr,[sp,#8] @ offload input pointer
261 add $s1,$r1,$r1,lsr#2
264 add $s2,$r2,$r2,lsr#2
266 add $s3,$r3,$r3,lsr#2
273 ldr $r1,[sp,#20] @ reload $r1
279 str r0,[sp,#0] @ future $h0
281 ldr $r2,[sp,#24] @ reload $r2
282 adds r2,r2,r1 @ d1+=d0>>32
284 adc lr,r3,#0 @ future $h2
285 str r2,[sp,#4] @ future $h1
290 ldr $r3,[sp,#28] @ reload $r3
302 adds $h2,lr,r0 @ d2+=d1>>32
303 ldr lr,[sp,#8] @ reload input pointer
305 adds $h3,r2,r1 @ d3+=d2>>32
306 ldr r0,[sp,#16] @ reload end pointer
308 add $h4,$h4,r3 @ h4+=d3>>32
312 add r1,r1,r1,lsr#2 @ *=5
319 cmp r0,lr @ done yet?
324 stmia $ctx,{$h0-$h4} @ store the result
328 ldmia sp!,{r3-r11,pc}
330 ldmia sp!,{r3-r11,lr}
332 moveq pc,lr @ be binary compatible with V4, yet
333 bx lr @ interoperable with Thumb ISA:-)
335 .size poly1305_blocks,.-poly1305_blocks
339 my ($ctx,$mac,$nonce)=map("r$_",(0..2));
340 my ($h0,$h1,$h2,$h3,$h4,$g0,$g1,$g2,$g3)=map("r$_",(3..11));
344 .type poly1305_emit,%function
348 .Lpoly1305_emit_enter:
351 adds $g0,$h0,#5 @ compare to modulus
356 tst $g4,#4 @ did it carry/borrow?
433 moveq pc,lr @ be binary compatible with V4, yet
434 bx lr @ interoperable with Thumb ISA:-)
436 .size poly1305_emit,.-poly1305_emit
439 my ($R0,$R1,$S1,$R2,$S2,$R3,$S3,$R4,$S4) = map("d$_",(0..9));
440 my ($D0,$D1,$D2,$D3,$D4, $H0,$H1,$H2,$H3,$H4) = map("q$_",(5..14));
441 my ($T0,$T1,$MASK) = map("q$_",(15,4,0));
443 my ($in2,$zeros,$tbl0,$tbl1) = map("r$_",(4..7));
446 #if __ARM_MAX_ARCH__>=7
449 .type poly1305_init_neon,%function
452 ldr r4,[$ctx,#20] @ load key base 2^32
457 and r2,r4,#0x03ffffff @ base 2^32 -> base 2^26
465 and r3,r3,#0x03ffffff
466 and r4,r4,#0x03ffffff
467 and r5,r5,#0x03ffffff
469 vdup.32 $R0,r2 @ r^1 in both lanes
470 add r2,r3,r3,lsl#2 @ *5
483 mov $zeros,#2 @ counter
486 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
487 @ d0 = h0*r0 + h4*5*r1 + h3*5*r2 + h2*5*r3 + h1*5*r4
488 @ d1 = h1*r0 + h0*r1 + h4*5*r2 + h3*5*r3 + h2*5*r4
489 @ d2 = h2*r0 + h1*r1 + h0*r2 + h4*5*r3 + h3*5*r4
490 @ d3 = h3*r0 + h2*r1 + h1*r2 + h0*r3 + h4*5*r4
491 @ d4 = h4*r0 + h3*r1 + h2*r2 + h1*r3 + h0*r4
493 vmull.u32 $D0,$R0,${R0}[1]
494 vmull.u32 $D1,$R1,${R0}[1]
495 vmull.u32 $D2,$R2,${R0}[1]
496 vmull.u32 $D3,$R3,${R0}[1]
497 vmull.u32 $D4,$R4,${R0}[1]
499 vmlal.u32 $D0,$R4,${S1}[1]
500 vmlal.u32 $D1,$R0,${R1}[1]
501 vmlal.u32 $D2,$R1,${R1}[1]
502 vmlal.u32 $D3,$R2,${R1}[1]
503 vmlal.u32 $D4,$R3,${R1}[1]
505 vmlal.u32 $D0,$R3,${S2}[1]
506 vmlal.u32 $D1,$R4,${S2}[1]
507 vmlal.u32 $D3,$R1,${R2}[1]
508 vmlal.u32 $D2,$R0,${R2}[1]
509 vmlal.u32 $D4,$R2,${R2}[1]
511 vmlal.u32 $D0,$R2,${S3}[1]
512 vmlal.u32 $D3,$R0,${R3}[1]
513 vmlal.u32 $D1,$R3,${S3}[1]
514 vmlal.u32 $D2,$R4,${S3}[1]
515 vmlal.u32 $D4,$R1,${R3}[1]
517 vmlal.u32 $D3,$R4,${S4}[1]
518 vmlal.u32 $D0,$R1,${S4}[1]
519 vmlal.u32 $D1,$R2,${S4}[1]
520 vmlal.u32 $D2,$R3,${S4}[1]
521 vmlal.u32 $D4,$R0,${R4}[1]
523 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
524 @ lazy reduction as discussed in "NEON crypto" by D.J. Bernstein
527 @ H0>>+H1>>+H2>>+H3>>+H4
528 @ H3>>+H4>>*5+H0>>+H1
532 @ Result of multiplication of n-bit number by m-bit number is
533 @ n+m bits wide. However! Even though 2^n is a n+1-bit number,
534 @ m-bit number multiplied by 2^n is still n+m bits wide.
536 @ Sum of two n-bit numbers is n+1 bits wide, sum of three - n+2,
537 @ and so is sum of four. Sum of 2^m n-m-bit numbers and n-bit
538 @ one is n+1 bits wide.
540 @ >>+ denotes Hnext += Hn>>26, Hn &= 0x3ffffff. This means that
541 @ H0, H2, H3 are guaranteed to be 26 bits wide, while H1 and H4
542 @ can be 27. However! In cases when their width exceeds 26 bits
543 @ they are limited by 2^26+2^6. This in turn means that *sum*
544 @ of the products with these values can still be viewed as sum
545 @ of 52-bit numbers as long as the amount of addends is not a
546 @ power of 2. For example,
548 @ H4 = H4*R0 + H3*R1 + H2*R2 + H1*R3 + H0 * R4,
550 @ which can't be larger than 5 * (2^26 + 2^6) * (2^26 + 2^6), or
551 @ 5 * (2^52 + 2*2^32 + 2^12), which in turn is smaller than
552 @ 8 * (2^52) or 2^55. However, the value is then multiplied by
553 @ by 5, so we should be looking at 5 * 5 * (2^52 + 2^33 + 2^12),
554 @ which is less than 32 * (2^52) or 2^57. And when processing
555 @ data we are looking at triple as many addends...
557 @ In key setup procedure pre-reduced H0 is limited by 5*4+1 and
558 @ 5*H4 - by 5*5 52-bit addends, or 57 bits. But when hashing the
559 @ input H0 is limited by (5*4+1)*3 addends, or 58 bits, while
560 @ 5*H4 by 5*5*3, or 59[!] bits. How is this relevant? vmlal.u32
561 @ instruction accepts 2x32-bit input and writes 2x64-bit result.
562 @ This means that result of reduction have to be compressed upon
563 @ loop wrap-around. This can be done in the process of reduction
564 @ to minimize amount of instructions [as well as amount of
565 @ 128-bit instructions, which benefits low-end processors], but
566 @ one has to watch for H2 (which is narrower than H0) and 5*H4
567 @ not being wider than 58 bits, so that result of right shift
568 @ by 26 bits fits in 32 bits. This is also useful on x86,
569 @ because it allows to use paddd in place for paddq, which
570 @ benefits Atom, where paddq is ridiculously slow.
576 vadd.i64 $D4,$D4,$T0 @ h3 -> h4
577 vbic.i32 $D3#lo,#0xfc000000 @ &=0x03ffffff
578 vadd.i64 $D1,$D1,$T1 @ h0 -> h1
579 vbic.i32 $D0#lo,#0xfc000000
581 vshrn.u64 $T0#lo,$D4,#26
585 vadd.i64 $D2,$D2,$T1 @ h1 -> h2
586 vbic.i32 $D4#lo,#0xfc000000
587 vbic.i32 $D1#lo,#0xfc000000
589 vadd.i32 $D0#lo,$D0#lo,$T0#lo
590 vshl.u32 $T0#lo,$T0#lo,#2
591 vshrn.u64 $T1#lo,$D2,#26
593 vadd.i32 $D0#lo,$D0#lo,$T0#lo @ h4 -> h0
594 vadd.i32 $D3#lo,$D3#lo,$T1#lo @ h2 -> h3
595 vbic.i32 $D2#lo,#0xfc000000
597 vshr.u32 $T0#lo,$D0#lo,#26
598 vbic.i32 $D0#lo,#0xfc000000
599 vshr.u32 $T1#lo,$D3#lo,#26
600 vbic.i32 $D3#lo,#0xfc000000
601 vadd.i32 $D1#lo,$D1#lo,$T0#lo @ h0 -> h1
602 vadd.i32 $D4#lo,$D4#lo,$T1#lo @ h3 -> h4
604 subs $zeros,$zeros,#1
605 beq .Lsquare_break_neon
607 add $tbl0,$ctx,#(48+0*9*4)
608 add $tbl1,$ctx,#(48+1*9*4)
610 vtrn.32 $R0,$D0#lo @ r^2:r^1
616 vshl.u32 $S2,$R2,#2 @ *5
625 vst4.32 {${R0}[0],${R1}[0],${S1}[0],${R2}[0]},[$tbl0]!
626 vst4.32 {${R0}[1],${R1}[1],${S1}[1],${R2}[1]},[$tbl1]!
627 vst4.32 {${S2}[0],${R3}[0],${S3}[0],${R4}[0]},[$tbl0]!
628 vst4.32 {${S2}[1],${R3}[1],${S3}[1],${R4}[1]},[$tbl1]!
629 vst1.32 {${S4}[0]},[$tbl0,:32]
630 vst1.32 {${S4}[1]},[$tbl1,:32]
636 add $tbl0,$ctx,#(48+2*4*9)
637 add $tbl1,$ctx,#(48+3*4*9)
639 vmov $R0,$D0#lo @ r^4:r^3
640 vshl.u32 $S1,$D1#lo,#2 @ *5
642 vshl.u32 $S2,$D2#lo,#2
644 vshl.u32 $S3,$D3#lo,#2
646 vshl.u32 $S4,$D4#lo,#2
648 vadd.i32 $S1,$S1,$D1#lo
649 vadd.i32 $S2,$S2,$D2#lo
650 vadd.i32 $S3,$S3,$D3#lo
651 vadd.i32 $S4,$S4,$D4#lo
653 vst4.32 {${R0}[0],${R1}[0],${S1}[0],${R2}[0]},[$tbl0]!
654 vst4.32 {${R0}[1],${R1}[1],${S1}[1],${R2}[1]},[$tbl1]!
655 vst4.32 {${S2}[0],${R3}[0],${S3}[0],${R4}[0]},[$tbl0]!
656 vst4.32 {${S2}[1],${R3}[1],${S3}[1],${R4}[1]},[$tbl1]!
657 vst1.32 {${S4}[0]},[$tbl0]
658 vst1.32 {${S4}[1]},[$tbl1]
661 .size poly1305_init_neon,.-poly1305_init_neon
663 .type poly1305_blocks_neon,%function
665 poly1305_blocks_neon:
666 ldr ip,[$ctx,#36] @ is_base2_26
672 tst ip,ip @ is_base2_26?
677 vstmdb sp!,{d8-d15} @ ABI specification says so
679 tst ip,ip @ is_base2_26?
683 bl poly1305_init_neon
685 ldr r4,[$ctx,#0] @ load hash value base 2^32
691 and r2,r4,#0x03ffffff @ base 2^32 -> base 2^26
693 veor $D0#lo,$D0#lo,$D0#lo
696 veor $D1#lo,$D1#lo,$D1#lo
699 veor $D2#lo,$D2#lo,$D2#lo
702 veor $D3#lo,$D3#lo,$D3#lo
703 and r3,r3,#0x03ffffff
705 veor $D4#lo,$D4#lo,$D4#lo
706 and r4,r4,#0x03ffffff
708 and r5,r5,#0x03ffffff
709 str r1,[$ctx,#36] @ is_base2_26
723 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
726 veor $D0#lo,$D0#lo,$D0#lo
727 veor $D1#lo,$D1#lo,$D1#lo
728 veor $D2#lo,$D2#lo,$D2#lo
729 veor $D3#lo,$D3#lo,$D3#lo
730 veor $D4#lo,$D4#lo,$D4#lo
731 vld4.32 {$D0#lo[0],$D1#lo[0],$D2#lo[0],$D3#lo[0]},[$ctx]!
733 vld1.32 {$D4#lo[0]},[$ctx]
734 sub $ctx,$ctx,#16 @ rewind
738 mov $padbit,$padbit,lsl#24
742 vld4.32 {$H0#lo[0],$H1#lo[0],$H2#lo[0],$H3#lo[0]},[$inp]!
743 vmov.32 $H4#lo[0],$padbit
753 vsri.u32 $H4#lo,$H3#lo,#8 @ base 2^32 -> base 2^26
754 vshl.u32 $H3#lo,$H3#lo,#18
756 vsri.u32 $H3#lo,$H2#lo,#14
757 vshl.u32 $H2#lo,$H2#lo,#12
758 vadd.i32 $H4#hi,$H4#lo,$D4#lo @ add hash value and move to #hi
760 vbic.i32 $H3#lo,#0xfc000000
761 vsri.u32 $H2#lo,$H1#lo,#20
762 vshl.u32 $H1#lo,$H1#lo,#6
764 vbic.i32 $H2#lo,#0xfc000000
765 vsri.u32 $H1#lo,$H0#lo,#26
766 vadd.i32 $H3#hi,$H3#lo,$D3#lo
768 vbic.i32 $H0#lo,#0xfc000000
769 vbic.i32 $H1#lo,#0xfc000000
770 vadd.i32 $H2#hi,$H2#lo,$D2#lo
772 vadd.i32 $H0#hi,$H0#lo,$D0#lo
773 vadd.i32 $H1#hi,$H1#lo,$D1#lo
787 vmov.i32 $H4,#1<<24 @ padbit, yes, always
788 vld4.32 {$H0#lo,$H1#lo,$H2#lo,$H3#lo},[$inp] @ inp[0:1]
790 vld4.32 {$H0#hi,$H1#hi,$H2#hi,$H3#hi},[$in2] @ inp[2:3] (or 0)
793 addhi $tbl1,$ctx,#(48+1*9*4)
794 addhi $tbl0,$ctx,#(48+3*9*4)
802 vsri.u32 $H4,$H3,#8 @ base 2^32 -> base 2^26
808 vbic.i32 $H3,#0xfc000000
812 vbic.i32 $H2,#0xfc000000
815 vbic.i32 $H0,#0xfc000000
816 vbic.i32 $H1,#0xfc000000
820 vld4.32 {${R0}[1],${R1}[1],${S1}[1],${R2}[1]},[$tbl1]! @ load r^2
821 vld4.32 {${R0}[0],${R1}[0],${S1}[0],${R2}[0]},[$tbl0]! @ load r^4
822 vld4.32 {${S2}[1],${R3}[1],${S3}[1],${R4}[1]},[$tbl1]!
823 vld4.32 {${S2}[0],${R3}[0],${S3}[0],${R4}[0]},[$tbl0]!
828 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
829 @ ((inp[0]*r^4+inp[2]*r^2+inp[4])*r^4+inp[6]*r^2
830 @ ((inp[1]*r^4+inp[3]*r^2+inp[5])*r^3+inp[7]*r
831 @ \___________________/
832 @ ((inp[0]*r^4+inp[2]*r^2+inp[4])*r^4+inp[6]*r^2+inp[8])*r^2
833 @ ((inp[1]*r^4+inp[3]*r^2+inp[5])*r^4+inp[7]*r^2+inp[9])*r
834 @ \___________________/ \____________________/
836 @ Note that we start with inp[2:3]*r^2. This is because it
837 @ doesn't depend on reduction in previous iteration.
838 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
839 @ d4 = h4*r0 + h3*r1 + h2*r2 + h1*r3 + h0*r4
840 @ d3 = h3*r0 + h2*r1 + h1*r2 + h0*r3 + h4*5*r4
841 @ d2 = h2*r0 + h1*r1 + h0*r2 + h4*5*r3 + h3*5*r4
842 @ d1 = h1*r0 + h0*r1 + h4*5*r2 + h3*5*r3 + h2*5*r4
843 @ d0 = h0*r0 + h4*5*r1 + h3*5*r2 + h2*5*r3 + h1*5*r4
845 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
848 vadd.i32 $H2#lo,$H2#lo,$D2#lo @ accumulate inp[0:1]
849 vmull.u32 $D2,$H2#hi,${R0}[1]
850 vadd.i32 $H0#lo,$H0#lo,$D0#lo
851 vmull.u32 $D0,$H0#hi,${R0}[1]
852 vadd.i32 $H3#lo,$H3#lo,$D3#lo
853 vmull.u32 $D3,$H3#hi,${R0}[1]
854 vmlal.u32 $D2,$H1#hi,${R1}[1]
855 vadd.i32 $H1#lo,$H1#lo,$D1#lo
856 vmull.u32 $D1,$H1#hi,${R0}[1]
858 vadd.i32 $H4#lo,$H4#lo,$D4#lo
859 vmull.u32 $D4,$H4#hi,${R0}[1]
861 vmlal.u32 $D0,$H4#hi,${S1}[1]
864 vmlal.u32 $D3,$H2#hi,${R1}[1]
865 vld1.32 ${S4}[1],[$tbl1,:32]
866 vmlal.u32 $D1,$H0#hi,${R1}[1]
867 vmlal.u32 $D4,$H3#hi,${R1}[1]
869 vmlal.u32 $D0,$H3#hi,${S2}[1]
870 vmlal.u32 $D3,$H1#hi,${R2}[1]
871 vmlal.u32 $D4,$H2#hi,${R2}[1]
872 vmlal.u32 $D1,$H4#hi,${S2}[1]
873 vmlal.u32 $D2,$H0#hi,${R2}[1]
875 vmlal.u32 $D3,$H0#hi,${R3}[1]
876 vmlal.u32 $D0,$H2#hi,${S3}[1]
877 vmlal.u32 $D4,$H1#hi,${R3}[1]
878 vmlal.u32 $D1,$H3#hi,${S3}[1]
879 vmlal.u32 $D2,$H4#hi,${S3}[1]
881 vmlal.u32 $D3,$H4#hi,${S4}[1]
882 vmlal.u32 $D0,$H1#hi,${S4}[1]
883 vmlal.u32 $D4,$H0#hi,${R4}[1]
884 vmlal.u32 $D1,$H2#hi,${S4}[1]
885 vmlal.u32 $D2,$H3#hi,${S4}[1]
887 vld4.32 {$H0#hi,$H1#hi,$H2#hi,$H3#hi},[$in2] @ inp[2:3] (or 0)
890 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
891 @ (hash+inp[0:1])*r^4 and accumulate
893 vmlal.u32 $D3,$H3#lo,${R0}[0]
894 vmlal.u32 $D0,$H0#lo,${R0}[0]
895 vmlal.u32 $D4,$H4#lo,${R0}[0]
896 vmlal.u32 $D1,$H1#lo,${R0}[0]
897 vmlal.u32 $D2,$H2#lo,${R0}[0]
898 vld1.32 ${S4}[0],[$tbl0,:32]
900 vmlal.u32 $D3,$H2#lo,${R1}[0]
901 vmlal.u32 $D0,$H4#lo,${S1}[0]
902 vmlal.u32 $D4,$H3#lo,${R1}[0]
903 vmlal.u32 $D1,$H0#lo,${R1}[0]
904 vmlal.u32 $D2,$H1#lo,${R1}[0]
906 vmlal.u32 $D3,$H1#lo,${R2}[0]
907 vmlal.u32 $D0,$H3#lo,${S2}[0]
908 vmlal.u32 $D4,$H2#lo,${R2}[0]
909 vmlal.u32 $D1,$H4#lo,${S2}[0]
910 vmlal.u32 $D2,$H0#lo,${R2}[0]
912 vmlal.u32 $D3,$H0#lo,${R3}[0]
913 vmlal.u32 $D0,$H2#lo,${S3}[0]
914 vmlal.u32 $D4,$H1#lo,${R3}[0]
915 vmlal.u32 $D1,$H3#lo,${S3}[0]
916 vmlal.u32 $D3,$H4#lo,${S4}[0]
918 vmlal.u32 $D2,$H4#lo,${S3}[0]
919 vmlal.u32 $D0,$H1#lo,${S4}[0]
920 vmlal.u32 $D4,$H0#lo,${R4}[0]
921 vmov.i32 $H4,#1<<24 @ padbit, yes, always
922 vmlal.u32 $D1,$H2#lo,${S4}[0]
923 vmlal.u32 $D2,$H3#lo,${S4}[0]
925 vld4.32 {$H0#lo,$H1#lo,$H2#lo,$H3#lo},[$inp] @ inp[0:1]
934 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
935 @ lazy reduction interleaved with base 2^32 -> base 2^26 of
936 @ inp[0:3] previously loaded to $H0-$H3 and smashed to $H0-$H4.
942 vadd.i64 $D4,$D4,$T0 @ h3 -> h4
943 vbic.i32 $D3#lo,#0xfc000000
944 vsri.u32 $H4,$H3,#8 @ base 2^32 -> base 2^26
945 vadd.i64 $D1,$D1,$T1 @ h0 -> h1
947 vbic.i32 $D0#lo,#0xfc000000
949 vshrn.u64 $T0#lo,$D4,#26
953 vadd.i64 $D2,$D2,$T1 @ h1 -> h2
955 vbic.i32 $D4#lo,#0xfc000000
957 vbic.i32 $D1#lo,#0xfc000000
959 vadd.i32 $D0#lo,$D0#lo,$T0#lo
960 vshl.u32 $T0#lo,$T0#lo,#2
961 vbic.i32 $H3,#0xfc000000
962 vshrn.u64 $T1#lo,$D2,#26
964 vaddl.u32 $D0,$D0#lo,$T0#lo @ h4 -> h0 [widen for a sec]
966 vadd.i32 $D3#lo,$D3#lo,$T1#lo @ h2 -> h3
968 vbic.i32 $D2#lo,#0xfc000000
969 vbic.i32 $H2,#0xfc000000
971 vshrn.u64 $T0#lo,$D0,#26 @ re-narrow
974 vbic.i32 $H0,#0xfc000000
975 vshr.u32 $T1#lo,$D3#lo,#26
976 vbic.i32 $D3#lo,#0xfc000000
977 vbic.i32 $D0#lo,#0xfc000000
978 vadd.i32 $D1#lo,$D1#lo,$T0#lo @ h0 -> h1
979 vadd.i32 $D4#lo,$D4#lo,$T1#lo @ h3 -> h4
980 vbic.i32 $H1,#0xfc000000
985 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
986 @ multiply (inp[0:1]+hash) or inp[2:3] by r^2:r^1
988 add $tbl1,$ctx,#(48+0*9*4)
989 add $tbl0,$ctx,#(48+1*9*4)
995 vadd.i32 $H2#hi,$H2#lo,$D2#lo @ add hash value and move to #hi
996 vadd.i32 $H0#hi,$H0#lo,$D0#lo
997 vadd.i32 $H3#hi,$H3#lo,$D3#lo
998 vadd.i32 $H1#hi,$H1#lo,$D1#lo
999 vadd.i32 $H4#hi,$H4#lo,$D4#lo
1002 vld4.32 {${R0}[1],${R1}[1],${S1}[1],${R2}[1]},[$tbl1]! @ load r^1
1003 vld4.32 {${R0}[0],${R1}[0],${S1}[0],${R2}[0]},[$tbl0]! @ load r^2
1005 vadd.i32 $H2#lo,$H2#lo,$D2#lo @ can be redundant
1006 vmull.u32 $D2,$H2#hi,$R0
1007 vadd.i32 $H0#lo,$H0#lo,$D0#lo
1008 vmull.u32 $D0,$H0#hi,$R0
1009 vadd.i32 $H3#lo,$H3#lo,$D3#lo
1010 vmull.u32 $D3,$H3#hi,$R0
1011 vadd.i32 $H1#lo,$H1#lo,$D1#lo
1012 vmull.u32 $D1,$H1#hi,$R0
1013 vadd.i32 $H4#lo,$H4#lo,$D4#lo
1014 vmull.u32 $D4,$H4#hi,$R0
1016 vmlal.u32 $D0,$H4#hi,$S1
1017 vld4.32 {${S2}[1],${R3}[1],${S3}[1],${R4}[1]},[$tbl1]!
1018 vmlal.u32 $D3,$H2#hi,$R1
1019 vld4.32 {${S2}[0],${R3}[0],${S3}[0],${R4}[0]},[$tbl0]!
1020 vmlal.u32 $D1,$H0#hi,$R1
1021 vmlal.u32 $D4,$H3#hi,$R1
1022 vmlal.u32 $D2,$H1#hi,$R1
1024 vmlal.u32 $D3,$H1#hi,$R2
1025 vld1.32 ${S4}[1],[$tbl1,:32]
1026 vmlal.u32 $D0,$H3#hi,$S2
1027 vld1.32 ${S4}[0],[$tbl0,:32]
1028 vmlal.u32 $D4,$H2#hi,$R2
1029 vmlal.u32 $D1,$H4#hi,$S2
1030 vmlal.u32 $D2,$H0#hi,$R2
1032 vmlal.u32 $D3,$H0#hi,$R3
1034 addne $tbl1,$ctx,#(48+2*9*4)
1035 vmlal.u32 $D0,$H2#hi,$S3
1037 addne $tbl0,$ctx,#(48+3*9*4)
1038 vmlal.u32 $D4,$H1#hi,$R3
1039 vmlal.u32 $D1,$H3#hi,$S3
1040 vmlal.u32 $D2,$H4#hi,$S3
1042 vmlal.u32 $D3,$H4#hi,$S4
1043 vorn $MASK,$MASK,$MASK @ all-ones, can be redundant
1044 vmlal.u32 $D0,$H1#hi,$S4
1045 vshr.u64 $MASK,$MASK,#38
1046 vmlal.u32 $D4,$H0#hi,$R4
1047 vmlal.u32 $D1,$H2#hi,$S4
1048 vmlal.u32 $D2,$H3#hi,$S4
1052 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1053 @ (hash+inp[0:1])*r^4:r^3 and accumulate
1055 vld4.32 {${R0}[1],${R1}[1],${S1}[1],${R2}[1]},[$tbl1]! @ load r^3
1056 vld4.32 {${R0}[0],${R1}[0],${S1}[0],${R2}[0]},[$tbl0]! @ load r^4
1058 vmlal.u32 $D2,$H2#lo,$R0
1059 vmlal.u32 $D0,$H0#lo,$R0
1060 vmlal.u32 $D3,$H3#lo,$R0
1061 vmlal.u32 $D1,$H1#lo,$R0
1062 vmlal.u32 $D4,$H4#lo,$R0
1064 vmlal.u32 $D0,$H4#lo,$S1
1065 vld4.32 {${S2}[1],${R3}[1],${S3}[1],${R4}[1]},[$tbl1]!
1066 vmlal.u32 $D3,$H2#lo,$R1
1067 vld4.32 {${S2}[0],${R3}[0],${S3}[0],${R4}[0]},[$tbl0]!
1068 vmlal.u32 $D1,$H0#lo,$R1
1069 vmlal.u32 $D4,$H3#lo,$R1
1070 vmlal.u32 $D2,$H1#lo,$R1
1072 vmlal.u32 $D3,$H1#lo,$R2
1073 vld1.32 ${S4}[1],[$tbl1,:32]
1074 vmlal.u32 $D0,$H3#lo,$S2
1075 vld1.32 ${S4}[0],[$tbl0,:32]
1076 vmlal.u32 $D4,$H2#lo,$R2
1077 vmlal.u32 $D1,$H4#lo,$S2
1078 vmlal.u32 $D2,$H0#lo,$R2
1080 vmlal.u32 $D3,$H0#lo,$R3
1081 vmlal.u32 $D0,$H2#lo,$S3
1082 vmlal.u32 $D4,$H1#lo,$R3
1083 vmlal.u32 $D1,$H3#lo,$S3
1084 vmlal.u32 $D2,$H4#lo,$S3
1086 vmlal.u32 $D3,$H4#lo,$S4
1087 vorn $MASK,$MASK,$MASK @ all-ones
1088 vmlal.u32 $D0,$H1#lo,$S4
1089 vshr.u64 $MASK,$MASK,#38
1090 vmlal.u32 $D4,$H0#lo,$R4
1091 vmlal.u32 $D1,$H2#lo,$S4
1092 vmlal.u32 $D2,$H3#lo,$S4
1095 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1096 @ horizontal addition
1098 vadd.i64 $D3#lo,$D3#lo,$D3#hi
1099 vadd.i64 $D0#lo,$D0#lo,$D0#hi
1100 vadd.i64 $D4#lo,$D4#lo,$D4#hi
1101 vadd.i64 $D1#lo,$D1#lo,$D1#hi
1102 vadd.i64 $D2#lo,$D2#lo,$D2#hi
1104 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1105 @ lazy reduction, but without narrowing
1107 vshr.u64 $T0,$D3,#26
1108 vand.i64 $D3,$D3,$MASK
1109 vshr.u64 $T1,$D0,#26
1110 vand.i64 $D0,$D0,$MASK
1111 vadd.i64 $D4,$D4,$T0 @ h3 -> h4
1112 vadd.i64 $D1,$D1,$T1 @ h0 -> h1
1114 vshr.u64 $T0,$D4,#26
1115 vand.i64 $D4,$D4,$MASK
1116 vshr.u64 $T1,$D1,#26
1117 vand.i64 $D1,$D1,$MASK
1118 vadd.i64 $D2,$D2,$T1 @ h1 -> h2
1120 vadd.i64 $D0,$D0,$T0
1122 vshr.u64 $T1,$D2,#26
1123 vand.i64 $D2,$D2,$MASK
1124 vadd.i64 $D0,$D0,$T0 @ h4 -> h0
1125 vadd.i64 $D3,$D3,$T1 @ h2 -> h3
1127 vshr.u64 $T0,$D0,#26
1128 vand.i64 $D0,$D0,$MASK
1129 vshr.u64 $T1,$D3,#26
1130 vand.i64 $D3,$D3,$MASK
1131 vadd.i64 $D1,$D1,$T0 @ h0 -> h1
1132 vadd.i64 $D4,$D4,$T1 @ h3 -> h4
1137 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1140 vst4.32 {$D0#lo[0],$D1#lo[0],$D2#lo[0],$D3#lo[0]},[$ctx]!
1141 vst1.32 {$D4#lo[0]},[$ctx]
1143 vldmia sp!,{d8-d15} @ epilogue
1147 .size poly1305_blocks_neon,.-poly1305_blocks_neon
1149 .type poly1305_emit_neon,%function
1152 ldr ip,[$ctx,#36] @ is_base2_26
1157 beq .Lpoly1305_emit_enter
1159 ldmia $ctx,{$h0-$h4}
1162 adds $h0,$h0,$h1,lsl#26 @ base 2^26 -> base 2^32
1164 adcs $h1,$h1,$h2,lsl#20
1166 adcs $h2,$h2,$h3,lsl#14
1168 adcs $h3,$h3,$h4,lsl#8
1169 adc $h4,$g0,$h4,lsr#24 @ can be partially reduced ...
1171 and $g0,$h4,#-4 @ ... so reduce
1173 add $g0,$g0,$g0,lsr#2 @ *= 5
1180 adds $g0,$h0,#5 @ compare to modulus
1185 tst $g4,#4 @ did it carry/borrow?
1198 ldr $g3,[$nonce,#12]
1200 adds $h0,$h0,$g0 @ accumulate nonce
1211 str $h0,[$mac,#0] @ store the result
1218 .size poly1305_emit_neon,.-poly1305_emit_neon
1222 .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1224 .word OPENSSL_armcap_P-.Lpoly1305_init
1229 .asciz "Poly1305 for ARMv4/NEON, CRYPTOGAMS by <appro\@openssl.org>"
1231 #if __ARM_MAX_ARCH__>=7
1232 .comm OPENSSL_armcap_P,4,4
1236 foreach (split("\n",$code)) {
1237 s/\`([^\`]*)\`/eval $1/geo;
1239 s/\bq([0-9]+)#(lo|hi)/sprintf "d%d",2*$1+($2 eq "hi")/geo or
1240 s/\bret\b/bx lr/go or
1241 s/\bbx\s+lr\b/.word\t0xe12fff1e/go; # make it possible to compile with -march=armv4
1245 close STDOUT; # enforce flush