2 # Copyright 2016 The OpenSSL Project Authors. All Rights Reserved.
4 # Licensed under the OpenSSL license (the "License"). You may not use
5 # this file except in compliance with the License. You can obtain a copy
6 # in the file LICENSE in the source distribution or at
7 # https://www.openssl.org/source/license.html
10 # ====================================================================
11 # Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
12 # project. The module is, however, dual licensed under OpenSSL and
13 # CRYPTOGAMS licenses depending on where you obtain it. For further
14 # details see http://www.openssl.org/~appro/cryptogams/.
15 # ====================================================================
17 # IALU(*)/gcc-4.4 NEON
19 # ARM11xx(ARMv6) 7.78/+100% -
20 # Cortex-A5 6.35/+130% 3.00
21 # Cortex-A8 6.25/+115% 2.36
22 # Cortex-A9 5.10/+95% 2.55
23 # Cortex-A15 3.85/+85% 1.25(**)
24 # Snapdragon S4 5.70/+100% 1.48(**)
26 # (*) this is for -march=armv6, i.e. with bunch of ldrb loading data;
27 # (**) these are trade-off results, they can be improved by ~8% but at
28 # the cost of 15/12% regression on Cortex-A5/A7, it's even possible
29 # to improve Cortex-A9 result, but then A5/A7 loose more than 20%;
32 if ($flavour=~/\w[\w\-]*\.\w+$/) { $output=$flavour; undef $flavour; }
33 else { while (($output=shift) && ($output!~/\w[\w\-]*\.\w+$/)) {} }
35 if ($flavour && $flavour ne "void") {
36 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
37 ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
38 ( $xlate="${dir}../../perlasm/arm-xlate.pl" and -f $xlate) or
39 die "can't locate arm-xlate.pl";
41 open STDOUT,"| \"$^X\" $xlate $flavour $output";
43 open STDOUT,">$output";
46 ($ctx,$inp,$len,$padbit)=map("r$_",(0..3));
52 #if defined(__thumb2__)
60 .globl poly1305_blocks
62 .type poly1305_init,%function
70 str r3,[$ctx,#0] @ zero hash value
75 str r3,[$ctx,#36] @ is_base2_26
84 #if __ARM_MAX_ARCH__>=7
85 adr r11,.Lpoly1305_init
86 ldr r12,.LOPENSSL_armcap
91 and r3,r10,#-4 @ 0x0ffffffc
102 #if __ARM_MAX_ARCH__>=7
103 ldr r12,[r11,r12] @ OPENSSL_armcap_P
117 #if __ARM_MAX_ARCH__>=7
118 tst r12,#ARMV7_NEON @ check for NEON
120 adr r9,poly1305_blocks_neon
121 adr r11,poly1305_blocks
126 adr r12,poly1305_emit
127 adr r10,poly1305_emit_neon
136 addeq r12,r11,#(poly1305_emit-.Lpoly1305_init)
137 addne r12,r11,#(poly1305_emit_neon-.Lpoly1305_init)
138 addeq r11,r11,#(poly1305_blocks-.Lpoly1305_init)
139 addne r11,r11,#(poly1305_blocks_neon-.Lpoly1305_init)
142 orr r12,r12,#1 @ thumb-ify address
164 #if __ARM_MAX_ARCH__>=7
165 stmia r2,{r11,r12} @ fill functions table
176 moveq pc,lr @ be binary compatible with V4, yet
177 bx lr @ interoperable with Thumb ISA:-)
179 .size poly1305_init,.-poly1305_init
182 my ($h0,$h1,$h2,$h3,$h4,$r0,$r1,$r2,$r3)=map("r$_",(4..12));
183 my ($s1,$s2,$s3)=($r1,$r2,$r3);
186 .type poly1305_blocks,%function
190 stmdb sp!,{r3-r11,lr}
196 add $len,$len,$inp @ end pointer
199 ldmia $ctx,{$h0-$r3} @ load context
201 str $ctx,[sp,#12] @ offload stuff
211 ldrb r0,[lr],#16 @ load input
215 addhi $h4,$h4,#1 @ 1<<128
225 adds $h0,$h0,r3 @ accumulate input
247 str lr,[sp,#8] @ offload input pointer
249 add $s1,$r1,$r1,lsr#2
252 ldr r0,[lr],#16 @ load input
256 addhi $h4,$h4,#1 @ padbit
266 adds $h0,$h0,r0 @ accumulate input
267 str lr,[sp,#8] @ offload input pointer
269 add $s1,$r1,$r1,lsr#2
272 add $s2,$r2,$r2,lsr#2
274 add $s3,$r3,$r3,lsr#2
281 ldr $r1,[sp,#20] @ reload $r1
287 str r0,[sp,#0] @ future $h0
289 ldr $r2,[sp,#24] @ reload $r2
290 adds r2,r2,r1 @ d1+=d0>>32
292 adc lr,r3,#0 @ future $h2
293 str r2,[sp,#4] @ future $h1
298 ldr $r3,[sp,#28] @ reload $r3
310 adds $h2,lr,r0 @ d2+=d1>>32
311 ldr lr,[sp,#8] @ reload input pointer
313 adds $h3,r2,r1 @ d3+=d2>>32
314 ldr r0,[sp,#16] @ reload end pointer
316 add $h4,$h4,r3 @ h4+=d3>>32
320 add r1,r1,r1,lsr#2 @ *=5
327 cmp r0,lr @ done yet?
332 stmia $ctx,{$h0-$h4} @ store the result
336 ldmia sp!,{r3-r11,pc}
338 ldmia sp!,{r3-r11,lr}
340 moveq pc,lr @ be binary compatible with V4, yet
341 bx lr @ interoperable with Thumb ISA:-)
343 .size poly1305_blocks,.-poly1305_blocks
347 my ($ctx,$mac,$nonce)=map("r$_",(0..2));
348 my ($h0,$h1,$h2,$h3,$h4,$g0,$g1,$g2,$g3)=map("r$_",(3..11));
352 .type poly1305_emit,%function
356 .Lpoly1305_emit_enter:
359 adds $g0,$h0,#5 @ compare to modulus
364 tst $g4,#4 @ did it carry/borrow?
441 moveq pc,lr @ be binary compatible with V4, yet
442 bx lr @ interoperable with Thumb ISA:-)
444 .size poly1305_emit,.-poly1305_emit
447 my ($R0,$R1,$S1,$R2,$S2,$R3,$S3,$R4,$S4) = map("d$_",(0..9));
448 my ($D0,$D1,$D2,$D3,$D4, $H0,$H1,$H2,$H3,$H4) = map("q$_",(5..14));
449 my ($T0,$T1,$MASK) = map("q$_",(15,4,0));
451 my ($in2,$zeros,$tbl0,$tbl1) = map("r$_",(4..7));
454 #if __ARM_MAX_ARCH__>=7
457 .type poly1305_init_neon,%function
460 ldr r4,[$ctx,#20] @ load key base 2^32
465 and r2,r4,#0x03ffffff @ base 2^32 -> base 2^26
473 and r3,r3,#0x03ffffff
474 and r4,r4,#0x03ffffff
475 and r5,r5,#0x03ffffff
477 vdup.32 $R0,r2 @ r^1 in both lanes
478 add r2,r3,r3,lsl#2 @ *5
491 mov $zeros,#2 @ counter
494 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
495 @ d0 = h0*r0 + h4*5*r1 + h3*5*r2 + h2*5*r3 + h1*5*r4
496 @ d1 = h1*r0 + h0*r1 + h4*5*r2 + h3*5*r3 + h2*5*r4
497 @ d2 = h2*r0 + h1*r1 + h0*r2 + h4*5*r3 + h3*5*r4
498 @ d3 = h3*r0 + h2*r1 + h1*r2 + h0*r3 + h4*5*r4
499 @ d4 = h4*r0 + h3*r1 + h2*r2 + h1*r3 + h0*r4
501 vmull.u32 $D0,$R0,${R0}[1]
502 vmull.u32 $D1,$R1,${R0}[1]
503 vmull.u32 $D2,$R2,${R0}[1]
504 vmull.u32 $D3,$R3,${R0}[1]
505 vmull.u32 $D4,$R4,${R0}[1]
507 vmlal.u32 $D0,$R4,${S1}[1]
508 vmlal.u32 $D1,$R0,${R1}[1]
509 vmlal.u32 $D2,$R1,${R1}[1]
510 vmlal.u32 $D3,$R2,${R1}[1]
511 vmlal.u32 $D4,$R3,${R1}[1]
513 vmlal.u32 $D0,$R3,${S2}[1]
514 vmlal.u32 $D1,$R4,${S2}[1]
515 vmlal.u32 $D3,$R1,${R2}[1]
516 vmlal.u32 $D2,$R0,${R2}[1]
517 vmlal.u32 $D4,$R2,${R2}[1]
519 vmlal.u32 $D0,$R2,${S3}[1]
520 vmlal.u32 $D3,$R0,${R3}[1]
521 vmlal.u32 $D1,$R3,${S3}[1]
522 vmlal.u32 $D2,$R4,${S3}[1]
523 vmlal.u32 $D4,$R1,${R3}[1]
525 vmlal.u32 $D3,$R4,${S4}[1]
526 vmlal.u32 $D0,$R1,${S4}[1]
527 vmlal.u32 $D1,$R2,${S4}[1]
528 vmlal.u32 $D2,$R3,${S4}[1]
529 vmlal.u32 $D4,$R0,${R4}[1]
531 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
532 @ lazy reduction as discussed in "NEON crypto" by D.J. Bernstein
535 @ H0>>+H1>>+H2>>+H3>>+H4
536 @ H3>>+H4>>*5+H0>>+H1
540 @ Result of multiplication of n-bit number by m-bit number is
541 @ n+m bits wide. However! Even though 2^n is a n+1-bit number,
542 @ m-bit number multiplied by 2^n is still n+m bits wide.
544 @ Sum of two n-bit numbers is n+1 bits wide, sum of three - n+2,
545 @ and so is sum of four. Sum of 2^m n-m-bit numbers and n-bit
546 @ one is n+1 bits wide.
548 @ >>+ denotes Hnext += Hn>>26, Hn &= 0x3ffffff. This means that
549 @ H0, H2, H3 are guaranteed to be 26 bits wide, while H1 and H4
550 @ can be 27. However! In cases when their width exceeds 26 bits
551 @ they are limited by 2^26+2^6. This in turn means that *sum*
552 @ of the products with these values can still be viewed as sum
553 @ of 52-bit numbers as long as the amount of addends is not a
554 @ power of 2. For example,
556 @ H4 = H4*R0 + H3*R1 + H2*R2 + H1*R3 + H0 * R4,
558 @ which can't be larger than 5 * (2^26 + 2^6) * (2^26 + 2^6), or
559 @ 5 * (2^52 + 2*2^32 + 2^12), which in turn is smaller than
560 @ 8 * (2^52) or 2^55. However, the value is then multiplied by
561 @ by 5, so we should be looking at 5 * 5 * (2^52 + 2^33 + 2^12),
562 @ which is less than 32 * (2^52) or 2^57. And when processing
563 @ data we are looking at triple as many addends...
565 @ In key setup procedure pre-reduced H0 is limited by 5*4+1 and
566 @ 5*H4 - by 5*5 52-bit addends, or 57 bits. But when hashing the
567 @ input H0 is limited by (5*4+1)*3 addends, or 58 bits, while
568 @ 5*H4 by 5*5*3, or 59[!] bits. How is this relevant? vmlal.u32
569 @ instruction accepts 2x32-bit input and writes 2x64-bit result.
570 @ This means that result of reduction have to be compressed upon
571 @ loop wrap-around. This can be done in the process of reduction
572 @ to minimize amount of instructions [as well as amount of
573 @ 128-bit instructions, which benefits low-end processors], but
574 @ one has to watch for H2 (which is narrower than H0) and 5*H4
575 @ not being wider than 58 bits, so that result of right shift
576 @ by 26 bits fits in 32 bits. This is also useful on x86,
577 @ because it allows to use paddd in place for paddq, which
578 @ benefits Atom, where paddq is ridiculously slow.
584 vadd.i64 $D4,$D4,$T0 @ h3 -> h4
585 vbic.i32 $D3#lo,#0xfc000000 @ &=0x03ffffff
586 vadd.i64 $D1,$D1,$T1 @ h0 -> h1
587 vbic.i32 $D0#lo,#0xfc000000
589 vshrn.u64 $T0#lo,$D4,#26
593 vadd.i64 $D2,$D2,$T1 @ h1 -> h2
594 vbic.i32 $D4#lo,#0xfc000000
595 vbic.i32 $D1#lo,#0xfc000000
597 vadd.i32 $D0#lo,$D0#lo,$T0#lo
598 vshl.u32 $T0#lo,$T0#lo,#2
599 vshrn.u64 $T1#lo,$D2,#26
601 vadd.i32 $D0#lo,$D0#lo,$T0#lo @ h4 -> h0
602 vadd.i32 $D3#lo,$D3#lo,$T1#lo @ h2 -> h3
603 vbic.i32 $D2#lo,#0xfc000000
605 vshr.u32 $T0#lo,$D0#lo,#26
606 vbic.i32 $D0#lo,#0xfc000000
607 vshr.u32 $T1#lo,$D3#lo,#26
608 vbic.i32 $D3#lo,#0xfc000000
609 vadd.i32 $D1#lo,$D1#lo,$T0#lo @ h0 -> h1
610 vadd.i32 $D4#lo,$D4#lo,$T1#lo @ h3 -> h4
612 subs $zeros,$zeros,#1
613 beq .Lsquare_break_neon
615 add $tbl0,$ctx,#(48+0*9*4)
616 add $tbl1,$ctx,#(48+1*9*4)
618 vtrn.32 $R0,$D0#lo @ r^2:r^1
624 vshl.u32 $S2,$R2,#2 @ *5
633 vst4.32 {${R0}[0],${R1}[0],${S1}[0],${R2}[0]},[$tbl0]!
634 vst4.32 {${R0}[1],${R1}[1],${S1}[1],${R2}[1]},[$tbl1]!
635 vst4.32 {${S2}[0],${R3}[0],${S3}[0],${R4}[0]},[$tbl0]!
636 vst4.32 {${S2}[1],${R3}[1],${S3}[1],${R4}[1]},[$tbl1]!
637 vst1.32 {${S4}[0]},[$tbl0,:32]
638 vst1.32 {${S4}[1]},[$tbl1,:32]
644 add $tbl0,$ctx,#(48+2*4*9)
645 add $tbl1,$ctx,#(48+3*4*9)
647 vmov $R0,$D0#lo @ r^4:r^3
648 vshl.u32 $S1,$D1#lo,#2 @ *5
650 vshl.u32 $S2,$D2#lo,#2
652 vshl.u32 $S3,$D3#lo,#2
654 vshl.u32 $S4,$D4#lo,#2
656 vadd.i32 $S1,$S1,$D1#lo
657 vadd.i32 $S2,$S2,$D2#lo
658 vadd.i32 $S3,$S3,$D3#lo
659 vadd.i32 $S4,$S4,$D4#lo
661 vst4.32 {${R0}[0],${R1}[0],${S1}[0],${R2}[0]},[$tbl0]!
662 vst4.32 {${R0}[1],${R1}[1],${S1}[1],${R2}[1]},[$tbl1]!
663 vst4.32 {${S2}[0],${R3}[0],${S3}[0],${R4}[0]},[$tbl0]!
664 vst4.32 {${S2}[1],${R3}[1],${S3}[1],${R4}[1]},[$tbl1]!
665 vst1.32 {${S4}[0]},[$tbl0]
666 vst1.32 {${S4}[1]},[$tbl1]
669 .size poly1305_init_neon,.-poly1305_init_neon
671 .type poly1305_blocks_neon,%function
673 poly1305_blocks_neon:
674 ldr ip,[$ctx,#36] @ is_base2_26
680 tst ip,ip @ is_base2_26?
681 beq .Lpoly1305_blocks
685 vstmdb sp!,{d8-d15} @ ABI specification says so
687 tst ip,ip @ is_base2_26?
691 bl poly1305_init_neon
693 ldr r4,[$ctx,#0] @ load hash value base 2^32
699 and r2,r4,#0x03ffffff @ base 2^32 -> base 2^26
701 veor $D0#lo,$D0#lo,$D0#lo
704 veor $D1#lo,$D1#lo,$D1#lo
707 veor $D2#lo,$D2#lo,$D2#lo
710 veor $D3#lo,$D3#lo,$D3#lo
711 and r3,r3,#0x03ffffff
713 veor $D4#lo,$D4#lo,$D4#lo
714 and r4,r4,#0x03ffffff
716 and r5,r5,#0x03ffffff
717 str r1,[$ctx,#36] @ is_base2_26
731 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
734 veor $D0#lo,$D0#lo,$D0#lo
735 veor $D1#lo,$D1#lo,$D1#lo
736 veor $D2#lo,$D2#lo,$D2#lo
737 veor $D3#lo,$D3#lo,$D3#lo
738 veor $D4#lo,$D4#lo,$D4#lo
739 vld4.32 {$D0#lo[0],$D1#lo[0],$D2#lo[0],$D3#lo[0]},[$ctx]!
741 vld1.32 {$D4#lo[0]},[$ctx]
742 sub $ctx,$ctx,#16 @ rewind
746 mov $padbit,$padbit,lsl#24
750 vld4.32 {$H0#lo[0],$H1#lo[0],$H2#lo[0],$H3#lo[0]},[$inp]!
751 vmov.32 $H4#lo[0],$padbit
761 vsri.u32 $H4#lo,$H3#lo,#8 @ base 2^32 -> base 2^26
762 vshl.u32 $H3#lo,$H3#lo,#18
764 vsri.u32 $H3#lo,$H2#lo,#14
765 vshl.u32 $H2#lo,$H2#lo,#12
766 vadd.i32 $H4#hi,$H4#lo,$D4#lo @ add hash value and move to #hi
768 vbic.i32 $H3#lo,#0xfc000000
769 vsri.u32 $H2#lo,$H1#lo,#20
770 vshl.u32 $H1#lo,$H1#lo,#6
772 vbic.i32 $H2#lo,#0xfc000000
773 vsri.u32 $H1#lo,$H0#lo,#26
774 vadd.i32 $H3#hi,$H3#lo,$D3#lo
776 vbic.i32 $H0#lo,#0xfc000000
777 vbic.i32 $H1#lo,#0xfc000000
778 vadd.i32 $H2#hi,$H2#lo,$D2#lo
780 vadd.i32 $H0#hi,$H0#lo,$D0#lo
781 vadd.i32 $H1#hi,$H1#lo,$D1#lo
795 vmov.i32 $H4,#1<<24 @ padbit, yes, always
796 vld4.32 {$H0#lo,$H1#lo,$H2#lo,$H3#lo},[$inp] @ inp[0:1]
798 vld4.32 {$H0#hi,$H1#hi,$H2#hi,$H3#hi},[$in2] @ inp[2:3] (or 0)
801 addhi $tbl1,$ctx,#(48+1*9*4)
802 addhi $tbl0,$ctx,#(48+3*9*4)
810 vsri.u32 $H4,$H3,#8 @ base 2^32 -> base 2^26
816 vbic.i32 $H3,#0xfc000000
820 vbic.i32 $H2,#0xfc000000
823 vbic.i32 $H0,#0xfc000000
824 vbic.i32 $H1,#0xfc000000
828 vld4.32 {${R0}[1],${R1}[1],${S1}[1],${R2}[1]},[$tbl1]! @ load r^2
829 vld4.32 {${R0}[0],${R1}[0],${S1}[0],${R2}[0]},[$tbl0]! @ load r^4
830 vld4.32 {${S2}[1],${R3}[1],${S3}[1],${R4}[1]},[$tbl1]!
831 vld4.32 {${S2}[0],${R3}[0],${S3}[0],${R4}[0]},[$tbl0]!
836 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
837 @ ((inp[0]*r^4+inp[2]*r^2+inp[4])*r^4+inp[6]*r^2
838 @ ((inp[1]*r^4+inp[3]*r^2+inp[5])*r^3+inp[7]*r
839 @ \___________________/
840 @ ((inp[0]*r^4+inp[2]*r^2+inp[4])*r^4+inp[6]*r^2+inp[8])*r^2
841 @ ((inp[1]*r^4+inp[3]*r^2+inp[5])*r^4+inp[7]*r^2+inp[9])*r
842 @ \___________________/ \____________________/
844 @ Note that we start with inp[2:3]*r^2. This is because it
845 @ doesn't depend on reduction in previous iteration.
846 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
847 @ d4 = h4*r0 + h3*r1 + h2*r2 + h1*r3 + h0*r4
848 @ d3 = h3*r0 + h2*r1 + h1*r2 + h0*r3 + h4*5*r4
849 @ d2 = h2*r0 + h1*r1 + h0*r2 + h4*5*r3 + h3*5*r4
850 @ d1 = h1*r0 + h0*r1 + h4*5*r2 + h3*5*r3 + h2*5*r4
851 @ d0 = h0*r0 + h4*5*r1 + h3*5*r2 + h2*5*r3 + h1*5*r4
853 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
856 vadd.i32 $H2#lo,$H2#lo,$D2#lo @ accumulate inp[0:1]
857 vmull.u32 $D2,$H2#hi,${R0}[1]
858 vadd.i32 $H0#lo,$H0#lo,$D0#lo
859 vmull.u32 $D0,$H0#hi,${R0}[1]
860 vadd.i32 $H3#lo,$H3#lo,$D3#lo
861 vmull.u32 $D3,$H3#hi,${R0}[1]
862 vmlal.u32 $D2,$H1#hi,${R1}[1]
863 vadd.i32 $H1#lo,$H1#lo,$D1#lo
864 vmull.u32 $D1,$H1#hi,${R0}[1]
866 vadd.i32 $H4#lo,$H4#lo,$D4#lo
867 vmull.u32 $D4,$H4#hi,${R0}[1]
869 vmlal.u32 $D0,$H4#hi,${S1}[1]
872 vmlal.u32 $D3,$H2#hi,${R1}[1]
873 vld1.32 ${S4}[1],[$tbl1,:32]
874 vmlal.u32 $D1,$H0#hi,${R1}[1]
875 vmlal.u32 $D4,$H3#hi,${R1}[1]
877 vmlal.u32 $D0,$H3#hi,${S2}[1]
878 vmlal.u32 $D3,$H1#hi,${R2}[1]
879 vmlal.u32 $D4,$H2#hi,${R2}[1]
880 vmlal.u32 $D1,$H4#hi,${S2}[1]
881 vmlal.u32 $D2,$H0#hi,${R2}[1]
883 vmlal.u32 $D3,$H0#hi,${R3}[1]
884 vmlal.u32 $D0,$H2#hi,${S3}[1]
885 vmlal.u32 $D4,$H1#hi,${R3}[1]
886 vmlal.u32 $D1,$H3#hi,${S3}[1]
887 vmlal.u32 $D2,$H4#hi,${S3}[1]
889 vmlal.u32 $D3,$H4#hi,${S4}[1]
890 vmlal.u32 $D0,$H1#hi,${S4}[1]
891 vmlal.u32 $D4,$H0#hi,${R4}[1]
892 vmlal.u32 $D1,$H2#hi,${S4}[1]
893 vmlal.u32 $D2,$H3#hi,${S4}[1]
895 vld4.32 {$H0#hi,$H1#hi,$H2#hi,$H3#hi},[$in2] @ inp[2:3] (or 0)
898 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
899 @ (hash+inp[0:1])*r^4 and accumulate
901 vmlal.u32 $D3,$H3#lo,${R0}[0]
902 vmlal.u32 $D0,$H0#lo,${R0}[0]
903 vmlal.u32 $D4,$H4#lo,${R0}[0]
904 vmlal.u32 $D1,$H1#lo,${R0}[0]
905 vmlal.u32 $D2,$H2#lo,${R0}[0]
906 vld1.32 ${S4}[0],[$tbl0,:32]
908 vmlal.u32 $D3,$H2#lo,${R1}[0]
909 vmlal.u32 $D0,$H4#lo,${S1}[0]
910 vmlal.u32 $D4,$H3#lo,${R1}[0]
911 vmlal.u32 $D1,$H0#lo,${R1}[0]
912 vmlal.u32 $D2,$H1#lo,${R1}[0]
914 vmlal.u32 $D3,$H1#lo,${R2}[0]
915 vmlal.u32 $D0,$H3#lo,${S2}[0]
916 vmlal.u32 $D4,$H2#lo,${R2}[0]
917 vmlal.u32 $D1,$H4#lo,${S2}[0]
918 vmlal.u32 $D2,$H0#lo,${R2}[0]
920 vmlal.u32 $D3,$H0#lo,${R3}[0]
921 vmlal.u32 $D0,$H2#lo,${S3}[0]
922 vmlal.u32 $D4,$H1#lo,${R3}[0]
923 vmlal.u32 $D1,$H3#lo,${S3}[0]
924 vmlal.u32 $D3,$H4#lo,${S4}[0]
926 vmlal.u32 $D2,$H4#lo,${S3}[0]
927 vmlal.u32 $D0,$H1#lo,${S4}[0]
928 vmlal.u32 $D4,$H0#lo,${R4}[0]
929 vmov.i32 $H4,#1<<24 @ padbit, yes, always
930 vmlal.u32 $D1,$H2#lo,${S4}[0]
931 vmlal.u32 $D2,$H3#lo,${S4}[0]
933 vld4.32 {$H0#lo,$H1#lo,$H2#lo,$H3#lo},[$inp] @ inp[0:1]
942 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
943 @ lazy reduction interleaved with base 2^32 -> base 2^26 of
944 @ inp[0:3] previously loaded to $H0-$H3 and smashed to $H0-$H4.
950 vadd.i64 $D4,$D4,$T0 @ h3 -> h4
951 vbic.i32 $D3#lo,#0xfc000000
952 vsri.u32 $H4,$H3,#8 @ base 2^32 -> base 2^26
953 vadd.i64 $D1,$D1,$T1 @ h0 -> h1
955 vbic.i32 $D0#lo,#0xfc000000
957 vshrn.u64 $T0#lo,$D4,#26
961 vadd.i64 $D2,$D2,$T1 @ h1 -> h2
963 vbic.i32 $D4#lo,#0xfc000000
965 vbic.i32 $D1#lo,#0xfc000000
967 vadd.i32 $D0#lo,$D0#lo,$T0#lo
968 vshl.u32 $T0#lo,$T0#lo,#2
969 vbic.i32 $H3,#0xfc000000
970 vshrn.u64 $T1#lo,$D2,#26
972 vaddl.u32 $D0,$D0#lo,$T0#lo @ h4 -> h0 [widen for a sec]
974 vadd.i32 $D3#lo,$D3#lo,$T1#lo @ h2 -> h3
976 vbic.i32 $D2#lo,#0xfc000000
977 vbic.i32 $H2,#0xfc000000
979 vshrn.u64 $T0#lo,$D0,#26 @ re-narrow
982 vbic.i32 $H0,#0xfc000000
983 vshr.u32 $T1#lo,$D3#lo,#26
984 vbic.i32 $D3#lo,#0xfc000000
985 vbic.i32 $D0#lo,#0xfc000000
986 vadd.i32 $D1#lo,$D1#lo,$T0#lo @ h0 -> h1
987 vadd.i32 $D4#lo,$D4#lo,$T1#lo @ h3 -> h4
988 vbic.i32 $H1,#0xfc000000
993 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
994 @ multiply (inp[0:1]+hash) or inp[2:3] by r^2:r^1
996 add $tbl1,$ctx,#(48+0*9*4)
997 add $tbl0,$ctx,#(48+1*9*4)
1003 vadd.i32 $H2#hi,$H2#lo,$D2#lo @ add hash value and move to #hi
1004 vadd.i32 $H0#hi,$H0#lo,$D0#lo
1005 vadd.i32 $H3#hi,$H3#lo,$D3#lo
1006 vadd.i32 $H1#hi,$H1#lo,$D1#lo
1007 vadd.i32 $H4#hi,$H4#lo,$D4#lo
1010 vld4.32 {${R0}[1],${R1}[1],${S1}[1],${R2}[1]},[$tbl1]! @ load r^1
1011 vld4.32 {${R0}[0],${R1}[0],${S1}[0],${R2}[0]},[$tbl0]! @ load r^2
1013 vadd.i32 $H2#lo,$H2#lo,$D2#lo @ can be redundant
1014 vmull.u32 $D2,$H2#hi,$R0
1015 vadd.i32 $H0#lo,$H0#lo,$D0#lo
1016 vmull.u32 $D0,$H0#hi,$R0
1017 vadd.i32 $H3#lo,$H3#lo,$D3#lo
1018 vmull.u32 $D3,$H3#hi,$R0
1019 vadd.i32 $H1#lo,$H1#lo,$D1#lo
1020 vmull.u32 $D1,$H1#hi,$R0
1021 vadd.i32 $H4#lo,$H4#lo,$D4#lo
1022 vmull.u32 $D4,$H4#hi,$R0
1024 vmlal.u32 $D0,$H4#hi,$S1
1025 vld4.32 {${S2}[1],${R3}[1],${S3}[1],${R4}[1]},[$tbl1]!
1026 vmlal.u32 $D3,$H2#hi,$R1
1027 vld4.32 {${S2}[0],${R3}[0],${S3}[0],${R4}[0]},[$tbl0]!
1028 vmlal.u32 $D1,$H0#hi,$R1
1029 vmlal.u32 $D4,$H3#hi,$R1
1030 vmlal.u32 $D2,$H1#hi,$R1
1032 vmlal.u32 $D3,$H1#hi,$R2
1033 vld1.32 ${S4}[1],[$tbl1,:32]
1034 vmlal.u32 $D0,$H3#hi,$S2
1035 vld1.32 ${S4}[0],[$tbl0,:32]
1036 vmlal.u32 $D4,$H2#hi,$R2
1037 vmlal.u32 $D1,$H4#hi,$S2
1038 vmlal.u32 $D2,$H0#hi,$R2
1040 vmlal.u32 $D3,$H0#hi,$R3
1042 addne $tbl1,$ctx,#(48+2*9*4)
1043 vmlal.u32 $D0,$H2#hi,$S3
1045 addne $tbl0,$ctx,#(48+3*9*4)
1046 vmlal.u32 $D4,$H1#hi,$R3
1047 vmlal.u32 $D1,$H3#hi,$S3
1048 vmlal.u32 $D2,$H4#hi,$S3
1050 vmlal.u32 $D3,$H4#hi,$S4
1051 vorn $MASK,$MASK,$MASK @ all-ones, can be redundant
1052 vmlal.u32 $D0,$H1#hi,$S4
1053 vshr.u64 $MASK,$MASK,#38
1054 vmlal.u32 $D4,$H0#hi,$R4
1055 vmlal.u32 $D1,$H2#hi,$S4
1056 vmlal.u32 $D2,$H3#hi,$S4
1060 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1061 @ (hash+inp[0:1])*r^4:r^3 and accumulate
1063 vld4.32 {${R0}[1],${R1}[1],${S1}[1],${R2}[1]},[$tbl1]! @ load r^3
1064 vld4.32 {${R0}[0],${R1}[0],${S1}[0],${R2}[0]},[$tbl0]! @ load r^4
1066 vmlal.u32 $D2,$H2#lo,$R0
1067 vmlal.u32 $D0,$H0#lo,$R0
1068 vmlal.u32 $D3,$H3#lo,$R0
1069 vmlal.u32 $D1,$H1#lo,$R0
1070 vmlal.u32 $D4,$H4#lo,$R0
1072 vmlal.u32 $D0,$H4#lo,$S1
1073 vld4.32 {${S2}[1],${R3}[1],${S3}[1],${R4}[1]},[$tbl1]!
1074 vmlal.u32 $D3,$H2#lo,$R1
1075 vld4.32 {${S2}[0],${R3}[0],${S3}[0],${R4}[0]},[$tbl0]!
1076 vmlal.u32 $D1,$H0#lo,$R1
1077 vmlal.u32 $D4,$H3#lo,$R1
1078 vmlal.u32 $D2,$H1#lo,$R1
1080 vmlal.u32 $D3,$H1#lo,$R2
1081 vld1.32 ${S4}[1],[$tbl1,:32]
1082 vmlal.u32 $D0,$H3#lo,$S2
1083 vld1.32 ${S4}[0],[$tbl0,:32]
1084 vmlal.u32 $D4,$H2#lo,$R2
1085 vmlal.u32 $D1,$H4#lo,$S2
1086 vmlal.u32 $D2,$H0#lo,$R2
1088 vmlal.u32 $D3,$H0#lo,$R3
1089 vmlal.u32 $D0,$H2#lo,$S3
1090 vmlal.u32 $D4,$H1#lo,$R3
1091 vmlal.u32 $D1,$H3#lo,$S3
1092 vmlal.u32 $D2,$H4#lo,$S3
1094 vmlal.u32 $D3,$H4#lo,$S4
1095 vorn $MASK,$MASK,$MASK @ all-ones
1096 vmlal.u32 $D0,$H1#lo,$S4
1097 vshr.u64 $MASK,$MASK,#38
1098 vmlal.u32 $D4,$H0#lo,$R4
1099 vmlal.u32 $D1,$H2#lo,$S4
1100 vmlal.u32 $D2,$H3#lo,$S4
1103 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1104 @ horizontal addition
1106 vadd.i64 $D3#lo,$D3#lo,$D3#hi
1107 vadd.i64 $D0#lo,$D0#lo,$D0#hi
1108 vadd.i64 $D4#lo,$D4#lo,$D4#hi
1109 vadd.i64 $D1#lo,$D1#lo,$D1#hi
1110 vadd.i64 $D2#lo,$D2#lo,$D2#hi
1112 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1113 @ lazy reduction, but without narrowing
1115 vshr.u64 $T0,$D3,#26
1116 vand.i64 $D3,$D3,$MASK
1117 vshr.u64 $T1,$D0,#26
1118 vand.i64 $D0,$D0,$MASK
1119 vadd.i64 $D4,$D4,$T0 @ h3 -> h4
1120 vadd.i64 $D1,$D1,$T1 @ h0 -> h1
1122 vshr.u64 $T0,$D4,#26
1123 vand.i64 $D4,$D4,$MASK
1124 vshr.u64 $T1,$D1,#26
1125 vand.i64 $D1,$D1,$MASK
1126 vadd.i64 $D2,$D2,$T1 @ h1 -> h2
1128 vadd.i64 $D0,$D0,$T0
1130 vshr.u64 $T1,$D2,#26
1131 vand.i64 $D2,$D2,$MASK
1132 vadd.i64 $D0,$D0,$T0 @ h4 -> h0
1133 vadd.i64 $D3,$D3,$T1 @ h2 -> h3
1135 vshr.u64 $T0,$D0,#26
1136 vand.i64 $D0,$D0,$MASK
1137 vshr.u64 $T1,$D3,#26
1138 vand.i64 $D3,$D3,$MASK
1139 vadd.i64 $D1,$D1,$T0 @ h0 -> h1
1140 vadd.i64 $D4,$D4,$T1 @ h3 -> h4
1145 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1148 vst4.32 {$D0#lo[0],$D1#lo[0],$D2#lo[0],$D3#lo[0]},[$ctx]!
1149 vst1.32 {$D4#lo[0]},[$ctx]
1151 vldmia sp!,{d8-d15} @ epilogue
1155 .size poly1305_blocks_neon,.-poly1305_blocks_neon
1157 .type poly1305_emit_neon,%function
1160 ldr ip,[$ctx,#36] @ is_base2_26
1165 beq .Lpoly1305_emit_enter
1167 ldmia $ctx,{$h0-$h4}
1170 adds $h0,$h0,$h1,lsl#26 @ base 2^26 -> base 2^32
1172 adcs $h1,$h1,$h2,lsl#20
1174 adcs $h2,$h2,$h3,lsl#14
1176 adcs $h3,$h3,$h4,lsl#8
1177 adc $h4,$g0,$h4,lsr#24 @ can be partially reduced ...
1179 and $g0,$h4,#-4 @ ... so reduce
1181 add $g0,$g0,$g0,lsr#2 @ *= 5
1188 adds $g0,$h0,#5 @ compare to modulus
1193 tst $g4,#4 @ did it carry/borrow?
1206 ldr $g3,[$nonce,#12]
1208 adds $h0,$h0,$g0 @ accumulate nonce
1219 str $h0,[$mac,#0] @ store the result
1226 .size poly1305_emit_neon,.-poly1305_emit_neon
1230 .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1232 .word OPENSSL_armcap_P-.Lpoly1305_init
1237 .asciz "Poly1305 for ARMv4/NEON, CRYPTOGAMS by <appro\@openssl.org>"
1239 #if __ARM_MAX_ARCH__>=7
1240 .comm OPENSSL_armcap_P,4,4
1244 foreach (split("\n",$code)) {
1245 s/\`([^\`]*)\`/eval $1/geo;
1247 s/\bq([0-9]+)#(lo|hi)/sprintf "d%d",2*$1+($2 eq "hi")/geo or
1248 s/\bret\b/bx lr/go or
1249 s/\bbx\s+lr\b/.word\t0xe12fff1e/go; # make it possible to compile with -march=armv4
1253 close STDOUT; # enforce flush