2 # Copyright 2014-2016 The OpenSSL Project Authors. All Rights Reserved.
4 # Licensed under the OpenSSL license (the "License"). You may not use
5 # this file except in compliance with the License. You can obtain a copy
6 # in the file LICENSE in the source distribution or at
7 # https://www.openssl.org/source/license.html
10 # ====================================================================
11 # Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
12 # project. The module is, however, dual licensed under OpenSSL and
13 # CRYPTOGAMS licenses depending on where you obtain it. For further
14 # details see http://www.openssl.org/~appro/cryptogams/.
15 # ====================================================================
17 # GHASH for ARMv8 Crypto Extension, 64-bit polynomial multiplication.
21 # Initial version was developed in tight cooperation with Ard
22 # Biesheuvel <ard.biesheuvel@linaro.org> from bits-n-pieces from
23 # other assembly modules. Just like aesv8-armx.pl this module
24 # supports both AArch32 and AArch64 execution modes.
28 # Implement 2x aggregated reduction [see ghash-x86.pl for background
31 # Current performance in cycles per processed byte:
33 # PMULL[2] 32-bit NEON(*)
35 # Cortex-A53 1.01 8.39
36 # Cortex-A57 1.17 7.61
39 # (*) presented for reference/comparison purposes;
44 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
45 ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
46 ( $xlate="${dir}../../perlasm/arm-xlate.pl" and -f $xlate) or
47 die "can't locate arm-xlate.pl";
49 open OUT,"| \"$^X\" $xlate $flavour $output";
52 $Xi="x0"; # argument block
60 my ($Xl,$Xm,$Xh,$IN)=map("q$_",(0..3));
61 my ($t0,$t1,$t2,$xC2,$H,$Hhl,$H2)=map("q$_",(8..14));
68 $code.=".arch armv8-a+crypto\n" if ($flavour =~ /64/);
69 $code.=".fpu neon\n.code 32\n" if ($flavour !~ /64/);
71 ################################################################################
72 # void gcm_init_v8(u128 Htable[16],const u64 H[2]);
74 # input: 128-bit H - secret parameter E(K,0^128)
75 # output: precomputed table filled with degrees of twisted H;
76 # H is twisted to handle reverse bitness of GHASH;
77 # only few of 16 slots of Htable[16] are used;
78 # data is opaque to outside world (which allows to
79 # optimize the code independently);
83 .type gcm_init_v8,%function
86 vld1.64 {$t1},[x1] @ load input H
88 vshl.i64 $xC2,$xC2,#57 @ 0xc2.0
92 vext.8 $t0,$t2,$xC2,#8 @ t0=0xc2....01
94 vshr.s32 $t1,$t1,#31 @ broadcast carry bit
99 vorr $IN,$IN,$t2 @ H<<<=1
100 veor $H,$IN,$t0 @ twisted H
101 vst1.64 {$H},[x0],#16 @ store Htable[0]
104 vext.8 $t0,$H,$H,#8 @ Karatsuba pre-processing
107 vpmull2.p64 $Xh,$H,$H
108 vpmull.p64 $Xm,$t0,$t0
110 vext.8 $t1,$Xl,$Xh,#8 @ Karatsuba post-processing
114 vpmull.p64 $t2,$Xl,$xC2 @ 1st phase
116 vmov $Xh#lo,$Xm#hi @ Xh|Xm - 256-bit result
117 vmov $Xm#hi,$Xl#lo @ Xm is rotated Xl
120 vext.8 $t2,$Xl,$Xl,#8 @ 2nd phase
121 vpmull.p64 $Xl,$Xl,$xC2
125 vext.8 $t1,$H2,$H2,#8 @ Karatsuba pre-processing
127 vext.8 $Hhl,$t0,$t1,#8 @ pack Karatsuba pre-processed
128 vst1.64 {$Hhl-$H2},[x0] @ store Htable[1..2]
131 .size gcm_init_v8,.-gcm_init_v8
133 ################################################################################
134 # void gcm_gmult_v8(u64 Xi[2],const u128 Htable[16]);
136 # input: Xi - current hash value;
137 # Htable - table precomputed in gcm_init_v8;
138 # output: Xi - next hash value Xi;
142 .type gcm_gmult_v8,%function
145 vld1.64 {$t1},[$Xi] @ load Xi
147 vld1.64 {$H-$Hhl},[$Htbl] @ load twisted H, ...
148 vshl.u64 $xC2,$xC2,#57
152 vext.8 $IN,$t1,$t1,#8
154 vpmull.p64 $Xl,$H,$IN @ H.lo·Xi.lo
155 veor $t1,$t1,$IN @ Karatsuba pre-processing
156 vpmull2.p64 $Xh,$H,$IN @ H.hi·Xi.hi
157 vpmull.p64 $Xm,$Hhl,$t1 @ (H.lo+H.hi)·(Xi.lo+Xi.hi)
159 vext.8 $t1,$Xl,$Xh,#8 @ Karatsuba post-processing
163 vpmull.p64 $t2,$Xl,$xC2 @ 1st phase of reduction
165 vmov $Xh#lo,$Xm#hi @ Xh|Xm - 256-bit result
166 vmov $Xm#hi,$Xl#lo @ Xm is rotated Xl
169 vext.8 $t2,$Xl,$Xl,#8 @ 2nd phase of reduction
170 vpmull.p64 $Xl,$Xl,$xC2
177 vext.8 $Xl,$Xl,$Xl,#8
178 vst1.64 {$Xl},[$Xi] @ write out Xi
181 .size gcm_gmult_v8,.-gcm_gmult_v8
183 ################################################################################
184 # void gcm_ghash_v8(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len);
186 # input: table precomputed in gcm_init_v8;
187 # current hash value Xi;
188 # pointer to input data;
189 # length of input data in bytes, but divisible by block size;
190 # output: next hash value Xi;
194 .type gcm_ghash_v8,%function
198 $code.=<<___ if ($flavour !~ /64/);
199 vstmdb sp!,{d8-d15} @ 32-bit ABI says so
202 vld1.64 {$Xl},[$Xi] @ load [rotated] Xi
203 @ "[rotated]" means that
204 @ loaded value would have
205 @ to be rotated in order to
206 @ make it appear as in
207 @ alorithm specification
208 subs $len,$len,#32 @ see if $len is 32 or larger
209 mov $inc,#16 @ $inc is used as post-
210 @ increment for input pointer;
211 @ as loop is modulo-scheduled
212 @ $inc is zeroed just in time
213 @ to preclude oversteping
214 @ inp[len], which means that
215 @ last block[s] are actually
216 @ loaded twice, but last
217 @ copy is not processed
218 vld1.64 {$H-$Hhl},[$Htbl],#32 @ load twisted H, ..., H^2
220 vld1.64 {$H2},[$Htbl]
221 cclr $inc,eq @ is it time to zero $inc?
222 vext.8 $Xl,$Xl,$Xl,#8 @ rotate Xi
223 vld1.64 {$t0},[$inp],#16 @ load [rotated] I[0]
224 vshl.u64 $xC2,$xC2,#57 @ compose 0xc2.0 constant
229 vext.8 $IN,$t0,$t0,#8 @ rotate I[0]
230 b.lo .Lodd_tail_v8 @ $len was less than 32
232 { my ($Xln,$Xmn,$Xhn,$In) = map("q$_",(4..7));
234 # Xi+2 =[H*(Ii+1 + Xi+1)] mod P =
235 # [(H*Ii+1) + (H*Xi+1)] mod P =
236 # [(H*Ii+1) + H^2*(Ii+Xi)] mod P
239 vld1.64 {$t1},[$inp],$inc @ load [rotated] I[1]
243 vext.8 $In,$t1,$t1,#8
244 veor $IN,$IN,$Xl @ I[i]^=Xi
245 vpmull.p64 $Xln,$H,$In @ H·Ii+1
246 veor $t1,$t1,$In @ Karatsuba pre-processing
247 vpmull2.p64 $Xhn,$H,$In
252 vext.8 $t2,$IN,$IN,#8
253 subs $len,$len,#32 @ is there more data?
254 vpmull.p64 $Xl,$H2,$IN @ H^2.lo·Xi.lo
255 cclr $inc,lo @ is it time to zero $inc?
257 vpmull.p64 $Xmn,$Hhl,$t1
258 veor $t2,$t2,$IN @ Karatsuba pre-processing
259 vpmull2.p64 $Xh,$H2,$IN @ H^2.hi·Xi.hi
260 veor $Xl,$Xl,$Xln @ accumulate
261 vpmull2.p64 $Xm,$Hhl,$t2 @ (H^2.lo+H^2.hi)·(Xi.lo+Xi.hi)
262 vld1.64 {$t0},[$inp],$inc @ load [rotated] I[i+2]
265 cclr $inc,eq @ is it time to zero $inc?
268 vext.8 $t1,$Xl,$Xh,#8 @ Karatsuba post-processing
271 vld1.64 {$t1},[$inp],$inc @ load [rotated] I[i+3]
276 vpmull.p64 $t2,$Xl,$xC2 @ 1st phase of reduction
281 vmov $Xh#lo,$Xm#hi @ Xh|Xm - 256-bit result
282 vmov $Xm#hi,$Xl#lo @ Xm is rotated Xl
283 vext.8 $In,$t1,$t1,#8
284 vext.8 $IN,$t0,$t0,#8
286 vpmull.p64 $Xln,$H,$In @ H·Ii+1
287 veor $IN,$IN,$Xh @ accumulate $IN early
289 vext.8 $t2,$Xl,$Xl,#8 @ 2nd phase of reduction
290 vpmull.p64 $Xl,$Xl,$xC2
292 veor $t1,$t1,$In @ Karatsuba pre-processing
294 vpmull2.p64 $Xhn,$H,$In
295 b.hs .Loop_mod2x_v8 @ there was at least 32 more bytes
298 vext.8 $IN,$t0,$t0,#8 @ re-construct $IN
299 adds $len,$len,#32 @ re-construct $len
300 veor $Xl,$Xl,$Xh @ re-construct $Xl
301 b.eq .Ldone_v8 @ is $len zero?
306 vext.8 $t2,$Xl,$Xl,#8
307 veor $IN,$IN,$Xl @ inp^=Xi
308 veor $t1,$t0,$t2 @ $t1 is rotated inp^Xi
310 vpmull.p64 $Xl,$H,$IN @ H.lo·Xi.lo
311 veor $t1,$t1,$IN @ Karatsuba pre-processing
312 vpmull2.p64 $Xh,$H,$IN @ H.hi·Xi.hi
313 vpmull.p64 $Xm,$Hhl,$t1 @ (H.lo+H.hi)·(Xi.lo+Xi.hi)
315 vext.8 $t1,$Xl,$Xh,#8 @ Karatsuba post-processing
319 vpmull.p64 $t2,$Xl,$xC2 @ 1st phase of reduction
321 vmov $Xh#lo,$Xm#hi @ Xh|Xm - 256-bit result
322 vmov $Xm#hi,$Xl#lo @ Xm is rotated Xl
325 vext.8 $t2,$Xl,$Xl,#8 @ 2nd phase of reduction
326 vpmull.p64 $Xl,$Xl,$xC2
334 vext.8 $Xl,$Xl,$Xl,#8
335 vst1.64 {$Xl},[$Xi] @ write out Xi
338 $code.=<<___ if ($flavour !~ /64/);
339 vldmia sp!,{d8-d15} @ 32-bit ABI says so
343 .size gcm_ghash_v8,.-gcm_ghash_v8
347 .asciz "GHASH for ARMv8, CRYPTOGAMS by <appro\@openssl.org>"
351 if ($flavour =~ /64/) { ######## 64-bit code
355 $arg =~ m/q([0-9]+)#(lo|hi),\s*q([0-9]+)#(lo|hi)/o &&
356 sprintf "ins v%d.d[%d],v%d.d[%d]",$1,($2 eq "lo")?0:1,$3,($4 eq "lo")?0:1;
358 foreach(split("\n",$code)) {
359 s/cclr\s+([wx])([^,]+),\s*([a-z]+)/csel $1$2,$1zr,$1$2,$3/o or
360 s/vmov\.i8/movi/o or # fix up legacy mnemonics
361 s/vmov\s+(.*)/unvmov($1)/geo or
363 s/vshr\.s/sshr\.s/o or
365 s/^(\s+)v/$1/o or # strip off v prefix
368 s/\bq([0-9]+)\b/"v".($1<8?$1:$1+8).".16b"/geo; # old->new registers
369 s/@\s/\/\//o; # old->new style commentary
371 # fix up remainig legacy suffixes
373 s/\.[uis]?32//o and s/\.16b/\.4s/go;
374 m/\.p64/o and s/\.16b/\.1q/o; # 1st pmull argument
375 m/l\.p64/o and s/\.16b/\.1d/go; # 2nd and 3rd pmull arguments
376 s/\.[uisp]?64//o and s/\.16b/\.2d/go;
377 s/\.[42]([sd])\[([0-3])\]/\.$1\[$2\]/o;
381 } else { ######## 32-bit code
385 $arg =~ m/q([0-9]+),\s*q([0-9]+)\[([0-3])\]/o &&
386 sprintf "vdup.32 q%d,d%d[%d]",$1,2*$2+($3>>1),$3&1;
389 my ($mnemonic,$arg)=@_;
391 if ($arg =~ m/q([0-9]+),\s*q([0-9]+),\s*q([0-9]+)/o) {
392 my $word = 0xf2a00e00|(($1&7)<<13)|(($1&8)<<19)
393 |(($2&7)<<17)|(($2&8)<<4)
394 |(($3&7)<<1) |(($3&8)<<2);
395 $word |= 0x00010001 if ($mnemonic =~ "2");
396 # since ARMv7 instructions are always encoded little-endian.
397 # correct solution is to use .inst directive, but older
398 # assemblers don't implement it:-(
399 sprintf ".byte\t0x%02x,0x%02x,0x%02x,0x%02x\t@ %s %s",
400 $word&0xff,($word>>8)&0xff,
401 ($word>>16)&0xff,($word>>24)&0xff,
406 foreach(split("\n",$code)) {
407 s/\b[wx]([0-9]+)\b/r$1/go; # new->old registers
408 s/\bv([0-9])\.[12468]+[bsd]\b/q$1/go; # new->old registers
409 s/\/\/\s?/@ /o; # new->old style commentary
411 # fix up remainig new-style suffixes
414 s/cclr\s+([^,]+),\s*([a-z]+)/mov$2 $1,#0/o or
415 s/vdup\.32\s+(.*)/unvdup32($1)/geo or
416 s/v?(pmull2?)\.p64\s+(.*)/unvpmullp64($1,$2)/geo or
417 s/\bq([0-9]+)#(lo|hi)/sprintf "d%d",2*$1+($2 eq "hi")/geo or
419 s/^(\s+)ret/$1bx\tlr/o;
425 close STDOUT; # enforce flush