2 # Copyright 2014-2018 The OpenSSL Project Authors. All Rights Reserved.
4 # Licensed under the Apache License 2.0 (the "License"). You may not use
5 # this file except in compliance with the License. You can obtain a copy
6 # in the file LICENSE in the source distribution or at
7 # https://www.openssl.org/source/license.html
10 # ====================================================================
11 # Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
12 # project. The module is, however, dual licensed under OpenSSL and
13 # CRYPTOGAMS licenses depending on where you obtain it. For further
14 # details see http://www.openssl.org/~appro/cryptogams/.
15 # ====================================================================
17 # GHASH for ARMv8 Crypto Extension, 64-bit polynomial multiplication.
21 # Initial version was developed in tight cooperation with Ard
22 # Biesheuvel of Linaro from bits-n-pieces from other assembly modules.
23 # Just like aesv8-armx.pl this module supports both AArch32 and
24 # AArch64 execution modes.
28 # Implement 2x aggregated reduction [see ghash-x86.pl for background
33 # AArch64 register bank to "accommodate" 4x aggregated reduction and
34 # improve performance by 20-70% depending on processor.
36 # Current performance in cycles per processed byte:
38 # 64-bit PMULL 32-bit PMULL 32-bit NEON(*)
39 # Apple A7 0.58 0.92 5.62
40 # Cortex-A53 0.85 1.01 8.39
41 # Cortex-A57 0.73 1.17 7.61
42 # Denver 0.51 0.65 6.02
43 # Mongoose 0.65 1.10 8.06
47 # (*) presented for reference/comparison purposes;
49 # $output is the last argument if it looks like a file (it has an extension)
50 # $flavour is the first argument if it doesn't look like a file
51 $output = $#ARGV >= 0 && $ARGV[$#ARGV] =~ m|\.\w+$| ? pop : undef;
52 $flavour = $#ARGV >= 0 && $ARGV[0] !~ m|\.| ? shift : undef;
54 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
55 ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
56 ( $xlate="${dir}../../perlasm/arm-xlate.pl" and -f $xlate) or
57 die "can't locate arm-xlate.pl";
59 open OUT,"| \"$^X\" $xlate $flavour \"$output\""
60 or die "can't call $xlate: $!";
63 $Xi="x0"; # argument block
71 my ($Xl,$Xm,$Xh,$IN)=map("q$_",(0..3));
72 my ($t0,$t1,$t2,$xC2,$H,$Hhl,$H2)=map("q$_",(8..14));
73 my $_byte = ($flavour =~ /win/ ? "DCB" : ".byte");
78 #if __ARM_MAX_ARCH__>=7
80 $code.=".arch armv8-a+crypto\n.text\n" if ($flavour =~ /64/);
81 $code.=<<___ if ($flavour !~ /64/);
86 # define INST(a,b,c,d) $_byte c,0xef,a,b
89 # define INST(a,b,c,d) $_byte a,b,c,0xf2
95 ################################################################################
96 # void gcm_init_v8(u128 Htable[16],const u64 H[2]);
98 # input: 128-bit H - secret parameter E(K,0^128)
99 # output: precomputed table filled with degrees of twisted H;
100 # H is twisted to handle reverse bitness of GHASH;
101 # only few of 16 slots of Htable[16] are used;
102 # data is opaque to outside world (which allows to
103 # optimize the code independently);
107 .type gcm_init_v8,%function
110 vld1.64 {$t1},[x1] @ load input H
112 vshl.i64 $xC2,$xC2,#57 @ 0xc2.0
113 vext.8 $IN,$t1,$t1,#8
114 vshr.u64 $t2,$xC2,#63
116 vext.8 $t0,$t2,$xC2,#8 @ t0=0xc2....01
118 vshr.s32 $t1,$t1,#31 @ broadcast carry bit
121 vext.8 $t2,$t2,$t2,#8
123 vorr $IN,$IN,$t2 @ H<<<=1
124 veor $H,$IN,$t0 @ twisted H
125 vst1.64 {$H},[x0],#16 @ store Htable[0]
128 vext.8 $t0,$H,$H,#8 @ Karatsuba pre-processing
131 vpmull2.p64 $Xh,$H,$H
132 vpmull.p64 $Xm,$t0,$t0
134 vext.8 $t1,$Xl,$Xh,#8 @ Karatsuba post-processing
138 vpmull.p64 $t2,$Xl,$xC2 @ 1st phase
140 vmov $Xh#lo,$Xm#hi @ Xh|Xm - 256-bit result
141 vmov $Xm#hi,$Xl#lo @ Xm is rotated Xl
144 vext.8 $t2,$Xl,$Xl,#8 @ 2nd phase
145 vpmull.p64 $Xl,$Xl,$xC2
149 vext.8 $t1,$H2,$H2,#8 @ Karatsuba pre-processing
151 vext.8 $Hhl,$t0,$t1,#8 @ pack Karatsuba pre-processed
152 vst1.64 {$Hhl-$H2},[x0],#32 @ store Htable[1..2]
154 if ($flavour =~ /64/) {
155 my ($t3,$Yl,$Ym,$Yh) = map("q$_",(4..7));
158 @ calculate H^3 and H^4
159 vpmull.p64 $Xl,$H, $H2
160 vpmull.p64 $Yl,$H2,$H2
161 vpmull2.p64 $Xh,$H, $H2
162 vpmull2.p64 $Yh,$H2,$H2
163 vpmull.p64 $Xm,$t0,$t1
164 vpmull.p64 $Ym,$t1,$t1
166 vext.8 $t0,$Xl,$Xh,#8 @ Karatsuba post-processing
167 vext.8 $t1,$Yl,$Yh,#8
173 vpmull.p64 $t2,$Xl,$xC2 @ 1st phase
175 vpmull.p64 $t3,$Yl,$xC2
177 vmov $Xh#lo,$Xm#hi @ Xh|Xm - 256-bit result
179 vmov $Xm#hi,$Xl#lo @ Xm is rotated Xl
184 vext.8 $t2,$Xl,$Xl,#8 @ 2nd phase
185 vext.8 $t3,$Yl,$Yl,#8
186 vpmull.p64 $Xl,$Xl,$xC2
187 vpmull.p64 $Yl,$Yl,$xC2
190 veor $H, $Xl,$t2 @ H^3
191 veor $H2,$Yl,$t3 @ H^4
193 vext.8 $t0,$H, $H,#8 @ Karatsuba pre-processing
194 vext.8 $t1,$H2,$H2,#8
197 vext.8 $Hhl,$t0,$t1,#8 @ pack Karatsuba pre-processed
198 vst1.64 {$H-$H2},[x0] @ store Htable[3..5]
203 .size gcm_init_v8,.-gcm_init_v8
205 ################################################################################
206 # void gcm_gmult_v8(u64 Xi[2],const u128 Htable[16]);
208 # input: Xi - current hash value;
209 # Htable - table precomputed in gcm_init_v8;
210 # output: Xi - next hash value Xi;
214 .type gcm_gmult_v8,%function
217 vld1.64 {$t1},[$Xi] @ load Xi
219 vld1.64 {$H-$Hhl},[$Htbl] @ load twisted H, ...
220 vshl.u64 $xC2,$xC2,#57
224 vext.8 $IN,$t1,$t1,#8
226 vpmull.p64 $Xl,$H,$IN @ H.lo·Xi.lo
227 veor $t1,$t1,$IN @ Karatsuba pre-processing
228 vpmull2.p64 $Xh,$H,$IN @ H.hi·Xi.hi
229 vpmull.p64 $Xm,$Hhl,$t1 @ (H.lo+H.hi)·(Xi.lo+Xi.hi)
231 vext.8 $t1,$Xl,$Xh,#8 @ Karatsuba post-processing
235 vpmull.p64 $t2,$Xl,$xC2 @ 1st phase of reduction
237 vmov $Xh#lo,$Xm#hi @ Xh|Xm - 256-bit result
238 vmov $Xm#hi,$Xl#lo @ Xm is rotated Xl
241 vext.8 $t2,$Xl,$Xl,#8 @ 2nd phase of reduction
242 vpmull.p64 $Xl,$Xl,$xC2
249 vext.8 $Xl,$Xl,$Xl,#8
250 vst1.64 {$Xl},[$Xi] @ write out Xi
253 .size gcm_gmult_v8,.-gcm_gmult_v8
255 ################################################################################
256 # void gcm_ghash_v8(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len);
258 # input: table precomputed in gcm_init_v8;
259 # current hash value Xi;
260 # pointer to input data;
261 # length of input data in bytes, but divisible by block size;
262 # output: next hash value Xi;
266 .type gcm_ghash_v8,%function
270 $code.=<<___ if ($flavour =~ /64/);
272 b.hs .Lgcm_ghash_v8_4x
274 $code.=<<___ if ($flavour !~ /64/);
275 vstmdb sp!,{d8-d15} @ 32-bit ABI says so
278 vld1.64 {$Xl},[$Xi] @ load [rotated] Xi
279 @ "[rotated]" means that
280 @ loaded value would have
281 @ to be rotated in order to
282 @ make it appear as in
283 @ algorithm specification
284 subs $len,$len,#32 @ see if $len is 32 or larger
285 mov $inc,#16 @ $inc is used as post-
286 @ increment for input pointer;
287 @ as loop is modulo-scheduled
288 @ $inc is zeroed just in time
289 @ to preclude overstepping
290 @ inp[len], which means that
291 @ last block[s] are actually
292 @ loaded twice, but last
293 @ copy is not processed
294 vld1.64 {$H-$Hhl},[$Htbl],#32 @ load twisted H, ..., H^2
296 vld1.64 {$H2},[$Htbl]
297 cclr $inc,eq @ is it time to zero $inc?
298 vext.8 $Xl,$Xl,$Xl,#8 @ rotate Xi
299 vld1.64 {$t0},[$inp],#16 @ load [rotated] I[0]
300 vshl.u64 $xC2,$xC2,#57 @ compose 0xc2.0 constant
305 vext.8 $IN,$t0,$t0,#8 @ rotate I[0]
306 b.lo .Lodd_tail_v8 @ $len was less than 32
308 { my ($Xln,$Xmn,$Xhn,$In) = map("q$_",(4..7));
310 # Xi+2 =[H*(Ii+1 + Xi+1)] mod P =
311 # [(H*Ii+1) + (H*Xi+1)] mod P =
312 # [(H*Ii+1) + H^2*(Ii+Xi)] mod P
315 vld1.64 {$t1},[$inp],$inc @ load [rotated] I[1]
319 vext.8 $In,$t1,$t1,#8
320 veor $IN,$IN,$Xl @ I[i]^=Xi
321 vpmull.p64 $Xln,$H,$In @ H·Ii+1
322 veor $t1,$t1,$In @ Karatsuba pre-processing
323 vpmull2.p64 $Xhn,$H,$In
328 vext.8 $t2,$IN,$IN,#8
329 subs $len,$len,#32 @ is there more data?
330 vpmull.p64 $Xl,$H2,$IN @ H^2.lo·Xi.lo
331 cclr $inc,lo @ is it time to zero $inc?
333 vpmull.p64 $Xmn,$Hhl,$t1
334 veor $t2,$t2,$IN @ Karatsuba pre-processing
335 vpmull2.p64 $Xh,$H2,$IN @ H^2.hi·Xi.hi
336 veor $Xl,$Xl,$Xln @ accumulate
337 vpmull2.p64 $Xm,$Hhl,$t2 @ (H^2.lo+H^2.hi)·(Xi.lo+Xi.hi)
338 vld1.64 {$t0},[$inp],$inc @ load [rotated] I[i+2]
341 cclr $inc,eq @ is it time to zero $inc?
344 vext.8 $t1,$Xl,$Xh,#8 @ Karatsuba post-processing
347 vld1.64 {$t1},[$inp],$inc @ load [rotated] I[i+3]
352 vpmull.p64 $t2,$Xl,$xC2 @ 1st phase of reduction
357 vmov $Xh#lo,$Xm#hi @ Xh|Xm - 256-bit result
358 vmov $Xm#hi,$Xl#lo @ Xm is rotated Xl
359 vext.8 $In,$t1,$t1,#8
360 vext.8 $IN,$t0,$t0,#8
362 vpmull.p64 $Xln,$H,$In @ H·Ii+1
363 veor $IN,$IN,$Xh @ accumulate $IN early
365 vext.8 $t2,$Xl,$Xl,#8 @ 2nd phase of reduction
366 vpmull.p64 $Xl,$Xl,$xC2
368 veor $t1,$t1,$In @ Karatsuba pre-processing
370 vpmull2.p64 $Xhn,$H,$In
371 b.hs .Loop_mod2x_v8 @ there was at least 32 more bytes
374 vext.8 $IN,$t0,$t0,#8 @ re-construct $IN
375 adds $len,$len,#32 @ re-construct $len
376 veor $Xl,$Xl,$Xh @ re-construct $Xl
377 b.eq .Ldone_v8 @ is $len zero?
382 vext.8 $t2,$Xl,$Xl,#8
383 veor $IN,$IN,$Xl @ inp^=Xi
384 veor $t1,$t0,$t2 @ $t1 is rotated inp^Xi
386 vpmull.p64 $Xl,$H,$IN @ H.lo·Xi.lo
387 veor $t1,$t1,$IN @ Karatsuba pre-processing
388 vpmull2.p64 $Xh,$H,$IN @ H.hi·Xi.hi
389 vpmull.p64 $Xm,$Hhl,$t1 @ (H.lo+H.hi)·(Xi.lo+Xi.hi)
391 vext.8 $t1,$Xl,$Xh,#8 @ Karatsuba post-processing
395 vpmull.p64 $t2,$Xl,$xC2 @ 1st phase of reduction
397 vmov $Xh#lo,$Xm#hi @ Xh|Xm - 256-bit result
398 vmov $Xm#hi,$Xl#lo @ Xm is rotated Xl
401 vext.8 $t2,$Xl,$Xl,#8 @ 2nd phase of reduction
402 vpmull.p64 $Xl,$Xl,$xC2
410 vext.8 $Xl,$Xl,$Xl,#8
411 vst1.64 {$Xl},[$Xi] @ write out Xi
414 $code.=<<___ if ($flavour !~ /64/);
415 vldmia sp!,{d8-d15} @ 32-bit ABI says so
419 .size gcm_ghash_v8,.-gcm_ghash_v8
422 if ($flavour =~ /64/) { # 4x subroutine
424 $I1,$I2,$I3,$H3,$H34,$H4,$Yl,$Ym,$Yh) = map("q$_",(4..7,15..23));
427 .type gcm_ghash_v8_4x,%function
431 vld1.64 {$Xl},[$Xi] @ load [rotated] Xi
432 vld1.64 {$H-$H2},[$Htbl],#48 @ load twisted H, ..., H^2
434 vld1.64 {$H3-$H4},[$Htbl] @ load twisted H^3, ..., H^4
435 vshl.u64 $xC2,$xC2,#57 @ compose 0xc2.0 constant
437 vld1.64 {$I0-$j3},[$inp],#64
445 vext.8 $I3,$j3,$j3,#8
446 vext.8 $I2,$j2,$j2,#8
447 vext.8 $I1,$j1,$j1,#8
449 vpmull.p64 $Yl,$H,$I3 @ H·Ii+3
451 vpmull2.p64 $Yh,$H,$I3
452 vpmull.p64 $Ym,$Hhl,$j3
454 vpmull.p64 $t0,$H2,$I2 @ H^2·Ii+2
456 vpmull2.p64 $I2,$H2,$I2
457 vpmull2.p64 $j2,$Hhl,$j2
463 vpmull.p64 $j3,$H3,$I1 @ H^3·Ii+1
465 vpmull2.p64 $I1,$H3,$I1
466 vpmull.p64 $j1,$H34,$j1
480 vld1.64 {$I0-$j3},[$inp],#64
481 vext.8 $IN,$t0,$t0,#8
489 vpmull.p64 $Xl,$H4,$IN @ H^4·(Xi+Ii)
491 vpmull2.p64 $Xh,$H4,$IN
492 vext.8 $I3,$j3,$j3,#8
493 vpmull2.p64 $Xm,$H34,$t0
497 vext.8 $I2,$j2,$j2,#8
499 vext.8 $I1,$j1,$j1,#8
501 vext.8 $t1,$Xl,$Xh,#8 @ Karatsuba post-processing
503 vpmull.p64 $Yl,$H,$I3 @ H·Ii+3
506 vpmull2.p64 $Yh,$H,$I3
508 vpmull.p64 $Ym,$Hhl,$j3
510 vpmull.p64 $t2,$Xl,$xC2 @ 1st phase of reduction
511 vmov $Xh#lo,$Xm#hi @ Xh|Xm - 256-bit result
512 vmov $Xm#hi,$Xl#lo @ Xm is rotated Xl
513 vpmull.p64 $t0,$H2,$I2 @ H^2·Ii+2
515 vpmull2.p64 $I2,$H2,$I2
517 vpmull2.p64 $j2,$Hhl,$j2
523 vext.8 $t2,$Xl,$Xl,#8 @ 2nd phase of reduction
524 vpmull.p64 $Xl,$Xl,$xC2
525 vpmull.p64 $j3,$H3,$I1 @ H^3·Ii+1
528 vpmull2.p64 $I1,$H3,$I1
529 vpmull.p64 $j1,$H34,$j1
534 vext.8 $Xl,$Xl,$Xl,#8
542 vext.8 $IN,$t0,$t0,#8
544 vpmull.p64 $Xl,$H4,$IN @ H^4·(Xi+Ii)
546 vpmull2.p64 $Xh,$H4,$IN
547 vpmull2.p64 $Xm,$H34,$t0
560 vext.8 $t1,$Xl,$Xh,#8 @ Karatsuba post-processing
563 vld1.64 {$I0-$j2},[$inp]
571 vpmull.p64 $t2,$Xl,$xC2 @ 1st phase of reduction
572 vmov $Xh#lo,$Xm#hi @ Xh|Xm - 256-bit result
573 vmov $Xm#hi,$Xl#lo @ Xm is rotated Xl
574 vext.8 $I2,$j2,$j2,#8
575 vext.8 $I1,$j1,$j1,#8
578 vpmull.p64 $Yl,$H,$I2 @ H·Ii+2
581 vext.8 $t2,$Xl,$Xl,#8 @ 2nd phase of reduction
582 vpmull.p64 $Xl,$Xl,$xC2
584 vpmull2.p64 $Yh,$H,$I2
585 vpmull.p64 $Ym,$Hhl,$j2
587 vpmull.p64 $j3,$H2,$I1 @ H^2·Ii+1
589 vext.8 $Xl,$Xl,$Xl,#8
591 vpmull2.p64 $I1,$H2,$I1
593 vpmull2.p64 $j1,$Hhl,$j1
594 vext.8 $IN,$t0,$t0,#8
600 vpmull.p64 $Xl,$H3,$IN @ H^3·(Xi+Ii)
602 vpmull2.p64 $Xh,$H3,$IN
603 vpmull.p64 $Xm,$H34,$t0
612 vext.8 $t1,$Xl,$Xh,#8 @ Karatsuba post-processing
615 vld1.64 {$I0-$j1},[$inp]
622 vpmull.p64 $t2,$Xl,$xC2 @ 1st phase of reduction
623 vmov $Xh#lo,$Xm#hi @ Xh|Xm - 256-bit result
624 vmov $Xm#hi,$Xl#lo @ Xm is rotated Xl
625 vext.8 $I1,$j1,$j1,#8
628 vext.8 $t2,$Xl,$Xl,#8 @ 2nd phase of reduction
629 vpmull.p64 $Xl,$Xl,$xC2
632 vext.8 $Xl,$Xl,$Xl,#8
634 vpmull.p64 $Yl,$H,$I1 @ H·Ii+1
638 vext.8 $IN,$t0,$t0,#8
640 vpmull2.p64 $Yh,$H,$I1
641 vpmull.p64 $Ym,$Hhl,$j1
643 vpmull.p64 $Xl,$H2,$IN @ H^2·(Xi+Ii)
645 vpmull2.p64 $Xh,$H2,$IN
646 vpmull2.p64 $Xm,$Hhl,$t0
655 vext.8 $t1,$Xl,$Xh,#8 @ Karatsuba post-processing
664 vpmull.p64 $t2,$Xl,$xC2 @ 1st phase of reduction
665 vmov $Xh#lo,$Xm#hi @ Xh|Xm - 256-bit result
666 vmov $Xm#hi,$Xl#lo @ Xm is rotated Xl
669 vext.8 $t2,$Xl,$Xl,#8 @ 2nd phase of reduction
670 vpmull.p64 $Xl,$Xl,$xC2
673 vext.8 $Xl,$Xl,$Xl,#8
676 vext.8 $IN,$t0,$t0,#8
678 vpmull.p64 $Xl,$H,$IN
680 vpmull2.p64 $Xh,$H,$IN
681 vpmull.p64 $Xm,$Hhl,$t0
684 vext.8 $t1,$Xl,$Xh,#8 @ Karatsuba post-processing
689 vpmull.p64 $t2,$Xl,$xC2 @ 1st phase of reduction
690 vmov $Xh#lo,$Xm#hi @ Xh|Xm - 256-bit result
691 vmov $Xm#hi,$Xl#lo @ Xm is rotated Xl
694 vext.8 $t2,$Xl,$Xl,#8 @ 2nd phase of reduction
695 vpmull.p64 $Xl,$Xl,$xC2
698 vext.8 $Xl,$Xl,$Xl,#8
703 vst1.64 {$Xl},[$Xi] @ write out Xi
706 .size gcm_ghash_v8_4x,.-gcm_ghash_v8_4x
713 .asciz "GHASH for ARMv8, CRYPTOGAMS by <appro\@openssl.org>"
718 if ($flavour =~ /64/) { ######## 64-bit code
722 $arg =~ m/q([0-9]+)#(lo|hi),\s*q([0-9]+)#(lo|hi)/o &&
723 sprintf "ins v%d.d[%d],v%d.d[%d]",$1<8?$1:$1+8,($2 eq "lo")?0:1,
724 $3<8?$3:$3+8,($4 eq "lo")?0:1;
726 foreach(split("\n",$code)) {
727 s/cclr\s+([wx])([^,]+),\s*([a-z]+)/csel $1$2,$1zr,$1$2,$3/o or
728 s/vmov\.i8/movi/o or # fix up legacy mnemonics
729 s/vmov\s+(.*)/unvmov($1)/geo or
731 s/vshr\.s/sshr\.s/o or
733 s/^(\s+)v/$1/o or # strip off v prefix
736 s/\bq([0-9]+)\b/"v".($1<8?$1:$1+8).".16b"/geo; # old->new registers
737 s/@\s/\/\//o; # old->new style commentary
739 # fix up remaining legacy suffixes
741 s/\.[uis]?32//o and s/\.16b/\.4s/go;
742 m/\.p64/o and s/\.16b/\.1q/o; # 1st pmull argument
743 m/l\.p64/o and s/\.16b/\.1d/go; # 2nd and 3rd pmull arguments
744 s/\.[uisp]?64//o and s/\.16b/\.2d/go;
745 s/\.[42]([sd])\[([0-3])\]/\.$1\[$2\]/o;
749 } else { ######## 32-bit code
753 $arg =~ m/q([0-9]+),\s*q([0-9]+)\[([0-3])\]/o &&
754 sprintf "vdup.32 q%d,d%d[%d]",$1,2*$2+($3>>1),$3&1;
757 my ($mnemonic,$arg)=@_;
759 if ($arg =~ m/q([0-9]+),\s*q([0-9]+),\s*q([0-9]+)/o) {
760 my $word = 0xf2a00e00|(($1&7)<<13)|(($1&8)<<19)
761 |(($2&7)<<17)|(($2&8)<<4)
762 |(($3&7)<<1) |(($3&8)<<2);
763 $word |= 0x00010001 if ($mnemonic =~ "2");
764 # since ARMv7 instructions are always encoded little-endian.
765 # correct solution is to use .inst directive, but older
766 # assemblers don't implement it:-(
767 sprintf "INST(0x%02x,0x%02x,0x%02x,0x%02x)\t@ %s %s",
768 $word&0xff,($word>>8)&0xff,
769 ($word>>16)&0xff,($word>>24)&0xff,
774 foreach(split("\n",$code)) {
775 s/\b[wx]([0-9]+)\b/r$1/go; # new->old registers
776 s/\bv([0-9])\.[12468]+[bsd]\b/q$1/go; # new->old registers
777 s/\/\/\s?/@ /o; # new->old style commentary
779 # fix up remaining new-style suffixes
782 s/cclr\s+([^,]+),\s*([a-z]+)/mov.$2 $1,#0/o or
783 s/vdup\.32\s+(.*)/unvdup32($1)/geo or
784 s/v?(pmull2?)\.p64\s+(.*)/unvpmullp64($1,$2)/geo or
785 s/\bq([0-9]+)#(lo|hi)/sprintf "d%d",2*$1+($2 eq "hi")/geo or
787 s/^(\s+)ret/$1bx\tlr/o;
789 if (s/^(\s+)mov\.([a-z]+)/$1mov$2/) {
797 close STDOUT; # enforce flush