3 # ====================================================================
4 # Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
5 # project. Rights for redistribution and usage in source and binary
6 # forms are granted according to the OpenSSL license.
7 # ====================================================================
11 # "Teaser" Montgomery multiplication module for UltraSPARC. Why FPU?
12 # Because unlike integer multiplier, which simply stalls whole CPU,
13 # FPU is fully pipelined and can effectively emit 48 bit partial
14 # product every cycle. Why not blended SPARC v9? One can argue that
15 # making this module dependent on UltraSPARC VIS extension limits its
16 # binary compatibility. Well yes, it does exclude SPARC64 prior-V(!)
17 # implementations from compatibility matrix. But the rest, whole Sun
18 # UltraSPARC family and brand new Fujitsu's SPARC64 V, all support
19 # VIS extension instructions used in this module. This is considered
20 # good enough to recommend HAL SPARC64 users [if any] to simply fall
21 # down to no-asm configuration.
23 # USI&II cores currently exhibit uniform 2x improvement [over pre-
24 # bn_mul_mont codebase] for all key lengths and benchmarks. On USIII
25 # performance improves few percents for shorter keys and worsens few
26 # percents for longer keys. This is because USIII integer multiplier
27 # is >3x faster than USI&II one, which is harder to match [but see
28 # TODO list below]. It should also be noted that SPARC64 V features
29 # out-of-order execution, which *might* mean that integer multiplier
30 # is pipelined, which in turn *might* be impossible to match... On
31 # additional note, SPARC64 V implements FP Multiply-Add instruction,
32 # which is perfectly usable in this context... In other words, as far
33 # as HAL/Fujitsu SPARC64 family goes, talk to the author:-)
35 # The implementation implies following "non-natural" limitations on
37 # - num may not be less than 4;
38 # - num has to be even;
39 # - ap, bp, rp, np has to be 64-bit aligned [which is not a problem
40 # as long as BIGNUM.d are malloc-ated];
41 # Failure to meet either condition has no fatal effects, simply
42 # doesn't give any performance gain.
45 # - modulo-schedule inner loop for better performance (on in-order
46 # execution core such as UltraSPARC this shall result in further
47 # noticeable(!) improvement);
48 # - dedicated squaring procedure[?];
50 $fname="bn_mul_mont_fpu";
52 for (@ARGV) { $bits=64 if (/\-m64/ || /\-xarch\=v9/); }
59 $frame=128; # 96 rounded up to largest known cache-line
63 # In order to provide for 32-/64-bit ABI duality, I keep integers wider
64 # than 32 bit in %g1-%g4 and %o0-%o5. %l0-%l7 and %i0-%i5 are used
65 # exclusively for pointers, indexes and other small values...
67 $rp="%i0"; # BN_ULONG *rp,
68 $ap="%i1"; # const BN_ULONG *ap,
69 $bp="%i2"; # const BN_ULONG *bp,
70 $np="%i3"; # const BN_ULONG *np,
71 $n0="%i4"; # const BN_ULONG *n0,
72 $num="%i5"; # int num);
75 $ap_l="%l1"; # a[num],n[num] are smashed to 32-bit words and saved
76 $ap_h="%l2"; # to these four vectors as double-precision FP values.
77 $np_l="%l3"; # This way a bunch of fxtods are eliminated in second
78 $np_h="%l4"; # loop and L1-cache aliasing is minimized...
81 $mask="%l7"; # 16-bit mask, 0xffff
83 $n0="%g4"; # reassigned(!) to "64-bit" register
84 $carry="%i4"; # %i4 reused(!) for a carry bit
86 # FP register naming chart
101 $ba="%f0"; $bb="%f2"; $bc="%f4"; $bd="%f6";
102 $na="%f8"; $nb="%f10"; $nc="%f12"; $nd="%f14";
103 $alo="%f16"; $alo_="%f17"; $ahi="%f18"; $ahi_="%f19";
104 $nlo="%f20"; $nlo_="%f21"; $nhi="%f22"; $nhi_="%f23";
106 $dota="%f24"; $dotb="%f26";
108 $aloa="%f32"; $alob="%f34"; $aloc="%f36"; $alod="%f38";
109 $ahia="%f40"; $ahib="%f42"; $ahic="%f44"; $ahid="%f46";
110 $nloa="%f48"; $nlob="%f50"; $nloc="%f52"; $nlod="%f54";
111 $nhia="%f56"; $nhib="%f58"; $nhic="%f60"; $nhid="%f62";
113 $ASI_FL16_P=0xD2; # magic ASI value to engage 16-bit FP load
116 .ident "UltraSPARC Montgomery multiply by <appro\@fy.chalmers.se>"
117 .section ".text",#alloc,#execinstr
122 save %sp,-$frame-$locals,%sp
123 sethi %hi(0xffff),$mask
124 or $mask,%lo(0xffff),$mask
129 andcc $num,1,%g0 ! $num has to be even...
131 clr %i0 ! signal "unsupported input value"
136 andcc %l0,7,%g0 ! ...and pointers has to be 8-byte aligned
138 clr %i0 ! signal "unsupported input value"
139 ld [%i4+0],$n0 ! $n0 reassigned, remember?
142 or %o0,$n0,$n0 ! $n0=n0[1].n0[0]
144 sll $num,3,$num ! num*=8
146 add %sp,$bias,%o0 ! real top of stack
148 add %o1,$num,%o1 ! %o1=num*5
150 and %o0,-2048,%o0 ! optimize TLB utilization
151 sub %o0,$bias,%sp ! alloca(5*num*8)
153 rd %asi,%o7 ! save %asi
154 add %sp,$bias+$frame+$locals,$tp
156 add $ap_l,$num,$ap_l ! [an]p_[lh] point at the vectors' ends !
161 wr %g0,$ASI_FL16_P,%asi ! setup %asi for 16-bit FP loads
163 add $rp,$num,$rp ! readjust input pointers to point
164 add $ap,$num,$ap ! at the ends too...
168 stx %o7,[%sp+$bias+$frame+48] ! save %asi
170 sub %g0,$num,$i ! i=-num
171 sub %g0,$num,$j ! j=-num
176 ldx [$bp+$i],%o0 ! bp[0]
177 ldx [$ap+$j],%o1 ! ap[0]
187 mulx %o1,%o0,%o0 ! ap[0]*bp[0]
188 mulx $n0,%o0,%o0 ! ap[0]*bp[0]*n0
189 stx %o0,[%sp+$bias+$frame+0]
191 ld [%o3+0],$alo_ ! load a[j] as pair of 32-bit words
195 ld [%o5+0],$nlo_ ! load n[j] as pair of 32-bit words
200 ! transfer b[i] to FPU as 4x16-bit values
210 ! transfer ap[0]*b[0]*n0 to FPU as 4x16-bit values
211 ldda [%sp+$bias+$frame+6]%asi,$na
213 ldda [%sp+$bias+$frame+4]%asi,$nb
215 ldda [%sp+$bias+$frame+2]%asi,$nc
217 ldda [%sp+$bias+$frame+0]%asi,$nd
220 std $alo,[$ap_l+$j] ! save smashed ap[j] in double format
224 std $nlo,[$np_l+$j] ! save smashed np[j] in double format
234 faddd $aloa,$nloa,$nloa
237 faddd $alob,$nlob,$nlob
240 faddd $aloc,$nloc,$nloc
243 faddd $alod,$nlod,$nlod
246 faddd $ahia,$nhia,$nhia
249 faddd $ahib,$nhib,$nhib
252 faddd $ahic,$nhic,$dota ! $nhic
253 faddd $ahid,$nhid,$dotb ! $nhid
255 faddd $nloc,$nhia,$nloc
256 faddd $nlod,$nhib,$nlod
263 std $nloa,[%sp+$bias+$frame+0]
264 std $nlob,[%sp+$bias+$frame+8]
265 std $nloc,[%sp+$bias+$frame+16]
266 std $nlod,[%sp+$bias+$frame+24]
267 ldx [%sp+$bias+$frame+0],%o0
268 ldx [%sp+$bias+$frame+8],%o1
269 ldx [%sp+$bias+$frame+16],%o2
270 ldx [%sp+$bias+$frame+24],%o3
277 add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15]
286 !or %o7,%o0,%o0 ! 64-bit result
287 srlx %o3,16,%g1 ! 34-bit carry
295 ld [%o3+0],$alo_ ! load a[j] as pair of 32-bit words
299 ld [%o4+0],$nlo_ ! load n[j] as pair of 32-bit words
309 std $alo,[$ap_l+$j] ! save smashed ap[j] in double format
313 std $nlo,[$np_l+$j] ! save smashed np[j] in double format
318 faddd $aloa,$nloa,$nloa
321 faddd $alob,$nlob,$nlob
324 faddd $aloc,$nloc,$nloc
327 faddd $alod,$nlod,$nlod
330 faddd $ahia,$nhia,$nhia
333 faddd $ahib,$nhib,$nhib
336 faddd $dota,$nloa,$nloa
337 faddd $dotb,$nlob,$nlob
338 faddd $ahic,$nhic,$dota ! $nhic
339 faddd $ahid,$nhid,$dotb ! $nhid
341 faddd $nloc,$nhia,$nloc
342 faddd $nlod,$nhib,$nlod
349 std $nloa,[%sp+$bias+$frame+0]
350 std $nlob,[%sp+$bias+$frame+8]
351 std $nloc,[%sp+$bias+$frame+16]
352 std $nlod,[%sp+$bias+$frame+24]
353 ldx [%sp+$bias+$frame+0],%o0
354 ldx [%sp+$bias+$frame+8],%o1
355 ldx [%sp+$bias+$frame+16],%o2
356 ldx [%sp+$bias+$frame+24],%o3
363 add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15]
372 or %o7,%o0,%o0 ! 64-bit result
374 srlx %o3,16,%g1 ! 34-bit carry
378 stx %o0,[$tp] ! tp[j-1]=
385 std $dota,[%sp+$bias+$frame+32]
386 std $dotb,[%sp+$bias+$frame+40]
387 ldx [%sp+$bias+$frame+32],%o0
388 ldx [%sp+$bias+$frame+40],%o1
401 stx %o0,[$tp] ! tp[num-1]=
407 sub %g0,$num,$j ! j=-num
408 add %sp,$bias+$frame+$locals,$tp
412 ldx [$bp+$i],%o0 ! bp[i]
413 ldx [$ap+$j],%o1 ! ap[0]
421 ldx [$tp],%o2 ! tp[0]
424 mulx $n0,%o0,%o0 ! (ap[0]*bp[i]+t[0])*n0
425 stx %o0,[%sp+$bias+$frame+0]
427 ! transfer b[i] to FPU as 4x16-bit values
433 ! transfer (ap[0]*b[i]+t[0])*n0 to FPU as 4x16-bit values
434 ldda [%sp+$bias+$frame+6]%asi,$na
436 ldda [%sp+$bias+$frame+4]%asi,$nb
438 ldda [%sp+$bias+$frame+2]%asi,$nc
440 ldda [%sp+$bias+$frame+0]%asi,$nd
442 ldd [$ap_l+$j],$alo ! load a[j] in double format
446 ldd [$np_l+$j],$nlo ! load n[j] in double format
456 faddd $aloa,$nloa,$nloa
459 faddd $alob,$nlob,$nlob
462 faddd $aloc,$nloc,$nloc
465 faddd $alod,$nlod,$nlod
468 faddd $ahia,$nhia,$nhia
471 faddd $ahib,$nhib,$nhib
474 faddd $ahic,$nhic,$dota ! $nhic
475 faddd $ahid,$nhid,$dotb ! $nhid
477 faddd $nloc,$nhia,$nloc
478 faddd $nlod,$nhib,$nlod
485 std $nloa,[%sp+$bias+$frame+0]
486 std $nlob,[%sp+$bias+$frame+8]
487 std $nloc,[%sp+$bias+$frame+16]
488 std $nlod,[%sp+$bias+$frame+24]
489 ldx [%sp+$bias+$frame+0],%o0
490 ldx [%sp+$bias+$frame+8],%o1
491 ldx [%sp+$bias+$frame+16],%o2
492 ldx [%sp+$bias+$frame+24],%o3
499 add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15]
509 or %o7,%o0,%o0 ! 64-bit result
513 srlx %o3,16,%g1 ! 34-bit carry
521 ldd [$ap_l+$j],$alo ! load a[j] in double format
523 ldd [$np_l+$j],$nlo ! load n[j] in double format
531 faddd $aloa,$nloa,$nloa
534 faddd $alob,$nlob,$nlob
537 faddd $aloc,$nloc,$nloc
540 faddd $alod,$nlod,$nlod
543 faddd $ahia,$nhia,$nhia
546 faddd $ahib,$nhib,$nhib
549 faddd $dota,$nloa,$nloa
550 faddd $dotb,$nlob,$nlob
551 faddd $ahic,$nhic,$dota ! $nhic
552 faddd $ahid,$nhid,$dotb ! $nhid
554 faddd $nloc,$nhia,$nloc
555 faddd $nlod,$nhib,$nlod
562 std $nloa,[%sp+$bias+$frame+0]
563 std $nlob,[%sp+$bias+$frame+8]
564 std $nloc,[%sp+$bias+$frame+16]
565 std $nlod,[%sp+$bias+$frame+24]
566 ldx [%sp+$bias+$frame+0],%o0
567 ldx [%sp+$bias+$frame+8],%o1
568 ldx [%sp+$bias+$frame+16],%o2
569 ldx [%sp+$bias+$frame+24],%o3
576 add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15]
585 or %o7,%o0,%o0 ! 64-bit result
587 srlx %o3,16,%g1 ! 34-bit carry
591 ldx [$tp+8],%o7 ! tp[j]
596 stx %o0,[$tp] ! tp[j-1]
603 std $dota,[%sp+$bias+$frame+32]
604 std $dotb,[%sp+$bias+$frame+40]
605 ldx [%sp+$bias+$frame+32],%o0
606 ldx [%sp+$bias+$frame+40],%o1
619 stx %o0,[$tp] ! tp[num-1]
628 sub %g0,$num,%o7 ! n=-num
629 cmp $carry,0 ! clears %icc.c
631 add $tp,8,$tp ! adjust tp to point at the end
635 cmp %o0,%o1 ! compare topmost words
636 bcs,pt %icc,.Lcopy ! %icc.c is clean if not taken
649 subccc $carry,0,$carry
651 sub %g0,$num,%o7 ! n=-num
662 sub %g0,$num,%o7 ! n=-num
675 ldx [%sp+$bias+$frame+48],%o7
676 wr %g0,%o7,%asi ! restore %asi
682 .type $fname,#function
683 .size $fname,(.-$fname)
686 $code =~ s/\`([^\`]*)\`/eval($1)/gem;
688 # Below substitution makes it possible to compile without demanding
689 # VIS extentions on command line, e.g. -xarch=v9 vs. -xarch=v9a. I
690 # dare to do this, because VIS capability is detected at run-time now
691 # and this routine is not called on CPU not capable to execute it. Do
692 # note that fzeros is not the only VIS dependency! Another dependency
693 # is implicit and is just _a_ numerical value loaded to %asi register,
694 # which assembler can't recognize as VIS specific...
695 $code =~ s/fzeros\s+%f([0-9]+)/
696 sprintf(".word\t0x%x\t! fzeros %%f%d",0x81b00c20|($1<<25),$1)