3 # ====================================================================
4 # Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
5 # project. The module is, however, dual licensed under OpenSSL and
6 # CRYPTOGAMS licenses depending on where you obtain it. For further
7 # details see http://www.openssl.org/~appro/cryptogams/.
8 # ====================================================================
12 # The reason for undertaken effort is basically following. Even though
13 # Power 6 CPU operates at incredible 4.7GHz clock frequency, its PKI
14 # performance was observed to be less than impressive, essentially as
15 # fast as 1.8GHz PPC970, or 2.6 times(!) slower than one would hope.
16 # Well, it's not surprising that IBM had to make some sacrifices to
17 # boost the clock frequency that much, but no overall improvement?
18 # Having observed how much difference did switching to FPU make on
19 # UltraSPARC, playing same stunt on Power 6 appeared appropriate...
20 # Unfortunately the resulting performance improvement is not as
21 # impressive, ~30%, and in absolute terms is still very far from what
22 # one would expect from 4.7GHz CPU. There is a chance that I'm doing
23 # something wrong, but in the lack of assembler level micro-profiling
24 # data or at least decent platform guide I can't tell... Or better
25 # results might be achieved with VMX... Anyway, this module provides
26 # *worse* performance on other PowerPC implementations, ~40-15% slower
27 # on PPC970 depending on key length and ~40% slower on Power 5 for all
28 # key lengths. As it's obviously inappropriate as "best all-round"
29 # alternative, it has to be complemented with run-time CPU family
30 # detection. Oh! It should also be noted that unlike other PowerPC
31 # implementation IALU ppc-mont.pl module performs *suboptimaly* on
32 # >=1024-bit key lengths on Power 6. It should also be noted that
33 # *everything* said so far applies to 64-bit builds! As far as 32-bit
34 # application executed on 64-bit CPU goes, this module is likely to
35 # become preferred choice, because it's easy to adapt it for such
36 # case and *is* faster than 32-bit ppc-mont.pl on *all* processors.
40 # Micro-profiling assisted optimization results in ~15% improvement
41 # over original ppc64-mont.pl version, or overall ~50% improvement
42 # over ppc.pl module on Power 6. If compared to ppc-mont.pl on same
43 # Power 6 CPU, this module is 5-150% faster depending on key length,
44 # [hereafter] more for longer keys. But if compared to ppc-mont.pl
45 # on 1.8GHz PPC970, it's only 5-55% faster. Still far from impressive
46 # in absolute terms, but it's apparently the way Power 6 is...
50 # Adapted for 32-bit build this module delivers 25-120%, more for
51 # longer keys, performance improvement on 1.8GHz PPC970. However!
52 # This implementation utilizes even 64-bit integer operations and
53 # trouble is that most PPC operating systems don't preserve upper
54 # halves of general purpose registers upong signal delivery. They do
55 # preserve them upon context switch, but not signalling:-( This means
56 # that asynchronous signals have to be blocked upon entry to this
57 # subroutine. Signal masking (and complementary unmasking) has quite
58 # an impact on performance, naturally larger for shorter keys. It's
59 # so severe that 512-bit key performance can be as low as 1/3 of
60 # expected one. This is why this routine can be engaged for longer
61 # key operations only, see crypto/ppccap.c for further details.
62 # Alternative is to break dependence on upper halves on GPRs...
63 # MacOS X is an exception from this and doesn't require signal
64 # masking, and that's where above improvement coefficients were
69 if ($flavour =~ /32/) {
72 $FRAME= $SIZE_T*12+8*12;
73 $fname= "bn_mul_mont_fpu64";
75 $STUX= "stwux"; # store indexed and update
78 } elsif ($flavour =~ /64/) {
81 $FRAME= $SIZE_T*12+8*12;
82 $fname= "bn_mul_mont_fpu64";
84 # same as above, but 64-bit mnemonics...
85 $STUX= "stdux"; # store indexed and update
88 } else { die "nonsense $flavour"; }
90 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
91 ( $xlate="${dir}ppc-xlate.pl" and -f $xlate ) or
92 ( $xlate="${dir}../../perlasm/ppc-xlate.pl" and -f $xlate) or
93 die "can't locate ppc-xlate.pl";
95 open STDOUT,"| $^X $xlate $flavour ".shift || die "can't call $xlate: $!";
97 $FRAME=($FRAME+63)&~63;
109 $rp="r9"; # $rp is reassigned
113 # non-volatile registers
114 $nap_d="r14"; # interleaved ap and np in double format
116 $t0="r16"; # temporary registers
125 # PPC offers enough register bank capacity to unroll inner loops twice
149 $ba="f0"; $bb="f1"; $bc="f2"; $bd="f3";
150 $na="f4"; $nb="f5"; $nc="f6"; $nd="f7";
151 $dota="f8"; $dotb="f9";
152 $A0="f10"; $A1="f11"; $A2="f12"; $A3="f13";
153 $N0="f14"; $N1="f15"; $N2="f16"; $N3="f17";
154 $T0a="f18"; $T0b="f19";
155 $T1a="f20"; $T1b="f21";
156 $T2a="f22"; $T2b="f23";
157 $T3a="f24"; $T3b="f25";
159 # sp----------->+-------------------------------+
161 # +-------------------------------+
163 # +-------------------------------+
164 # | 10 saved gpr, r14-r23 |
167 # +12*size_t +-------------------------------+
168 # | 12 saved fpr, f14-f25 |
171 # +12*8 +-------------------------------+
172 # | padding to 64 byte boundary |
174 # +X +-------------------------------+
175 # | 16 gpr<->fpr transfer zone |
178 # +16*8 +-------------------------------+
179 # | __int64 tmp[-1] |
180 # +-------------------------------+
181 # | __int64 tmp[num] |
185 # +(num+1)*8 +-------------------------------+
186 # | padding to 64 byte boundary |
188 # +X +-------------------------------+
189 # | double nap_d[4*num] |
193 # +-------------------------------+
202 cmpwi $num,`3*8/$SIZE_T`
203 mr $rp,r3 ; $rp is reassigned
204 li r3,0 ; possible "not handled" return code
206 andi. r0,$num,`16/$SIZE_T-1` ; $num has to be "even"
209 slwi $num,$num,`log($SIZE_T)/log(2)` ; num*=sizeof(BN_LONG)
211 slwi $tp,$num,2 ; place for {an}p_{lh}[num], i.e. 4*num
212 add $tp,$tp,$num ; place for tp[num+1]
213 addi $tp,$tp,`$FRAME+$TRANSFER+8+64+$RZONE`
214 subf $tp,$tp,$sp ; $sp-$tp
215 and $tp,$tp,$i ; minimize TLB usage
216 subf $tp,$sp,$tp ; $tp-$sp
217 $STUX $sp,$sp,$tp ; alloca
219 $PUSH r14,`2*$SIZE_T`($sp)
220 $PUSH r15,`3*$SIZE_T`($sp)
221 $PUSH r16,`4*$SIZE_T`($sp)
222 $PUSH r17,`5*$SIZE_T`($sp)
223 $PUSH r18,`6*$SIZE_T`($sp)
224 $PUSH r19,`7*$SIZE_T`($sp)
225 $PUSH r20,`8*$SIZE_T`($sp)
226 $PUSH r21,`9*$SIZE_T`($sp)
227 $PUSH r22,`10*$SIZE_T`($sp)
228 $PUSH r23,`11*$SIZE_T`($sp)
229 stfd f14,`12*$SIZE_T+0`($sp)
230 stfd f15,`12*$SIZE_T+8`($sp)
231 stfd f16,`12*$SIZE_T+16`($sp)
232 stfd f17,`12*$SIZE_T+24`($sp)
233 stfd f18,`12*$SIZE_T+32`($sp)
234 stfd f19,`12*$SIZE_T+40`($sp)
235 stfd f20,`12*$SIZE_T+48`($sp)
236 stfd f21,`12*$SIZE_T+56`($sp)
237 stfd f22,`12*$SIZE_T+64`($sp)
238 stfd f23,`12*$SIZE_T+72`($sp)
239 stfd f24,`12*$SIZE_T+80`($sp)
240 stfd f25,`12*$SIZE_T+88`($sp)
242 $code.=<<___ if ($SIZE_T==8);
243 ld $a0,0($ap) ; pull ap[0] value
244 ld $n0,0($n0) ; pull n0[0] value
245 ld $t3,0($bp) ; bp[0]
247 $code.=<<___ if ($SIZE_T==4);
249 lwz $a0,0($ap) ; pull ap[0,1] value
251 lwz $n0,0($t1) ; pull n0[0,1] value
253 lwz $t3,0($bp) ; bp[0,1]
260 addi $tp,$sp,`$FRAME+$TRANSFER+8+64`
263 and $nap_d,$nap_d,$i ; align to 64 bytes
265 mulld $t7,$a0,$t3 ; ap[0]*bp[0]
266 ; nap_d is off by 1, because it's used with stfdu/lfdu
267 addi $nap_d,$nap_d,-8
268 srwi $j,$num,`3+1` ; counter register, num/2
269 mulld $t7,$t7,$n0 ; tp[0]*n0
271 addi $tp,$sp,`$FRAME+$TRANSFER-8`
275 ; transfer bp[0] to FPU as 4x16-bit values
280 std $t0,`$FRAME+0`($sp)
281 std $t1,`$FRAME+8`($sp)
282 std $t2,`$FRAME+16`($sp)
283 std $t3,`$FRAME+24`($sp)
284 ; transfer (ap[0]*bp[0])*n0 to FPU as 4x16-bit values
289 std $t4,`$FRAME+32`($sp)
290 std $t5,`$FRAME+40`($sp)
291 std $t6,`$FRAME+48`($sp)
292 std $t7,`$FRAME+56`($sp)
294 $code.=<<___ if ($SIZE_T==8);
295 lwz $t0,4($ap) ; load a[j] as 32-bit word pair
297 lwz $t2,12($ap) ; load a[j+1] as 32-bit word pair
299 lwz $t4,4($np) ; load n[j] as 32-bit word pair
301 lwz $t6,12($np) ; load n[j+1] as 32-bit word pair
304 $code.=<<___ if ($SIZE_T==4);
305 lwz $t0,0($ap) ; load a[j..j+3] as 32-bit word pairs
309 lwz $t4,0($np) ; load n[j..j+3] as 32-bit word pairs
315 lfd $ba,`$FRAME+0`($sp)
316 lfd $bb,`$FRAME+8`($sp)
317 lfd $bc,`$FRAME+16`($sp)
318 lfd $bd,`$FRAME+24`($sp)
319 lfd $na,`$FRAME+32`($sp)
320 lfd $nb,`$FRAME+40`($sp)
321 lfd $nc,`$FRAME+48`($sp)
322 lfd $nd,`$FRAME+56`($sp)
323 std $t0,`$FRAME+64`($sp)
324 std $t1,`$FRAME+72`($sp)
325 std $t2,`$FRAME+80`($sp)
326 std $t3,`$FRAME+88`($sp)
327 std $t4,`$FRAME+96`($sp)
328 std $t5,`$FRAME+104`($sp)
329 std $t6,`$FRAME+112`($sp)
330 std $t7,`$FRAME+120`($sp)
340 lfd $A0,`$FRAME+64`($sp)
341 lfd $A1,`$FRAME+72`($sp)
342 lfd $A2,`$FRAME+80`($sp)
343 lfd $A3,`$FRAME+88`($sp)
344 lfd $N0,`$FRAME+96`($sp)
345 lfd $N1,`$FRAME+104`($sp)
346 lfd $N2,`$FRAME+112`($sp)
347 lfd $N3,`$FRAME+120`($sp)
361 stfd $A0,8($nap_d) ; save a[j] in double format
365 stfd $A2,24($nap_d) ; save a[j+1] in double format
369 stfd $N0,40($nap_d) ; save n[j] in double format
373 stfd $N2,56($nap_d) ; save n[j+1] in double format
376 fmadd $T1a,$A0,$bc,$T1a
377 fmadd $T1b,$A0,$bd,$T1b
378 fmadd $T2a,$A1,$bc,$T2a
379 fmadd $T2b,$A1,$bd,$T2b
380 fmadd $T3a,$A2,$bc,$T3a
381 fmadd $T3b,$A2,$bd,$T3b
385 fmadd $T1a,$N1,$na,$T1a
386 fmadd $T1b,$N1,$nb,$T1b
387 fmadd $T2a,$N2,$na,$T2a
388 fmadd $T2b,$N2,$nb,$T2b
389 fmadd $T3a,$N3,$na,$T3a
390 fmadd $T3b,$N3,$nb,$T3b
391 fmadd $T0a,$N0,$na,$T0a
392 fmadd $T0b,$N0,$nb,$T0b
394 fmadd $T1a,$N0,$nc,$T1a
395 fmadd $T1b,$N0,$nd,$T1b
396 fmadd $T2a,$N1,$nc,$T2a
397 fmadd $T2b,$N1,$nd,$T2b
398 fmadd $T3a,$N2,$nc,$T3a
399 fmadd $T3b,$N2,$nd,$T3b
400 fmadd $dota,$N3,$nc,$dota
401 fmadd $dotb,$N3,$nd,$dotb
412 stfd $T0a,`$FRAME+0`($sp)
413 stfd $T0b,`$FRAME+8`($sp)
414 stfd $T1a,`$FRAME+16`($sp)
415 stfd $T1b,`$FRAME+24`($sp)
416 stfd $T2a,`$FRAME+32`($sp)
417 stfd $T2b,`$FRAME+40`($sp)
418 stfd $T3a,`$FRAME+48`($sp)
419 stfd $T3b,`$FRAME+56`($sp)
424 $code.=<<___ if ($SIZE_T==8);
425 lwz $t0,4($ap) ; load a[j] as 32-bit word pair
427 lwz $t2,12($ap) ; load a[j+1] as 32-bit word pair
429 lwz $t4,4($np) ; load n[j] as 32-bit word pair
431 lwz $t6,12($np) ; load n[j+1] as 32-bit word pair
434 $code.=<<___ if ($SIZE_T==4);
435 lwz $t0,0($ap) ; load a[j..j+3] as 32-bit word pairs
439 lwz $t4,0($np) ; load n[j..j+3] as 32-bit word pairs
445 std $t0,`$FRAME+64`($sp)
446 std $t1,`$FRAME+72`($sp)
447 std $t2,`$FRAME+80`($sp)
448 std $t3,`$FRAME+88`($sp)
449 std $t4,`$FRAME+96`($sp)
450 std $t5,`$FRAME+104`($sp)
451 std $t6,`$FRAME+112`($sp)
452 std $t7,`$FRAME+120`($sp)
453 ld $t0,`$FRAME+0`($sp)
454 ld $t1,`$FRAME+8`($sp)
455 ld $t2,`$FRAME+16`($sp)
456 ld $t3,`$FRAME+24`($sp)
457 ld $t4,`$FRAME+32`($sp)
458 ld $t5,`$FRAME+40`($sp)
459 ld $t6,`$FRAME+48`($sp)
460 ld $t7,`$FRAME+56`($sp)
461 lfd $A0,`$FRAME+64`($sp)
462 lfd $A1,`$FRAME+72`($sp)
463 lfd $A2,`$FRAME+80`($sp)
464 lfd $A3,`$FRAME+88`($sp)
465 lfd $N0,`$FRAME+96`($sp)
466 lfd $N1,`$FRAME+104`($sp)
467 lfd $N2,`$FRAME+112`($sp)
468 lfd $N3,`$FRAME+120`($sp)
484 stfd $A0,8($nap_d) ; save a[j] in double format
488 fmadd $T0a,$A0,$ba,$dota
489 fmadd $T0b,$A0,$bb,$dotb
490 stfd $A2,24($nap_d) ; save a[j+1] in double format
493 fmadd $T1a,$A0,$bc,$T1a
494 fmadd $T1b,$A0,$bd,$T1b
495 fmadd $T2a,$A1,$bc,$T2a
496 fmadd $T2b,$A1,$bd,$T2b
497 stfd $N0,40($nap_d) ; save n[j] in double format
499 fmadd $T3a,$A2,$bc,$T3a
500 fmadd $T3b,$A2,$bd,$T3b
501 add $t0,$t0,$carry ; can not overflow
504 stfd $N2,56($nap_d) ; save n[j+1] in double format
510 fmadd $T1a,$N1,$na,$T1a
511 fmadd $T1b,$N1,$nb,$T1b
513 fmadd $T2a,$N2,$na,$T2a
514 fmadd $T2b,$N2,$nb,$T2b
516 fmadd $T3a,$N3,$na,$T3a
517 fmadd $T3b,$N3,$nb,$T3b
519 fmadd $T0a,$N0,$na,$T0a
520 fmadd $T0b,$N0,$nb,$T0b
525 fmadd $T1a,$N0,$nc,$T1a
526 fmadd $T1b,$N0,$nd,$T1b
527 insrdi $t0,$t3,16,0 ; 0..63 bits
528 fmadd $T2a,$N1,$nc,$T2a
529 fmadd $T2b,$N1,$nd,$T2b
531 fmadd $T3a,$N2,$nc,$T3a
532 fmadd $T3b,$N2,$nd,$T3b
534 fmadd $dota,$N3,$nc,$dota
535 fmadd $dotb,$N3,$nd,$dotb
552 insrdi $t4,$t7,16,0 ; 64..127 bits
553 srdi $carry,$t7,16 ; upper 33 bits
555 stfd $T0a,`$FRAME+0`($sp)
556 stfd $T0b,`$FRAME+8`($sp)
557 stfd $T1a,`$FRAME+16`($sp)
558 stfd $T1b,`$FRAME+24`($sp)
559 stfd $T2a,`$FRAME+32`($sp)
560 stfd $T2b,`$FRAME+40`($sp)
561 stfd $T3a,`$FRAME+48`($sp)
562 stfd $T3b,`$FRAME+56`($sp)
563 std $t0,8($tp) ; tp[j-1]
564 stdu $t4,16($tp) ; tp[j]
570 ld $t0,`$FRAME+0`($sp)
571 ld $t1,`$FRAME+8`($sp)
572 ld $t2,`$FRAME+16`($sp)
573 ld $t3,`$FRAME+24`($sp)
574 ld $t4,`$FRAME+32`($sp)
575 ld $t5,`$FRAME+40`($sp)
576 ld $t6,`$FRAME+48`($sp)
577 ld $t7,`$FRAME+56`($sp)
578 stfd $dota,`$FRAME+64`($sp)
579 stfd $dotb,`$FRAME+72`($sp)
581 add $t0,$t0,$carry ; can not overflow
591 insrdi $t0,$t3,16,0 ; 0..63 bits
601 insrdi $t4,$t7,16,0 ; 64..127 bits
602 srdi $carry,$t7,16 ; upper 33 bits
603 ld $t6,`$FRAME+64`($sp)
604 ld $t7,`$FRAME+72`($sp)
606 std $t0,8($tp) ; tp[j-1]
607 stdu $t4,16($tp) ; tp[j]
609 add $t6,$t6,$carry ; can not overflow
614 std $t6,8($tp) ; tp[num-1]
617 subf $nap_d,$t7,$nap_d ; rewind pointer
623 $code.=<<___ if ($SIZE_T==8);
624 ldx $t3,$bp,$i ; bp[i]
626 $code.=<<___ if ($SIZE_T==4);
628 lwz $t3,0($t0) ; bp[i,i+1]
633 ld $t6,`$FRAME+$TRANSFER+8`($sp) ; tp[0]
634 mulld $t7,$a0,$t3 ; ap[0]*bp[i]
636 addi $tp,$sp,`$FRAME+$TRANSFER`
637 add $t7,$t7,$t6 ; ap[0]*bp[i]+tp[0]
639 mulld $t7,$t7,$n0 ; tp[0]*n0
642 ; transfer bp[i] to FPU as 4x16-bit values
647 std $t0,`$FRAME+0`($sp)
648 std $t1,`$FRAME+8`($sp)
649 std $t2,`$FRAME+16`($sp)
650 std $t3,`$FRAME+24`($sp)
651 ; transfer (ap[0]*bp[i]+tp[0])*n0 to FPU as 4x16-bit values
656 std $t4,`$FRAME+32`($sp)
657 std $t5,`$FRAME+40`($sp)
658 std $t6,`$FRAME+48`($sp)
659 std $t7,`$FRAME+56`($sp)
661 lfd $A0,8($nap_d) ; load a[j] in double format
663 lfd $A2,24($nap_d) ; load a[j+1] in double format
665 lfd $N0,40($nap_d) ; load n[j] in double format
667 lfd $N2,56($nap_d) ; load n[j+1] in double format
670 lfd $ba,`$FRAME+0`($sp)
671 lfd $bb,`$FRAME+8`($sp)
672 lfd $bc,`$FRAME+16`($sp)
673 lfd $bd,`$FRAME+24`($sp)
674 lfd $na,`$FRAME+32`($sp)
675 lfd $nb,`$FRAME+40`($sp)
676 lfd $nc,`$FRAME+48`($sp)
677 lfd $nd,`$FRAME+56`($sp)
697 fmadd $T1a,$A0,$bc,$T1a
698 fmadd $T1b,$A0,$bd,$T1b
699 fmadd $T2a,$A1,$bc,$T2a
700 fmadd $T2b,$A1,$bd,$T2b
701 fmadd $T3a,$A2,$bc,$T3a
702 fmadd $T3b,$A2,$bd,$T3b
706 fmadd $T1a,$N1,$na,$T1a
707 fmadd $T1b,$N1,$nb,$T1b
708 lfd $A0,8($nap_d) ; load a[j] in double format
710 fmadd $T2a,$N2,$na,$T2a
711 fmadd $T2b,$N2,$nb,$T2b
712 lfd $A2,24($nap_d) ; load a[j+1] in double format
714 fmadd $T3a,$N3,$na,$T3a
715 fmadd $T3b,$N3,$nb,$T3b
716 fmadd $T0a,$N0,$na,$T0a
717 fmadd $T0b,$N0,$nb,$T0b
719 fmadd $T1a,$N0,$nc,$T1a
720 fmadd $T1b,$N0,$nd,$T1b
721 fmadd $T2a,$N1,$nc,$T2a
722 fmadd $T2b,$N1,$nd,$T2b
723 fmadd $T3a,$N2,$nc,$T3a
724 fmadd $T3b,$N2,$nd,$T3b
725 fmadd $dota,$N3,$nc,$dota
726 fmadd $dotb,$N3,$nd,$dotb
737 stfd $T0a,`$FRAME+0`($sp)
738 stfd $T0b,`$FRAME+8`($sp)
739 stfd $T1a,`$FRAME+16`($sp)
740 stfd $T1b,`$FRAME+24`($sp)
741 stfd $T2a,`$FRAME+32`($sp)
742 stfd $T2b,`$FRAME+40`($sp)
743 stfd $T3a,`$FRAME+48`($sp)
744 stfd $T3b,`$FRAME+56`($sp)
752 lfd $N0,40($nap_d) ; load n[j] in double format
756 fmadd $T0a,$A0,$ba,$dota
757 fmadd $T0b,$A0,$bb,$dotb
758 lfd $N2,56($nap_d) ; load n[j+1] in double format
761 fmadd $T1a,$A0,$bc,$T1a
762 fmadd $T1b,$A0,$bd,$T1b
763 fmadd $T2a,$A1,$bc,$T2a
764 fmadd $T2b,$A1,$bd,$T2b
765 lfd $A0,8($nap_d) ; load a[j] in double format
767 fmadd $T3a,$A2,$bc,$T3a
768 fmadd $T3b,$A2,$bd,$T3b
771 lfd $A2,24($nap_d) ; load a[j+1] in double format
774 fmadd $T1a,$N1,$na,$T1a
775 fmadd $T1b,$N1,$nb,$T1b
776 ld $t0,`$FRAME+0`($sp)
777 ld $t1,`$FRAME+8`($sp)
778 fmadd $T2a,$N2,$na,$T2a
779 fmadd $T2b,$N2,$nb,$T2b
780 ld $t2,`$FRAME+16`($sp)
781 ld $t3,`$FRAME+24`($sp)
782 fmadd $T3a,$N3,$na,$T3a
783 fmadd $T3b,$N3,$nb,$T3b
784 add $t0,$t0,$carry ; can not overflow
785 ld $t4,`$FRAME+32`($sp)
786 ld $t5,`$FRAME+40`($sp)
787 fmadd $T0a,$N0,$na,$T0a
788 fmadd $T0b,$N0,$nb,$T0b
792 ld $t6,`$FRAME+48`($sp)
793 ld $t7,`$FRAME+56`($sp)
795 fmadd $T1a,$N0,$nc,$T1a
796 fmadd $T1b,$N0,$nd,$T1b
798 ld $t1,8($tp) ; tp[j]
799 fmadd $T2a,$N1,$nc,$T2a
800 fmadd $T2b,$N1,$nd,$T2b
802 fmadd $T3a,$N2,$nc,$T3a
803 fmadd $T3b,$N2,$nd,$T3b
806 fmadd $dota,$N3,$nc,$dota
807 fmadd $dotb,$N3,$nd,$dotb
809 ldu $t2,16($tp) ; tp[j+1]
811 insrdi $t0,$t3,16,0 ; 0..63 bits
830 stfd $T0a,`$FRAME+0`($sp)
831 stfd $T0b,`$FRAME+8`($sp)
835 $code.=<<___ if ($SIZE_T==4); # adjust XER[CA]
841 stfd $T1a,`$FRAME+16`($sp)
842 stfd $T1b,`$FRAME+24`($sp)
843 insrdi $t4,$t7,16,0 ; 64..127 bits
844 srdi $carry,$t7,16 ; upper 33 bits
845 stfd $T2a,`$FRAME+32`($sp)
846 stfd $T2b,`$FRAME+40`($sp)
849 $code.=<<___ if ($SIZE_T==4); # adjust XER[CA]
855 stfd $T3a,`$FRAME+48`($sp)
856 stfd $T3b,`$FRAME+56`($sp)
858 std $t3,-16($tp) ; tp[j-1]
859 std $t5,-8($tp) ; tp[j]
864 ld $t0,`$FRAME+0`($sp)
865 ld $t1,`$FRAME+8`($sp)
866 ld $t2,`$FRAME+16`($sp)
867 ld $t3,`$FRAME+24`($sp)
868 ld $t4,`$FRAME+32`($sp)
869 ld $t5,`$FRAME+40`($sp)
870 ld $t6,`$FRAME+48`($sp)
871 ld $t7,`$FRAME+56`($sp)
872 stfd $dota,`$FRAME+64`($sp)
873 stfd $dotb,`$FRAME+72`($sp)
875 add $t0,$t0,$carry ; can not overflow
881 ld $t1,8($tp) ; tp[j]
885 ldu $t2,16($tp) ; tp[j+1]
887 insrdi $t0,$t3,16,0 ; 0..63 bits
897 insrdi $t4,$t7,16,0 ; 64..127 bits
898 srdi $carry,$t7,16 ; upper 33 bits
899 ld $t6,`$FRAME+64`($sp)
900 ld $t7,`$FRAME+72`($sp)
904 $code.=<<___ if ($SIZE_T==4); # adjust XER[CA]
912 $code.=<<___ if ($SIZE_T==4); # adjust XER[CA]
920 std $t3,-16($tp) ; tp[j-1]
921 std $t5,-8($tp) ; tp[j]
923 add $carry,$carry,$ovf ; comsume upmost overflow
924 add $t6,$t6,$carry ; can not overflow
929 std $t6,0($tp) ; tp[num-1]
933 subf $nap_d,$t7,$nap_d ; rewind pointer
938 $code.=<<___ if ($SIZE_T==8);
939 subf $np,$num,$np ; rewind np
940 addi $j,$j,1 ; restore counter
941 subfc $i,$i,$i ; j=0 and "clear" XER[CA]
942 addi $tp,$sp,`$FRAME+$TRANSFER+8`
943 addi $t4,$sp,`$FRAME+$TRANSFER+16`
953 subfe $t0,$t1,$t0 ; tp[j]-np[j]
954 subfe $t2,$t3,$t2 ; tp[j+1]-np[j+1]
961 subfe $ovf,$i,$ovf ; handle upmost overflow bit
964 or $ap,$ap,$np ; ap=borrow?tp:rp
969 Lcopy: ; copy or in-place refresh
972 std $i,8($nap_d) ; zap nap_d
982 stdx $i,$tp,$i ; zap tp at once
987 $code.=<<___ if ($SIZE_T==4);
988 subf $np,$num,$np ; rewind np
989 addi $j,$j,1 ; restore counter
990 subfc $i,$i,$i ; j=0 and "clear" XER[CA]
991 addi $tp,$sp,`$FRAME+$TRANSFER`
994 addi $ap,$sp,`$FRAME+$TRANSFER+4`
998 Lsub: ld $t0,8($tp) ; load tp[j..j+3] in 64-bit word order
1000 lwz $t4,4($np) ; load np[j..j+3] in 32-bit word order
1006 subfe $t4,$t4,$t0 ; tp[j]-np[j]
1007 stw $t0,4($ap) ; save tp[j..j+3] in 32-bit word order
1008 subfe $t5,$t5,$t1 ; tp[j+1]-np[j+1]
1010 subfe $t6,$t6,$t2 ; tp[j+2]-np[j+2]
1012 subfe $t7,$t7,$t3 ; tp[j+3]-np[j+3]
1021 subfe $ovf,$i,$ovf ; handle upmost overflow bit
1022 addi $tp,$sp,`$FRAME+$TRANSFER+4`
1023 subf $rp,$num,$rp ; rewind rp
1026 or $ap,$ap,$np ; ap=borrow?tp:rp
1027 addi $tp,$sp,`$FRAME+$TRANSFER`
1031 Lcopy: ; copy or in-place refresh
1036 std $i,8($nap_d) ; zap nap_d
1048 std $i,8($tp) ; zap tp at once
1054 $POP r14,`2*$SIZE_T`($sp)
1055 $POP r15,`3*$SIZE_T`($sp)
1056 $POP r16,`4*$SIZE_T`($sp)
1057 $POP r17,`5*$SIZE_T`($sp)
1058 $POP r18,`6*$SIZE_T`($sp)
1059 $POP r19,`7*$SIZE_T`($sp)
1060 $POP r20,`8*$SIZE_T`($sp)
1061 $POP r21,`9*$SIZE_T`($sp)
1062 $POP r22,`10*$SIZE_T`($sp)
1063 $POP r23,`11*$SIZE_T`($sp)
1064 lfd f14,`12*$SIZE_T+0`($sp)
1065 lfd f15,`12*$SIZE_T+8`($sp)
1066 lfd f16,`12*$SIZE_T+16`($sp)
1067 lfd f17,`12*$SIZE_T+24`($sp)
1068 lfd f18,`12*$SIZE_T+32`($sp)
1069 lfd f19,`12*$SIZE_T+40`($sp)
1070 lfd f20,`12*$SIZE_T+48`($sp)
1071 lfd f21,`12*$SIZE_T+56`($sp)
1072 lfd f22,`12*$SIZE_T+64`($sp)
1073 lfd f23,`12*$SIZE_T+72`($sp)
1074 lfd f24,`12*$SIZE_T+80`($sp)
1075 lfd f25,`12*$SIZE_T+88`($sp)
1077 li r3,1 ; signal "handled"
1080 .asciz "Montgomery Multiplication for PPC64, CRYPTOGAMS by <appro\@fy.chalmers.se>"
1083 $code =~ s/\`([^\`]*)\`/eval $1/gem;