1 ;;====================================================================
2 ;; Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
5 ;; Rights for redistribution and usage in source and binary forms are
6 ;; granted according to the OpenSSL license. Warranty of any kind is
8 ;;====================================================================
9 ;; Compiler-generated multiply-n-add SPLOOP runs at 12*n cycles, n
10 ;; being the number of 32-bit words, addition - 8*n. Corresponding 4x
11 ;; unrolled SPLOOP-free loops - at ~8*n and ~5*n. Below assembler
12 ;; SPLOOPs spin at ... 2*n cycles [plus epilogue].
13 ;;====================================================================
16 .if .ASSEMBLER_VERSION<7000000
20 .asg bn_mul_add_words,_bn_mul_add_words
21 .asg bn_mul_words,_bn_mul_words
22 .asg bn_sqr_words,_bn_sqr_words
23 .asg bn_add_words,_bn_add_words
24 .asg bn_sub_words,_bn_sub_words
25 .asg bn_div_words,_bn_div_words
26 .asg bn_sqr_comba8,_bn_sqr_comba8
27 .asg bn_mul_comba8,_bn_mul_comba8
28 .asg bn_sqr_comba4,_bn_sqr_comba4
29 .asg bn_mul_comba4,_bn_mul_comba4
44 .global _bn_mul_add_words
51 [B0] ZERO A19 ; high part of accumulator
57 ;;====================================================================
58 LDW *ARG1++,B7 ; ap[i]
60 LDW *ARG0++,A7 ; rp[i]
62 NOP 3 ; [2,0] in epilogue
64 ADDU A19,A21:A20,A19:A18
66 SPKERNEL 2,1 ; leave slot for "return value"
67 || STW A18,*A2++ ; rp[i]
69 ;;====================================================================
71 MV A19,RET ; return value
81 [B0] ZERO A19 ; high part of accumulator
85 ;;====================================================================
86 LDW *ARG1++,A7 ; ap[i]
88 MPY32U A7,ARG3,A17:A16
89 NOP 4 ; [2,0] in epiloque
92 SPKERNEL 2,1 ; leave slot for "return value"
93 || STW A18,*ARG0++ ; rp[i]
95 ;;====================================================================
97 MV A19,RET ; return value
100 .global _bn_sqr_words
108 || [B0] ADD 4,ARG0,ARG0
112 ;;====================================================================
113 LDW *ARG1++,B7 ; ap[i]
116 NOP 3 ; [2,0] in epilogue
117 STW B0,*B2++(8) ; rp[2*i]
119 SPKERNEL 2,0 ; fully overlap BNOP RA,5
120 || STW A1,*ARG0++(8) ; rp[2*i+1]
121 ;;====================================================================
125 .global _bn_add_words
132 [B0] ZERO A1 ; carry flag
137 ;;====================================================================
138 LDW *ARG2++,A7 ; bp[i]
139 || LDW *ARG1++,B7 ; ap[i]
143 SPKERNEL 0,0 ; fully overlap BNOP RA,5
144 || STW A0,*A3++ ; write result
145 || MV A1,RET ; keep carry flag in RET
146 ;;====================================================================
150 .global _bn_sub_words
157 [B0] ZERO A2 ; borrow flag
162 ;;====================================================================
163 LDW *ARG2++,A7 ; bp[i]
164 || LDW *ARG1++,B7 ; ap[i]
167 [A2] SUB A1:A0,1,A1:A0
168 SPKERNEL 0,1 ; leave slot for "return borrow flag"
169 || STW A0,*A3++ ; write result
170 || AND 1,A1,A2 ; pass on borrow flag
171 ;;====================================================================
173 AND 1,A1,RET ; return borrow flag
176 .global _bn_div_words
179 LMBD 1,A6,A0 ; leading zero bits in dv
180 LMBD 1,A4,A1 ; leading zero bits in hi
185 ||[ A2] MVK -1,A4 ; return overflow
186 ||[!A2] MV A4,A3 ; reassign hi
187 [!A2] MV B4,A4 ; reassign lo, will be quotient
189 [!A2] SHL A6,A0,A6 ; normalize dv
192 [!A2] CMPLTU A3,A6,A1 ; hi<dv?
193 ||[!A2] SHL A4,1,A5:A4 ; lo<<1
194 [!A1] SUB A3,A6,A3 ; hi-=dv
196 [!A2] SHRU A3,31,A1 ; upper bit
197 ||[!A2] ADDAH A5,A3,A3 ; hi<<1|lo>>31
200 [!A1] CMPLTU A3,A6,A1 ; hi<dv?
202 || SHL A4,1,A5:A4 ; lo<<1
203 [!A1] SUB A3,A6,A3 ; hi-=dv
204 ||[!A1] OR 1,A4,A4 ; quotient
205 SHRU A3,31,A1 ; upper bit
206 || ADDAH A5,A3,A3 ; hi<<1|lo>>31
212 ;;====================================================================
213 ;; Not really Comba algorithm, just straightforward NxM... Dedicated
214 ;; fully unrolled real Comba implementations are asymptotically 2x
215 ;; faster, but naturally larger undertaking. Purpose of this exercise
216 ;; was rather to learn to master nested SPLOOPs...
217 ;;====================================================================
218 .global _bn_sqr_comba8
219 .global _bn_mul_comba8
225 || MVK 8,A0 ; M, outer loop counter
226 || MV ARG1,A5 ; copy ap
227 || MV ARG0,B4 ; copy rp
228 || ZERO B19 ; high part of accumulator
230 || SUB B0,2,B1 ; N-2, initial ILC
231 || SUB B0,1,B2 ; const B2=N-1
232 || LDW *A5++,B6 ; ap[0]
233 || MV A0,A3 ; const A3=M
234 sploopNxM?: ; for best performance arrange M<=N
235 [A0] SPLOOPD 2 ; 2*n+10
239 || LDW *A5++,A9 ; pre-fetch ap[1]
242 ;;====================================================================
243 ;; SPLOOP from bn_mul_add_words, but with flipped A<>B register files.
244 ;; This is because of Advisory 15 from TI publication SPRZ247I.
245 LDW *ARG2++,A7 ; bp[i]
247 [A1] LDW *B5++,B7 ; rp[i]
251 ADDU B19,B21:B20,B19:B18
254 || STW B18,*B4++ ; rp[i]
256 ;;====================================================================
257 outer?: ; m*2*(n+1)+10
258 SUBAW ARG2,A3,ARG2 ; rewind bp to bp[0]
260 || CMPGT A0,1,A2 ; done pre-fetching ap[i+1]?
261 MVD A9,B6 ; move through .M unit(*)
262 [A2] LDW *A5++,A9 ; pre-fetch ap[i+1]
263 SUBAW B5,B2,B5 ; rewind rp to rp[1]
265 [A0] BNOP.S1 outer?,4
266 || [A0] SUB.L A0,1,A0
267 STW B19,*B4--[B2] ; rewind rp tp rp[1]
268 || ZERO.S B19 ; high part of accumulator
272 ;; (*) It should be noted that B6 is used as input to MPY32U in
273 ;; chronologically next cycle in *preceding* SPLOOP iteration.
274 ;; Normally such arrangement would require DINT, but at this
275 ;; point SPLOOP is draining and interrupts are disabled
278 .global _bn_sqr_comba4
279 .global _bn_mul_comba4
286 ;; Above mentioned m*2*(n+1)+10 does not apply in n=m=4 case,
287 ;; because of read-after-write penalties, it's rather
288 ;; n*2*(n+3)+10, or 66 cycles [plus various overheads]...
290 || MVK 4,A0 ; M, outer loop counter
291 || MV ARG1,A5 ; copy ap
292 || MV ARG0,B4 ; copy rp
293 || ZERO B19 ; high part of accumulator
295 || SUB B0,2,B1 ; first ILC
296 || SUB B0,1,B2 ; const B2=N-1
297 || LDW *A5++,B6 ; ap[0]
298 || MV A0,A3 ; const A3=M
300 ;; This alternative is an exercise in fully unrolled Comba
301 ;; algorithm implementation that operates at n*(n+1)+12, or
302 ;; as little as 32 cycles...
303 LDW *ARG1[0],B16 ; a[0]
304 || LDW *ARG2[0],A16 ; b[0]
305 LDW *ARG1[1],B17 ; a[1]
306 || LDW *ARG2[1],A17 ; b[1]
307 LDW *ARG1[2],B18 ; a[2]
308 || LDW *ARG2[2],A18 ; b[2]
309 LDW *ARG1[3],B19 ; a[3]
310 || LDW *ARG2[3],A19 ; b[3]
312 MPY32U A16,B16,A1:A0 ; a[0]*b[0]
313 MPY32U A17,B16,A23:A22 ; a[0]*b[1]
314 MPY32U A16,B17,A25:A24 ; a[1]*b[0]
315 MPY32U A16,B18,A27:A26 ; a[2]*b[0]
317 || MPY32U A17,B17,A29:A28 ; a[1]*b[1]
318 MPY32U A18,B16,A31:A30 ; a[0]*b[2]
321 || MPY32U A19,B16,A21:A20 ; a[3]*b[0]
322 || ADDU A24,A1:A0,A1:A0
325 || MPY32U A18,B17,A23:A22 ; a[2]*b[1]
328 || MPY32U A17,B18,A25:A24 ; a[1]*b[2]
329 || ADDU A28,A9:A8,A9:A8
331 || MPY32U A16,B19,A27:A26 ; a[0]*b[3]
332 || ADDU A30,A9:A8,A9:A8
334 || ADDU B0,A9:A8,A9:A8
338 || MPY32U A19,B17,A21:A20 ; a[3]*b[1]
339 || ADDU A22,A1:A0,A1:A0
341 || MPY32U A18,B18,A23:A22 ; a[2]*b[2]
342 || ADDU A24,A1:A0,A1:A0
344 || MPY32U A17,B19,A25:A24 ; a[1]*b[3]
345 || ADDU A26,A1:A0,A1:A0
347 || ADDU B8,A1:A0,A1:A0
349 || MPY32U A19,B18,A27:A26 ; a[3]*b[2]
352 || MPY32U A18,B19,A29:A28 ; a[2]*b[3]
353 || ADDU A22,A9:A8,A9:A8
355 || MPY32U A19,B19,A31:A30 ; a[3]*b[3]
356 || ADDU A24,A9:A8,A9:A8
358 || ADDU B0,A9:A8,A9:A8
362 || ADDU A28,A1:A0,A1:A0
365 || ADDU B8,A1:A0,A1:A0
369 ADDU B0,A9:A8,A9:A8 ; removed || to avoid cross-path stall below