2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2002 (440 port)
6 * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
8 * (C) Copyright 2003 (440GX port)
9 * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
11 * (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX)
12 * Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
13 * Work supported by Qtechnology (htpp://qtec.com)
15 * See file CREDITS for list of people who contributed to this
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 #include <asm/processor.h>
38 #include <asm/interrupt.h>
40 #include <ppc_asm.tmpl>
44 #define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
45 UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI) | \
46 UIC_MASK(VECNUM_UIC3CI) | UIC_MASK(VECNUM_UIC3NCI))
48 #define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
49 UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI))
51 #define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI))
58 DECLARE_GLOBAL_DATA_PTR;
64 /* Install the UIC1 handlers */
65 irq_install_handler(VECNUM_UIC1NCI, (void *)(void *)external_interrupt,
67 irq_install_handler(VECNUM_UIC1CI, (void *)(void *)external_interrupt,
71 irq_install_handler(VECNUM_UIC2NCI, (void *)(void *)external_interrupt,
73 irq_install_handler(VECNUM_UIC2CI, (void *)(void *)external_interrupt,
77 irq_install_handler(VECNUM_UIC3NCI, (void *)(void *)external_interrupt,
79 irq_install_handler(VECNUM_UIC3CI, (void *)(void *)external_interrupt,
85 /* Handler for UIC interrupt */
86 static void uic_interrupt(u32 uic_base, int vec_base)
93 * Read masked interrupt status register to determine interrupt source
95 uic_msr = get_dcr(uic_base + UIC_MSR);
99 while (msr_shift != 0) {
100 if (msr_shift & 0x80000000)
101 interrupt_run_handler(vec);
103 * Shift msr to next position and increment vector
111 * Handle external interrupts
113 void external_interrupt(struct pt_regs *regs)
118 * Read masked interrupt status register to determine interrupt source
120 uic_msr = mfdcr(uic0msr);
123 if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) ||
124 (UIC_MASK(VECNUM_UIC1NCI) & uic_msr))
125 uic_interrupt(UIC1_DCR_BASE, 32);
129 if ((UIC_MASK(VECNUM_UIC2CI) & uic_msr) ||
130 (UIC_MASK(VECNUM_UIC2NCI) & uic_msr))
131 uic_interrupt(UIC2_DCR_BASE, 64);
135 if ((UIC_MASK(VECNUM_UIC3CI) & uic_msr) ||
136 (UIC_MASK(VECNUM_UIC3NCI) & uic_msr))
137 uic_interrupt(UIC3_DCR_BASE, 96);
140 if (uic_msr & ~(UICB0_ALL))
141 uic_interrupt(UIC0_DCR_BASE, 0);
143 mtdcr(uic0sr, uic_msr);
148 void pic_irq_ack(unsigned int vec)
151 if ((vec >= 0) && (vec < 32))
152 mtdcr(uicsr, UIC_MASK(vec));
154 else if ((vec >= 32) && (vec < 64))
155 mtdcr(uic1sr, UIC_MASK(vec));
158 else if ((vec >= 64) && (vec < 96))
159 mtdcr(uic2sr, UIC_MASK(vec));
163 mtdcr(uic3sr, UIC_MASK(vec));
168 * Install and free a interrupt handler.
170 void pic_irq_enable(unsigned int vec)
173 if ((vec >= 0) && (vec < 32))
174 mtdcr(uicer, mfdcr(uicer) | UIC_MASK(vec));
176 else if ((vec >= 32) && (vec < 64))
177 mtdcr(uic1er, mfdcr(uic1er) | UIC_MASK(vec));
180 else if ((vec >= 64) && (vec < 96))
181 mtdcr(uic2er, mfdcr(uic2er) | UIC_MASK(vec));
185 mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec));
188 debug("Install interrupt for vector %d ==> %p\n", vec, handler);
191 void pic_irq_disable(unsigned int vec)
194 if ((vec >= 0) && (vec < 32))
195 mtdcr(uicer, mfdcr(uicer) & ~UIC_MASK(vec));
197 else if ((vec >= 32) && (vec < 64))
198 mtdcr(uic1er, mfdcr(uic1er) & ~UIC_MASK(vec));
201 else if ((vec >= 64) && (vec < 96))
202 mtdcr(uic2er, mfdcr(uic2er) & ~UIC_MASK(vec));
206 mtdcr(uic3er, mfdcr(uic3er) & ~UIC_MASK(vec));