2 * linux/arch/ppc/kernel/traps.c
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 * Modified by Cort Dougan (cort@cs.nmt.edu)
7 * and Paul Mackerras (paulus@cs.anu.edu.au)
10 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * This file handles the architecture-dependent parts of hardware exceptions
37 #include <asm/processor.h>
39 DECLARE_GLOBAL_DATA_PTR;
41 #if defined(CONFIG_CMD_KGDB)
42 int (*debugger_exception_handler)(struct pt_regs *) = 0;
45 /* Returns 0 if exception not found and fixup otherwise. */
46 extern unsigned long search_exception_table(unsigned long);
48 /* THIS NEEDS CHANGING to use the board info structure.
50 #define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
52 static __inline__ void set_tsr(unsigned long val)
54 #if defined(CONFIG_440)
55 asm volatile("mtspr 0x150, %0" : : "r" (val));
57 asm volatile("mttsr %0" : : "r" (val));
61 static __inline__ unsigned long get_esr(void)
65 #if defined(CONFIG_440)
66 asm volatile("mfspr %0, 0x03e" : "=r" (val) :);
68 asm volatile("mfesr %0" : "=r" (val) :);
73 #define ESR_MCI 0x80000000
74 #define ESR_PIL 0x08000000
75 #define ESR_PPR 0x04000000
76 #define ESR_PTR 0x02000000
77 #define ESR_DST 0x00800000
78 #define ESR_DIZ 0x00400000
79 #define ESR_U0F 0x00008000
81 #if defined(CONFIG_CMD_BEDBUG)
82 extern void do_bedbug_breakpoint(struct pt_regs *);
86 * Trap & Exception support
90 print_backtrace(unsigned long *sp)
95 printf("Call backtrace: ");
97 if ((uint)sp > END_OF_MEM)
105 sp = (unsigned long *)*sp;
110 void show_regs(struct pt_regs * regs)
114 printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DEAR: %08lX\n",
115 regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
116 printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
117 regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
118 regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
119 regs->msr&MSR_IR ? 1 : 0,
120 regs->msr&MSR_DR ? 1 : 0);
123 for (i = 0; i < 32; i++) {
125 printf("GPR%02d: ", i);
128 printf("%08lX ", regs->gpr[i]);
137 _exception(int signr, struct pt_regs *regs)
140 print_backtrace((unsigned long *)regs->gpr[1]);
145 MachineCheckException(struct pt_regs *regs)
147 unsigned long fixup, val;
148 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
154 if ((fixup = search_exception_table(regs->nip)) != 0) {
158 mtspr(SPRN_MCSR, val);
162 #if defined(CONFIG_CMD_KGDB)
163 if (debugger_exception_handler && (*debugger_exception_handler)(regs))
167 printf("Machine Check Exception.\n");
168 printf("Caused by (from msr): ");
169 printf("regs %p ", regs);
173 #if !defined(CONFIG_440) && !defined(CONFIG_405EX)
175 printf("Instruction");
176 mtspr(ESR, val & ~ESR_IMCP);
180 printf(" machine check.\n");
182 #elif defined(CONFIG_440) || defined(CONFIG_405EX)
184 printf("Instruction Synchronous Machine Check exception\n");
185 mtspr(SPRN_ESR, val & ~ESR_IMCP);
189 printf("Instruction Read PLB Error\n");
190 #if defined(CONFIG_440)
192 printf("Data Read PLB Error\n");
194 printf("Data Write PLB Error\n");
197 printf("Data PLB Error\n");
200 printf("TLB Parity Error\n");
202 /*flush_instruction_cache(); */
203 printf("I-Cache Parity Error\n");
206 printf("D-Cache Search Parity Error\n");
208 printf("D-Cache Flush Parity Error\n");
210 printf("Machine Check exception is imprecise\n");
213 mtspr(SPRN_MCSR, val);
215 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
216 mfsdram(DDR0_00, val) ;
217 printf("DDR0: DDR0_00 %p\n", val);
218 val = (val >> 16) & 0xff;
220 printf("DDR0: At least one interrupt active\n");
222 printf("DDR0: DRAM initialization complete.\n");
224 printf("DDR0: Multiple uncorrectable ECC events.\n");
228 printf("DDR0: Single uncorrectable ECC event.\n");
232 printf("DDR0: Multiple correctable ECC events.\n");
236 printf("DDR0: Single correctable ECC event.\n");
240 printf("Multiple accesses outside the defined"
241 " physical memory space detected\n");
243 printf("DDR0: Single access outside the defined"
244 " physical memory space detected.\n");
246 mfsdram(DDR0_01, val);
247 val = (val >> 8) & 0x7;
250 printf("DDR0: Write Out-of-Range command\n");
253 printf("DDR0: Read Out-of-Range command\n");
256 printf("DDR0: Masked write Out-of-Range command\n");
259 printf("DDR0: Wrap write Out-of-Range command\n");
262 printf("DDR0: Wrap read Out-of-Range command\n");
265 mfsdram(DDR0_01, value2);
266 printf("DDR0: No DDR0 error know 0x%x %p\n", val, value2);
268 mfsdram(DDR0_23, val);
269 if (((val >> 16) & 0xff) && corr_ecc)
270 printf("DDR0: Syndrome for correctable ECC event 0x%x\n",
272 mfsdram(DDR0_23, val);
273 if (((val >> 8) & 0xff) && uncorr_ecc)
274 printf("DDR0: Syndrome for uncorrectable ECC event 0x%x\n",
276 mfsdram(DDR0_33, val);
278 printf("DDR0: Address of command that caused an "
279 "Out-of-Range interrupt %p\n", val);
280 mfsdram(DDR0_34, val);
281 if (val && uncorr_ecc)
282 printf("DDR0: Address of uncorrectable ECC event %p\n", val);
283 mfsdram(DDR0_35, val);
284 if (val && uncorr_ecc)
285 printf("DDR0: Address of uncorrectable ECC event %p\n", val);
286 mfsdram(DDR0_36, val);
287 if (val && uncorr_ecc)
288 printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val);
289 mfsdram(DDR0_37, val);
290 if (val && uncorr_ecc)
291 printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val);
292 mfsdram(DDR0_38, val);
294 printf("DDR0: Address of correctable ECC event %p\n", val);
295 mfsdram(DDR0_39, val);
297 printf("DDR0: Address of correctable ECC event %p\n", val);
298 mfsdram(DDR0_40, val);
300 printf("DDR0: Data of correctable ECC event 0x%08x\n", val);
301 mfsdram(DDR0_41, val);
303 printf("DDR0: Data of correctable ECC event 0x%08x\n", val);
304 #endif /* CONFIG_440EPX */
305 #endif /* CONFIG_440 */
307 print_backtrace((unsigned long *)regs->gpr[1]);
308 panic("machine check");
312 AlignmentException(struct pt_regs *regs)
314 #if defined(CONFIG_CMD_KGDB)
315 if (debugger_exception_handler && (*debugger_exception_handler)(regs))
320 print_backtrace((unsigned long *)regs->gpr[1]);
321 panic("Alignment Exception");
325 ProgramCheckException(struct pt_regs *regs)
329 #if defined(CONFIG_CMD_KGDB)
330 if (debugger_exception_handler && (*debugger_exception_handler)(regs))
337 if( esr_val & ESR_PIL )
338 printf( "** Illegal Instruction **\n" );
339 else if( esr_val & ESR_PPR )
340 printf( "** Privileged Instruction **\n" );
341 else if( esr_val & ESR_PTR )
342 printf( "** Trap Instruction **\n" );
344 print_backtrace((unsigned long *)regs->gpr[1]);
345 panic("Program Check Exception");
349 DecrementerPITException(struct pt_regs *regs)
352 * Reset PIT interrupt
357 * Call timer_interrupt routine in interrupts.c
359 timer_interrupt(NULL);
364 UnknownException(struct pt_regs *regs)
366 #if defined(CONFIG_CMD_KGDB)
367 if (debugger_exception_handler && (*debugger_exception_handler)(regs))
371 printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
372 regs->nip, regs->msr, regs->trap);
377 DebugException(struct pt_regs *regs)
379 printf("Debugger trap at @ %lx\n", regs->nip );
381 #if defined(CONFIG_CMD_BEDBUG)
382 do_bedbug_breakpoint( regs );
386 /* Probe an address by reading. If not present, return -1, otherwise
390 addr_probe(uint *addr)
395 __asm__ __volatile__( \
396 "1: lwz %0,0(%1)\n" \
400 ".section .fixup,\"ax\"\n" \
403 ".section __ex_table,\"a\"\n" \
407 : "=r" (retval) : "r"(addr));