3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #if defined(CONFIG_440)
33 typedef struct region {
36 unsigned long tlb_word2_i_value;
39 static int add_tlb_entry(unsigned long phys_addr,
40 unsigned long virt_addr,
41 unsigned long tlb_word0_size_value,
42 unsigned long tlb_word2_i_value)
45 unsigned long tlb_word0_value;
46 unsigned long tlb_word1_value;
47 unsigned long tlb_word2_value;
49 /* First, find the index of a TLB entry not being used */
50 for (i=0; i<PPC4XX_TLB_SIZE; i++) {
51 tlb_word0_value = mftlb1(i);
52 if ((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_DISABLE)
55 if (i >= PPC4XX_TLB_SIZE)
58 /* Second, create the TLB entry */
59 tlb_word0_value = TLB_WORD0_EPN_ENCODE(virt_addr) | TLB_WORD0_V_ENABLE |
60 TLB_WORD0_TS_0 | tlb_word0_size_value;
61 tlb_word1_value = TLB_WORD1_RPN_ENCODE(phys_addr) | TLB_WORD1_ERPN_ENCODE(0);
62 tlb_word2_value = TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE |
63 TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE |
64 TLB_WORD2_W_DISABLE | tlb_word2_i_value |
65 TLB_WORD2_M_DISABLE | TLB_WORD2_G_DISABLE |
66 TLB_WORD2_E_DISABLE | TLB_WORD2_UX_ENABLE |
67 TLB_WORD2_UW_ENABLE | TLB_WORD2_UR_ENABLE |
68 TLB_WORD2_SX_ENABLE | TLB_WORD2_SW_ENABLE |
71 /* Wait for all memory accesses to complete */
74 /* Third, add the TLB entries */
75 mttlb1(i, tlb_word0_value);
76 mttlb2(i, tlb_word1_value);
77 mttlb3(i, tlb_word2_value);
79 /* Execute an ISYNC instruction so that the new TLB entry takes effect */
85 static void program_tlb_addr(unsigned long phys_addr,
86 unsigned long virt_addr,
87 unsigned long mem_size,
88 unsigned long tlb_word2_i_value)
93 tlb_i = tlb_word2_i_value;
94 while (mem_size != 0) {
96 /* Add the TLB entries in to map the region. */
97 if (((phys_addr & TLB_256MB_ALIGN_MASK) == phys_addr) &&
98 (mem_size >= TLB_256MB_SIZE)) {
99 /* Add a 256MB TLB entry */
100 if ((rc = add_tlb_entry(phys_addr, virt_addr,
101 TLB_WORD0_SIZE_256MB, tlb_i)) == 0) {
102 mem_size -= TLB_256MB_SIZE;
103 phys_addr += TLB_256MB_SIZE;
105 } else if (((phys_addr & TLB_16MB_ALIGN_MASK) == phys_addr) &&
106 (mem_size >= TLB_16MB_SIZE)) {
107 /* Add a 16MB TLB entry */
108 if ((rc = add_tlb_entry(phys_addr, virt_addr,
109 TLB_WORD0_SIZE_16MB, tlb_i)) == 0) {
110 mem_size -= TLB_16MB_SIZE;
111 phys_addr += TLB_16MB_SIZE;
113 } else if (((phys_addr & TLB_1MB_ALIGN_MASK) == phys_addr) &&
114 (mem_size >= TLB_1MB_SIZE)) {
115 /* Add a 1MB TLB entry */
116 if ((rc = add_tlb_entry(phys_addr, virt_addr,
117 TLB_WORD0_SIZE_1MB, tlb_i)) == 0) {
118 mem_size -= TLB_1MB_SIZE;
119 phys_addr += TLB_1MB_SIZE;
121 } else if (((phys_addr & TLB_256KB_ALIGN_MASK) == phys_addr) &&
122 (mem_size >= TLB_256KB_SIZE)) {
123 /* Add a 256KB TLB entry */
124 if ((rc = add_tlb_entry(phys_addr, virt_addr,
125 TLB_WORD0_SIZE_256KB, tlb_i)) == 0) {
126 mem_size -= TLB_256KB_SIZE;
127 phys_addr += TLB_256KB_SIZE;
129 } else if (((phys_addr & TLB_64KB_ALIGN_MASK) == phys_addr) &&
130 (mem_size >= TLB_64KB_SIZE)) {
131 /* Add a 64KB TLB entry */
132 if ((rc = add_tlb_entry(phys_addr, virt_addr,
133 TLB_WORD0_SIZE_64KB, tlb_i)) == 0) {
134 mem_size -= TLB_64KB_SIZE;
135 phys_addr += TLB_64KB_SIZE;
137 } else if (((phys_addr & TLB_16KB_ALIGN_MASK) == phys_addr) &&
138 (mem_size >= TLB_16KB_SIZE)) {
139 /* Add a 16KB TLB entry */
140 if ((rc = add_tlb_entry(phys_addr, virt_addr,
141 TLB_WORD0_SIZE_16KB, tlb_i)) == 0) {
142 mem_size -= TLB_16KB_SIZE;
143 phys_addr += TLB_16KB_SIZE;
145 } else if (((phys_addr & TLB_4KB_ALIGN_MASK) == phys_addr) &&
146 (mem_size >= TLB_4KB_SIZE)) {
147 /* Add a 4KB TLB entry */
148 if ((rc = add_tlb_entry(phys_addr, virt_addr,
149 TLB_WORD0_SIZE_4KB, tlb_i)) == 0) {
150 mem_size -= TLB_4KB_SIZE;
151 phys_addr += TLB_4KB_SIZE;
153 } else if (((phys_addr & TLB_1KB_ALIGN_MASK) == phys_addr) &&
154 (mem_size >= TLB_1KB_SIZE)) {
155 /* Add a 1KB TLB entry */
156 if ((rc = add_tlb_entry(phys_addr, virt_addr,
157 TLB_WORD0_SIZE_1KB, tlb_i)) == 0) {
158 mem_size -= TLB_1KB_SIZE;
159 phys_addr += TLB_1KB_SIZE;
162 printf("ERROR: no TLB size exists for the base address 0x%0X.\n",
167 printf("ERROR: no TLB entries available for the base addr 0x%0X.\n",
175 * Program one (or multiple) TLB entries for one memory region
177 * Common usage for boards with SDRAM DIMM modules to dynamically
178 * configure the TLB's for the SDRAM
180 void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value)
182 region_t region_array;
184 region_array.base = phys_addr;
185 region_array.size = size;
186 region_array.tlb_word2_i_value = tlb_word2_i_value; /* en-/disable cache */
188 /* Call the routine to add in the tlb entries for the memory regions */
189 program_tlb_addr(region_array.base, virt_addr, region_array.size,
190 region_array.tlb_word2_i_value);
195 #endif /* CONFIG_440 */