3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #if defined(CONFIG_440)
29 #include <asm/cache.h>
33 typedef struct region {
36 unsigned long tlb_word2_i_value;
39 void remove_tlb(u32 vaddr, u32 size)
46 for (i=0; i<PPC4XX_TLB_SIZE; i++) {
47 tlb_word0_value = mftlb1(i);
48 tlb_vaddr = TLB_WORD0_EPN_DECODE(tlb_word0_value);
49 if (((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_ENABLE) &&
50 (tlb_vaddr >= vaddr)) {
52 * TLB is enabled and start address is lower or equal
53 * than the area we are looking for. Now we only have
54 * to check the size/end address for a match.
56 switch (tlb_word0_value & TLB_WORD0_SIZE_MASK) {
57 case TLB_WORD0_SIZE_1KB:
60 case TLB_WORD0_SIZE_4KB:
63 case TLB_WORD0_SIZE_16KB:
66 case TLB_WORD0_SIZE_64KB:
69 case TLB_WORD0_SIZE_256KB:
72 case TLB_WORD0_SIZE_1MB:
75 case TLB_WORD0_SIZE_16MB:
78 case TLB_WORD0_SIZE_256MB:
84 * Now check the end-address if it's in the range
86 if ((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1))
88 * Found a TLB in the range.
89 * Disable it by writing 0 to tlb0 word.
95 /* Execute an ISYNC instruction so that the new TLB entry takes effect */
100 * Change the I attribute (cache inhibited) of a TLB or multiple TLB's.
101 * This function is used to either turn cache on or off in a specific
104 void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value)
112 for (i=0; i<PPC4XX_TLB_SIZE; i++) {
113 tlb_word0_value = mftlb1(i);
114 tlb_vaddr = TLB_WORD0_EPN_DECODE(tlb_word0_value);
115 if (((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_ENABLE) &&
116 (tlb_vaddr >= vaddr)) {
118 * TLB is enabled and start address is lower or equal
119 * than the area we are looking for. Now we only have
120 * to check the size/end address for a match.
122 switch (tlb_word0_value & TLB_WORD0_SIZE_MASK) {
123 case TLB_WORD0_SIZE_1KB:
126 case TLB_WORD0_SIZE_4KB:
129 case TLB_WORD0_SIZE_16KB:
132 case TLB_WORD0_SIZE_64KB:
135 case TLB_WORD0_SIZE_256KB:
136 tlb_size = 256 << 10;
138 case TLB_WORD0_SIZE_1MB:
141 case TLB_WORD0_SIZE_16MB:
144 case TLB_WORD0_SIZE_256MB:
145 tlb_size = 256 << 20;
150 * Now check the end-address if it's in the range
152 if ((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1)) {
154 * Found a TLB in the range.
155 * Change cache attribute in tlb2 word.
158 TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE |
159 TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE |
160 TLB_WORD2_W_DISABLE | tlb_word2_i_value |
161 TLB_WORD2_M_DISABLE | TLB_WORD2_G_DISABLE |
162 TLB_WORD2_E_DISABLE | TLB_WORD2_UX_ENABLE |
163 TLB_WORD2_UW_ENABLE | TLB_WORD2_UR_ENABLE |
164 TLB_WORD2_SX_ENABLE | TLB_WORD2_SW_ENABLE |
168 * Now either flush or invalidate the dcache
170 if (tlb_word2_i_value)
175 mttlb3(i, tlb_word2_value);
181 /* Execute an ISYNC instruction so that the new TLB entry takes effect */
185 static int add_tlb_entry(unsigned long phys_addr,
186 unsigned long virt_addr,
187 unsigned long tlb_word0_size_value,
188 unsigned long tlb_word2_i_value)
191 unsigned long tlb_word0_value;
192 unsigned long tlb_word1_value;
193 unsigned long tlb_word2_value;
195 /* First, find the index of a TLB entry not being used */
196 for (i=0; i<PPC4XX_TLB_SIZE; i++) {
197 tlb_word0_value = mftlb1(i);
198 if ((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_DISABLE)
201 if (i >= PPC4XX_TLB_SIZE)
204 /* Second, create the TLB entry */
205 tlb_word0_value = TLB_WORD0_EPN_ENCODE(virt_addr) | TLB_WORD0_V_ENABLE |
206 TLB_WORD0_TS_0 | tlb_word0_size_value;
207 tlb_word1_value = TLB_WORD1_RPN_ENCODE(phys_addr) | TLB_WORD1_ERPN_ENCODE(0);
208 tlb_word2_value = TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE |
209 TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE |
210 TLB_WORD2_W_DISABLE | tlb_word2_i_value |
211 TLB_WORD2_M_DISABLE | TLB_WORD2_G_DISABLE |
212 TLB_WORD2_E_DISABLE | TLB_WORD2_UX_ENABLE |
213 TLB_WORD2_UW_ENABLE | TLB_WORD2_UR_ENABLE |
214 TLB_WORD2_SX_ENABLE | TLB_WORD2_SW_ENABLE |
217 /* Wait for all memory accesses to complete */
220 /* Third, add the TLB entries */
221 mttlb1(i, tlb_word0_value);
222 mttlb2(i, tlb_word1_value);
223 mttlb3(i, tlb_word2_value);
225 /* Execute an ISYNC instruction so that the new TLB entry takes effect */
231 static void program_tlb_addr(unsigned long phys_addr,
232 unsigned long virt_addr,
233 unsigned long mem_size,
234 unsigned long tlb_word2_i_value)
239 tlb_i = tlb_word2_i_value;
240 while (mem_size != 0) {
242 /* Add the TLB entries in to map the region. */
243 if (((phys_addr & TLB_256MB_ALIGN_MASK) == phys_addr) &&
244 (mem_size >= TLB_256MB_SIZE)) {
245 /* Add a 256MB TLB entry */
246 if ((rc = add_tlb_entry(phys_addr, virt_addr,
247 TLB_WORD0_SIZE_256MB, tlb_i)) == 0) {
248 mem_size -= TLB_256MB_SIZE;
249 phys_addr += TLB_256MB_SIZE;
250 virt_addr += TLB_256MB_SIZE;
252 } else if (((phys_addr & TLB_16MB_ALIGN_MASK) == phys_addr) &&
253 (mem_size >= TLB_16MB_SIZE)) {
254 /* Add a 16MB TLB entry */
255 if ((rc = add_tlb_entry(phys_addr, virt_addr,
256 TLB_WORD0_SIZE_16MB, tlb_i)) == 0) {
257 mem_size -= TLB_16MB_SIZE;
258 phys_addr += TLB_16MB_SIZE;
259 virt_addr += TLB_16MB_SIZE;
261 } else if (((phys_addr & TLB_1MB_ALIGN_MASK) == phys_addr) &&
262 (mem_size >= TLB_1MB_SIZE)) {
263 /* Add a 1MB TLB entry */
264 if ((rc = add_tlb_entry(phys_addr, virt_addr,
265 TLB_WORD0_SIZE_1MB, tlb_i)) == 0) {
266 mem_size -= TLB_1MB_SIZE;
267 phys_addr += TLB_1MB_SIZE;
268 virt_addr += TLB_1MB_SIZE;
270 } else if (((phys_addr & TLB_256KB_ALIGN_MASK) == phys_addr) &&
271 (mem_size >= TLB_256KB_SIZE)) {
272 /* Add a 256KB TLB entry */
273 if ((rc = add_tlb_entry(phys_addr, virt_addr,
274 TLB_WORD0_SIZE_256KB, tlb_i)) == 0) {
275 mem_size -= TLB_256KB_SIZE;
276 phys_addr += TLB_256KB_SIZE;
277 virt_addr += TLB_256KB_SIZE;
279 } else if (((phys_addr & TLB_64KB_ALIGN_MASK) == phys_addr) &&
280 (mem_size >= TLB_64KB_SIZE)) {
281 /* Add a 64KB TLB entry */
282 if ((rc = add_tlb_entry(phys_addr, virt_addr,
283 TLB_WORD0_SIZE_64KB, tlb_i)) == 0) {
284 mem_size -= TLB_64KB_SIZE;
285 phys_addr += TLB_64KB_SIZE;
286 virt_addr += TLB_64KB_SIZE;
288 } else if (((phys_addr & TLB_16KB_ALIGN_MASK) == phys_addr) &&
289 (mem_size >= TLB_16KB_SIZE)) {
290 /* Add a 16KB TLB entry */
291 if ((rc = add_tlb_entry(phys_addr, virt_addr,
292 TLB_WORD0_SIZE_16KB, tlb_i)) == 0) {
293 mem_size -= TLB_16KB_SIZE;
294 phys_addr += TLB_16KB_SIZE;
295 virt_addr += TLB_16KB_SIZE;
297 } else if (((phys_addr & TLB_4KB_ALIGN_MASK) == phys_addr) &&
298 (mem_size >= TLB_4KB_SIZE)) {
299 /* Add a 4KB TLB entry */
300 if ((rc = add_tlb_entry(phys_addr, virt_addr,
301 TLB_WORD0_SIZE_4KB, tlb_i)) == 0) {
302 mem_size -= TLB_4KB_SIZE;
303 phys_addr += TLB_4KB_SIZE;
304 virt_addr += TLB_4KB_SIZE;
306 } else if (((phys_addr & TLB_1KB_ALIGN_MASK) == phys_addr) &&
307 (mem_size >= TLB_1KB_SIZE)) {
308 /* Add a 1KB TLB entry */
309 if ((rc = add_tlb_entry(phys_addr, virt_addr,
310 TLB_WORD0_SIZE_1KB, tlb_i)) == 0) {
311 mem_size -= TLB_1KB_SIZE;
312 phys_addr += TLB_1KB_SIZE;
313 virt_addr += TLB_1KB_SIZE;
316 printf("ERROR: no TLB size exists for the base address 0x%0X.\n",
321 printf("ERROR: no TLB entries available for the base addr 0x%0X.\n",
329 * Program one (or multiple) TLB entries for one memory region
331 * Common usage for boards with SDRAM DIMM modules to dynamically
332 * configure the TLB's for the SDRAM
334 void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value)
336 region_t region_array;
338 region_array.base = phys_addr;
339 region_array.size = size;
340 region_array.tlb_word2_i_value = tlb_word2_i_value; /* en-/disable cache */
342 /* Call the routine to add in the tlb entries for the memory regions */
343 program_tlb_addr(region_array.base, virt_addr, region_array.size,
344 region_array.tlb_word2_i_value);
349 #endif /* CONFIG_440 */