2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 /*------------------------------------------------------------------------------+
27 * This source code has been made available to you by IBM on an AS-IS
28 * basis. Anyone receiving this source is licensed under IBM
29 * copyrights to use it in any way he or she deems fit, including
30 * copying it, modifying it, compiling it, and redistributing it either
31 * with or without modifications. No license under IBM patents or
32 * patent applications is to be implied by the copyright license.
34 * Any user of this software should understand that IBM cannot provide
35 * technical support for this software and will not be responsible for
36 * any consequences resulting from the use of this software.
38 * Any person who transfers this source code or any derivative work
39 * must include the IBM copyright notice, this paragraph, and the
40 * preceding two paragraphs in the transferred software.
42 * COPYRIGHT I B M CORPORATION 1995
43 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
44 *-------------------------------------------------------------------------------
47 /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
50 * The processor starts at 0xfffffffc and the code is executed
52 * in memory, but as long we don't jump around before relocating.
53 * board_init lies at a quite high address and when the cpu has
54 * jumped there, everything is ok.
55 * This works because the cpu gives the FLASH (CS0) the whole
56 * address space at startup, and board_init lies as a echo of
57 * the flash somewhere up there in the memorymap.
59 * board_init will change CS0 to be positioned at the correct
60 * address and (s)dram will be positioned at address 0
66 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
68 #include <ppc_asm.tmpl>
71 #include <asm/cache.h>
74 #ifndef CONFIG_IDENT_STRING
75 #define CONFIG_IDENT_STRING ""
78 #ifdef CFG_INIT_DCACHE_CS
79 # if (CFG_INIT_DCACHE_CS == 0)
83 # if (CFG_INIT_DCACHE_CS == 1)
87 # if (CFG_INIT_DCACHE_CS == 2)
91 # if (CFG_INIT_DCACHE_CS == 3)
95 # if (CFG_INIT_DCACHE_CS == 4)
99 # if (CFG_INIT_DCACHE_CS == 5)
103 # if (CFG_INIT_DCACHE_CS == 6)
107 # if (CFG_INIT_DCACHE_CS == 7)
111 #endif /* CFG_INIT_DCACHE_CS */
113 #if (defined(CFG_INIT_RAM_DCACHE) && (CFG_INIT_RAM_END > (4 << 10)))
114 #error Only 4k of init-ram is supported - please adjust CFG_INIT_RAM_END!
117 #define function_prolog(func_name) .text; \
121 #define function_epilog(func_name) .type func_name,@function; \
122 .size func_name,.-func_name
124 /* We don't want the MMU yet.
127 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
130 .extern ext_bus_cntlr_init
132 #ifdef CONFIG_NAND_U_BOOT
133 .extern reconfig_tlb0
137 * Set up GOT: Global Offset Table
139 * Use r14 to access the GOT
141 #if !defined(CONFIG_NAND_SPL)
143 GOT_ENTRY(_GOT2_TABLE_)
144 GOT_ENTRY(_FIXUP_TABLE_)
147 GOT_ENTRY(_start_of_vectors)
148 GOT_ENTRY(_end_of_vectors)
149 GOT_ENTRY(transfer_to_handler)
151 GOT_ENTRY(__init_end)
153 GOT_ENTRY(__bss_start)
155 #endif /* CONFIG_NAND_SPL */
157 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
159 * NAND U-Boot image is started from offset 0
162 #if defined(CONFIG_440)
166 bl cpu_init_f /* run low-level CPU init code (from Flash) */
171 * 440 Startup -- on reset only the top 4k of the effective
172 * address space is mapped in by an entry in the instruction
173 * and data shadow TLB. The .bootpg section is located in the
174 * top 4k & does only what's necessary to map in the the rest
175 * of the boot rom. Once the boot rom is mapped in we can
176 * proceed with normal startup.
178 * NOTE: CS0 only covers the top 2MB of the effective address
182 #if defined(CONFIG_440)
183 #if !defined(CONFIG_NAND_SPL)
184 .section .bootpg,"ax"
188 /**************************************************************************/
190 /*--------------------------------------------------------------------+
191 | 440EPX BUP Change - Hardware team request
192 +--------------------------------------------------------------------*/
193 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
198 /*----------------------------------------------------------------+
199 | Core bug fix. Clear the esr
200 +-----------------------------------------------------------------*/
203 /*----------------------------------------------------------------*/
204 /* Clear and set up some registers. */
205 /*----------------------------------------------------------------*/
206 iccci r0,r0 /* NOTE: operands not used for 440 */
207 dccci r0,r0 /* NOTE: operands not used for 440 */
214 /* NOTE: 440GX adds machine check status regs */
215 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
222 /*----------------------------------------------------------------*/
224 /*----------------------------------------------------------------*/
225 /* Disable store gathering & broadcast, guarantee inst/data
226 * cache block touch, force load/store alignment
227 * (see errata 1.12: 440_33)
229 lis r1,0x0030 /* store gathering & broadcast disable */
230 ori r1,r1,0x6000 /* cache touch */
233 /*----------------------------------------------------------------*/
234 /* Initialize debug */
235 /*----------------------------------------------------------------*/
237 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
238 bne skip_debug_init /* if set, don't clear debug register */
251 mtspr dbsr,r1 /* Clear all valid bits */
254 #if defined (CONFIG_440SPE)
255 /*----------------------------------------------------------------+
256 | Initialize Core Configuration Reg1.
257 | a. ICDPEI: Record even parity. Normal operation.
258 | b. ICTPEI: Record even parity. Normal operation.
259 | c. DCTPEI: Record even parity. Normal operation.
260 | d. DCDPEI: Record even parity. Normal operation.
261 | e. DCUPEI: Record even parity. Normal operation.
262 | f. DCMPEI: Record even parity. Normal operation.
263 | g. FCOM: Normal operation
264 | h. MMUPEI: Record even parity. Normal operation.
265 | i. FFF: Flush only as much data as necessary.
266 | j. TCS: Timebase increments from CPU clock.
267 +-----------------------------------------------------------------*/
271 /*----------------------------------------------------------------+
272 | Reset the timebase.
273 | The previous write to CCR1 sets the timebase source.
274 +-----------------------------------------------------------------*/
279 /*----------------------------------------------------------------*/
280 /* Setup interrupt vectors */
281 /*----------------------------------------------------------------*/
282 mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */
284 mtspr ivor0,r1 /* Critical input */
286 mtspr ivor1,r1 /* Machine check */
288 mtspr ivor2,r1 /* Data storage */
290 mtspr ivor3,r1 /* Instruction storage */
292 mtspr ivor4,r1 /* External interrupt */
294 mtspr ivor5,r1 /* Alignment */
296 mtspr ivor6,r1 /* Program check */
298 mtspr ivor7,r1 /* Floating point unavailable */
300 mtspr ivor8,r1 /* System call */
302 mtspr ivor9,r1 /* Auxiliary Processor unavailable */
304 mtspr ivor10,r1 /* Decrementer */
306 mtspr ivor13,r1 /* Data TLB error */
308 mtspr ivor14,r1 /* Instr TLB error */
310 mtspr ivor15,r1 /* Debug */
312 /*----------------------------------------------------------------*/
313 /* Configure cache regions */
314 /*----------------------------------------------------------------*/
332 /*----------------------------------------------------------------*/
333 /* Cache victim limits */
334 /*----------------------------------------------------------------*/
335 /* floors 0, ceiling max to use the entire cache -- nothing locked
342 /*----------------------------------------------------------------+
343 |Initialize MMUCR[STID] = 0.
344 +-----------------------------------------------------------------*/
351 /*----------------------------------------------------------------*/
352 /* Clear all TLB entries -- TID = 0, TS = 0 */
353 /*----------------------------------------------------------------*/
355 li r1,0x003f /* 64 TLB entries */
357 rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
363 /*----------------------------------------------------------------*/
364 /* TLB entry setup -- step thru tlbtab */
365 /*----------------------------------------------------------------*/
366 #if defined(CONFIG_440SPE)
367 /*----------------------------------------------------------------*/
368 /* We have different TLB tables for revA and rev B of 440SPe */
369 /*----------------------------------------------------------------*/
381 bl tlbtab /* Get tlbtab pointer */
384 li r1,0x003f /* 64 TLB entries max */
391 beq 2f /* 0 marks end */
394 tlbwe r0,r4,0 /* TLB Word 0 */
395 tlbwe r1,r4,1 /* TLB Word 1 */
396 tlbwe r2,r4,2 /* TLB Word 2 */
397 addi r4,r4,1 /* Next TLB */
400 /*----------------------------------------------------------------*/
401 /* Continue from 'normal' start */
402 /*----------------------------------------------------------------*/
405 #if defined(CONFIG_NAND_SPL)
406 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
407 defined(CONFIG_460EX) || defined(CONFIG_460GT)
409 * Enable internal SRAM (only on 440EPx/GRx, 440EP/GR have no OCM)
414 and r1,r1,r2 /* Disable parity check */
417 and r1,r1,r2 /* Disable pwr mgmt */
419 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
420 lis r1,0x4000 /* BAS = 8000_0000 */
421 ori r1,r1,0x4580 /* 16k */
422 mtdcr isram0_sb0cr,r1
425 #if defined(CONFIG_440EP)
427 * On 440EP with no internal SRAM, we setup SDRAM very early
428 * and copy the NAND_SPL to SDRAM and jump to it
430 /* Clear Dcache to use as RAM */
431 addis r3,r0,CFG_INIT_RAM_ADDR@h
432 ori r3,r3,CFG_INIT_RAM_ADDR@l
433 addis r4,r0,CFG_INIT_RAM_END@h
434 ori r4,r4,CFG_INIT_RAM_END@l
435 rlwinm. r5,r4,0,27,31
445 /*----------------------------------------------------------------*/
446 /* Setup the stack in internal SRAM */
447 /*----------------------------------------------------------------*/
448 lis r1,CFG_INIT_RAM_ADDR@h
449 ori r1,r1,CFG_INIT_SP_OFFSET@l
452 stwu r0,-4(r1) /* Terminate call chain */
454 stwu r1,-8(r1) /* Save back chain and move SP */
455 lis r0,RESET_VECTOR@h /* Address of reset vector */
456 ori r0,r0, RESET_VECTOR@l
457 stwu r1,-8(r1) /* Save back chain and move SP */
458 stw r0,+12(r1) /* Save return addr (underflow vect) */
462 #endif /* CONFIG_440EP */
465 * Copy SPL from cache into internal SRAM
467 li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
469 lis r2,CFG_NAND_BOOT_SPL_SRC@h
470 ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
471 lis r3,CFG_NAND_BOOT_SPL_DST@h
472 ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
479 * Jump to code in RAM
483 lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
484 ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
493 #endif /* CONFIG_NAND_SPL */
499 mtspr srr1,r0 /* Keep things disabled for now */
503 #endif /* CONFIG_440 */
506 * r3 - 1st arg to board_init(): IMMP pointer
507 * r4 - 2nd arg to board_init(): boot flag
509 #ifndef CONFIG_NAND_SPL
511 .long 0x27051956 /* U-Boot Magic Number */
512 .globl version_string
514 .ascii U_BOOT_VERSION
515 .ascii " (", __DATE__, " - ", __TIME__, ")"
516 .ascii CONFIG_IDENT_STRING, "\0"
518 . = EXC_OFF_SYS_RESET
519 .globl _start_of_vectors
522 /* Critical input. */
523 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
527 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
529 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
530 #endif /* CONFIG_440 */
532 /* Data Storage exception. */
533 STD_EXCEPTION(0x300, DataStorage, UnknownException)
535 /* Instruction Storage exception. */
536 STD_EXCEPTION(0x400, InstStorage, UnknownException)
538 /* External Interrupt exception. */
539 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
541 /* Alignment exception. */
544 EXCEPTION_PROLOG(SRR0, SRR1)
549 addi r3,r1,STACK_FRAME_OVERHEAD
551 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
552 lwz r6,GOT(transfer_to_handler)
556 .long AlignmentException - _start + _START_OFFSET
557 .long int_return - _start + _START_OFFSET
559 /* Program check exception */
562 EXCEPTION_PROLOG(SRR0, SRR1)
563 addi r3,r1,STACK_FRAME_OVERHEAD
565 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
566 lwz r6,GOT(transfer_to_handler)
570 .long ProgramCheckException - _start + _START_OFFSET
571 .long int_return - _start + _START_OFFSET
574 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
575 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
576 STD_EXCEPTION(0xa00, APU, UnknownException)
578 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
581 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
582 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
584 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
585 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
586 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
588 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
590 .globl _end_of_vectors
597 /*****************************************************************************/
598 #if defined(CONFIG_440)
600 /*----------------------------------------------------------------*/
601 /* Clear and set up some registers. */
602 /*----------------------------------------------------------------*/
605 mtspr dec,r0 /* prevent dec exceptions */
606 mtspr tbl,r0 /* prevent fit & wdt exceptions */
608 mtspr tsr,r1 /* clear all timer exception status */
609 mtspr tcr,r0 /* disable all */
610 mtspr esr,r0 /* clear exception syndrome register */
611 mtxer r0 /* clear integer exception register */
613 /*----------------------------------------------------------------*/
614 /* Debug setup -- some (not very good) ice's need an event*/
615 /* to establish control :-( Define CFG_INIT_DBCR to the dbsr */
616 /* value you need in this case 0x8cff 0000 should do the trick */
617 /*----------------------------------------------------------------*/
618 #if defined(CFG_INIT_DBCR)
621 mtspr dbsr,r1 /* Clear all status bits */
622 lis r0,CFG_INIT_DBCR@h
623 ori r0,r0,CFG_INIT_DBCR@l
628 /*----------------------------------------------------------------*/
629 /* Setup the internal SRAM */
630 /*----------------------------------------------------------------*/
633 #ifdef CFG_INIT_RAM_DCACHE
634 /* Clear Dcache to use as RAM */
635 addis r3,r0,CFG_INIT_RAM_ADDR@h
636 ori r3,r3,CFG_INIT_RAM_ADDR@l
637 addis r4,r0,CFG_INIT_RAM_END@h
638 ori r4,r4,CFG_INIT_RAM_END@l
639 rlwinm. r5,r4,0,27,31
651 * Lock the init-ram/stack in d-cache, so that other regions
652 * may use d-cache as well
653 * Note, that this current implementation locks exactly 4k
654 * of d-cache, so please make sure that you don't define a
655 * bigger init-ram area. Take a look at the lwmon5 440EPx
656 * implementation as a reference.
660 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
676 #endif /* CFG_INIT_RAM_DCACHE */
678 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
679 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
680 /* not all PPC's have internal SRAM usable as L2-cache */
681 #if defined(CONFIG_440GX) || \
682 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
683 defined(CONFIG_460EX) || defined(CONFIG_460GT)
684 mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
690 and r1,r1,r2 /* Disable parity check */
693 and r1,r1,r2 /* Disable pwr mgmt */
696 lis r1,0x8000 /* BAS = 8000_0000 */
697 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
698 ori r1,r1,0x0980 /* first 64k */
699 mtdcr isram0_sb0cr,r1
701 ori r1,r1,0x0980 /* second 64k */
702 mtdcr isram0_sb1cr,r1
704 ori r1,r1, 0x0980 /* third 64k */
705 mtdcr isram0_sb2cr,r1
707 ori r1,r1, 0x0980 /* fourth 64k */
708 mtdcr isram0_sb3cr,r1
709 #elif defined(CONFIG_440SPE)
710 lis r1,0x0000 /* BAS = 0000_0000 */
711 ori r1,r1,0x0984 /* first 64k */
712 mtdcr isram0_sb0cr,r1
714 ori r1,r1,0x0984 /* second 64k */
715 mtdcr isram0_sb1cr,r1
717 ori r1,r1, 0x0984 /* third 64k */
718 mtdcr isram0_sb2cr,r1
720 ori r1,r1, 0x0984 /* fourth 64k */
721 mtdcr isram0_sb3cr,r1
722 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
723 lis r1,0x4000 /* BAS = 8000_0000 */
724 ori r1,r1,0x4580 /* 16k */
725 mtdcr isram0_sb0cr,r1
726 #elif defined(CONFIG_440GP)
727 ori r1,r1,0x0380 /* 8k rw */
728 mtdcr isram0_sb0cr,r1
729 mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
731 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
733 /*----------------------------------------------------------------*/
734 /* Setup the stack in internal SRAM */
735 /*----------------------------------------------------------------*/
736 lis r1,CFG_INIT_RAM_ADDR@h
737 ori r1,r1,CFG_INIT_SP_OFFSET@l
740 stwu r0,-4(r1) /* Terminate call chain */
742 stwu r1,-8(r1) /* Save back chain and move SP */
743 lis r0,RESET_VECTOR@h /* Address of reset vector */
744 ori r0,r0, RESET_VECTOR@l
745 stwu r1,-8(r1) /* Save back chain and move SP */
746 stw r0,+12(r1) /* Save return addr (underflow vect) */
748 #ifdef CONFIG_NAND_SPL
749 bl nand_boot /* will not return */
753 bl cpu_init_f /* run low-level CPU init code (from Flash) */
757 #endif /* CONFIG_440 */
759 /*****************************************************************************/
761 /*----------------------------------------------------------------------- */
762 /* Set up some machine state registers. */
763 /*----------------------------------------------------------------------- */
764 addi r0,r0,0x0000 /* initialize r0 to zero */
765 mtspr esr,r0 /* clear Exception Syndrome Reg */
766 mttcr r0 /* timer control register */
767 mtexier r0 /* disable all interrupts */
768 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
769 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
770 mtdbsr r4 /* clear/reset the dbsr */
771 mtexisr r4 /* clear all pending interrupts */
773 mtexier r4 /* enable critical exceptions */
774 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
775 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
776 mtiocr r4 /* since bit not used) & DRC to latch */
777 /* data bus on rising edge of CAS */
778 /*----------------------------------------------------------------------- */
780 /*----------------------------------------------------------------------- */
782 /*----------------------------------------------------------------------- */
783 /* Invalidate i-cache and d-cache TAG arrays. */
784 /*----------------------------------------------------------------------- */
785 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
786 addi r4,0,1024 /* 1/4 of I-cache */
791 addic. r3,r3,-16 /* move back one cache line */
792 bne ..cloop /* loop back to do rest until r3 = 0 */
795 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
796 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
799 /* first copy IOP480 register base address into r3 */
800 addis r3,0,0x5000 /* IOP480 register base address hi */
801 /* ori r3,r3,0x0000 / IOP480 register base address lo */
804 /* use r4 as the working variable */
805 /* turn on CS3 (LOCCTL.7) */
806 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
807 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
808 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
811 #ifdef CONFIG_DASA_SIM
812 /* use r4 as the working variable */
813 /* turn on MA17 (LOCCTL.7) */
814 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
815 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
816 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
819 /* turn on MA16..13 (LCS0BRD.12 = 0) */
820 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
821 andi. r4,r4,0xefff /* make bit 12 = 0 */
822 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
824 /* make sure above stores all comlete before going on */
827 /* last thing, set local init status done bit (DEVINIT.31) */
828 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
829 oris r4,r4,0x8000 /* make bit 31 = 1 */
830 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
832 /* clear all pending interrupts and disable all interrupts */
833 li r4,-1 /* set p1 to 0xffffffff */
834 stw r4,0x1b0(r3) /* clear all pending interrupts */
835 stw r4,0x1b8(r3) /* clear all pending interrupts */
836 li r4,0 /* set r4 to 0 */
837 stw r4,0x1b4(r3) /* disable all interrupts */
838 stw r4,0x1bc(r3) /* disable all interrupts */
840 /* make sure above stores all comlete before going on */
843 /*----------------------------------------------------------------------- */
844 /* Enable two 128MB cachable regions. */
845 /*----------------------------------------------------------------------- */
848 mticcr r1 /* instruction cache */
852 mtdccr r1 /* data cache */
854 addis r1,r0,CFG_INIT_RAM_ADDR@h
855 ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */
856 li r0, 0 /* Make room for stack frame header and */
857 stwu r0, -4(r1) /* clear final stack frame so that */
858 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
860 GET_GOT /* initialize GOT access */
862 bl board_init_f /* run first part of init code (from Flash) */
864 #endif /* CONFIG_IOP480 */
866 /*****************************************************************************/
867 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
868 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
869 defined(CONFIG_405EX) || defined(CONFIG_405)
870 /*----------------------------------------------------------------------- */
871 /* Clear and set up some registers. */
872 /*----------------------------------------------------------------------- */
874 #if !defined(CONFIG_405EX)
878 * On 405EX, completely clearing the SGR leads to PPC hangup
879 * upon PCIe configuration access. The PCIe memory regions
880 * need to be guarded!
887 mtesr r4 /* clear Exception Syndrome Reg */
888 mttcr r4 /* clear Timer Control Reg */
889 mtxer r4 /* clear Fixed-Point Exception Reg */
890 mtevpr r4 /* clear Exception Vector Prefix Reg */
891 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
892 /* dbsr is cleared by setting bits to 1) */
893 mtdbsr r4 /* clear/reset the dbsr */
895 /*----------------------------------------------------------------------- */
896 /* Invalidate I and D caches. Enable I cache for defined memory regions */
897 /* to speed things up. Leave the D cache disabled for now. It will be */
898 /* enabled/left disabled later based on user selected menu options. */
899 /* Be aware that the I cache may be disabled later based on the menu */
900 /* options as well. See miscLib/main.c. */
901 /*----------------------------------------------------------------------- */
905 /*----------------------------------------------------------------------- */
906 /* Enable two 128MB cachable regions. */
907 /*----------------------------------------------------------------------- */
910 mticcr r4 /* instruction cache */
915 mtdccr r4 /* data cache */
917 #if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) || defined(CONFIG_405EX)
918 /*----------------------------------------------------------------------- */
919 /* Tune the speed and size for flash CS0 */
920 /*----------------------------------------------------------------------- */
921 bl ext_bus_cntlr_init
923 #if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
925 * Boards like the Kilauea (405EX) don't have OCM and can't use
926 * DCache for init-ram. So setup stack here directly after the
927 * SDRAM is initialized.
929 lis r1, CFG_INIT_RAM_ADDR@h
930 ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
932 li r0, 0 /* Make room for stack frame header and */
933 stwu r0, -4(r1) /* clear final stack frame so that */
934 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
936 * Set up a dummy frame to store reset vector as return address.
937 * this causes stack underflow to reset board.
939 stwu r1, -8(r1) /* Save back chain and move SP */
940 lis r0, RESET_VECTOR@h /* Address of reset vector */
941 ori r0, r0, RESET_VECTOR@l
942 stwu r1, -8(r1) /* Save back chain and move SP */
943 stw r0, +12(r1) /* Save return addr (underflow vect) */
944 #endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
946 #if defined(CONFIG_405EP)
947 /*----------------------------------------------------------------------- */
948 /* DMA Status, clear to come up clean */
949 /*----------------------------------------------------------------------- */
950 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
954 bl ppc405ep_init /* do ppc405ep specific init */
955 #endif /* CONFIG_405EP */
957 #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
958 #if defined(CONFIG_405EZ)
959 /********************************************************************
960 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
961 *******************************************************************/
963 * We can map the OCM on the PLB3, so map it at
964 * CFG_OCM_DATA_ADDR + 0x8000
966 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
967 ori r3,r3,CFG_OCM_DATA_ADDR@l
968 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
969 mtdcr ocmplb3cr1,r3 /* Set PLB Access */
970 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
971 mtdcr ocmplb3cr2,r3 /* Set PLB Access */
974 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
975 ori r3,r3,CFG_OCM_DATA_ADDR@l
976 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
977 mtdcr ocmdscr1, r3 /* Set Data Side */
978 mtdcr ocmiscr1, r3 /* Set Instruction Side */
979 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
980 mtdcr ocmdscr2, r3 /* Set Data Side */
981 mtdcr ocmiscr2, r3 /* Set Instruction Side */
982 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
986 #else /* CONFIG_405EZ */
987 /********************************************************************
988 * Setup OCM - On Chip Memory
989 *******************************************************************/
993 mfdcr r3, ocmiscntl /* get instr-side IRAM config */
994 mfdcr r4, ocmdscntl /* get data-side IRAM config */
995 and r3, r3, r0 /* disable data-side IRAM */
996 and r4, r4, r0 /* disable data-side IRAM */
997 mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
998 mtdcr ocmdscntl, r4 /* set data-side IRAM config */
1001 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
1002 ori r3,r3,CFG_OCM_DATA_ADDR@l
1004 addis r4, 0, 0xC000 /* OCM data area enabled */
1007 #endif /* CONFIG_405EZ */
1010 #ifdef CONFIG_NAND_SPL
1012 * Copy SPL from cache into internal SRAM
1014 li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
1016 lis r2,CFG_NAND_BOOT_SPL_SRC@h
1017 ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
1018 lis r3,CFG_NAND_BOOT_SPL_DST@h
1019 ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
1026 * Jump to code in RAM
1030 lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
1031 ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
1040 #endif /* CONFIG_NAND_SPL */
1042 /*----------------------------------------------------------------------- */
1043 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
1044 /*----------------------------------------------------------------------- */
1045 #ifdef CFG_INIT_DCACHE_CS
1046 /*----------------------------------------------------------------------- */
1047 /* Memory Bank x (nothingness) initialization 1GB+64MEG */
1048 /* used as temporary stack pointer for stage0 */
1049 /*----------------------------------------------------------------------- */
1062 /* turn on data cache for this region */
1066 /* set stack pointer and clear stack to known value */
1068 lis r1,CFG_INIT_RAM_ADDR@h
1069 ori r1,r1,CFG_INIT_SP_OFFSET@l
1071 li r4,2048 /* we store 2048 words to stack */
1074 lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */
1075 ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */
1077 lis r4,0xdead /* we store 0xdeaddead in the stack */
1084 li r0, 0 /* Make room for stack frame header and */
1085 stwu r0, -4(r1) /* clear final stack frame so that */
1086 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
1088 * Set up a dummy frame to store reset vector as return address.
1089 * this causes stack underflow to reset board.
1091 stwu r1, -8(r1) /* Save back chain and move SP */
1092 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1093 ori r0, r0, RESET_VECTOR@l
1094 stwu r1, -8(r1) /* Save back chain and move SP */
1095 stw r0, +12(r1) /* Save return addr (underflow vect) */
1097 #elif defined(CFG_TEMP_STACK_OCM) && \
1098 (defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE))
1103 /* Set up Stack at top of OCM */
1104 lis r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h
1105 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l
1107 /* Set up a zeroized stack frame so that backtrace works right */
1113 * Set up a dummy frame to store reset vector as return address.
1114 * this causes stack underflow to reset board.
1116 stwu r1, -8(r1) /* Save back chain and move SP */
1117 lis r0, RESET_VECTOR@h /* Address of reset vector */
1118 ori r0, r0, RESET_VECTOR@l
1119 stwu r1, -8(r1) /* Save back chain and move SP */
1120 stw r0, +12(r1) /* Save return addr (underflow vect) */
1121 #endif /* CFG_INIT_DCACHE_CS */
1123 /*----------------------------------------------------------------------- */
1124 /* Initialize SDRAM Controller */
1125 /*----------------------------------------------------------------------- */
1128 #ifdef CONFIG_NAND_SPL
1129 bl nand_boot /* will not return */
1131 GET_GOT /* initialize GOT access */
1133 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1135 /* NEVER RETURNS! */
1136 bl board_init_f /* run first part of init code (from Flash) */
1137 #endif /* CONFIG_NAND_SPL */
1139 #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1140 /*----------------------------------------------------------------------- */
1143 #ifndef CONFIG_NAND_SPL
1145 * This code finishes saving the registers to the exception frame
1146 * and jumps to the appropriate handler for the exception.
1147 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1149 .globl transfer_to_handler
1150 transfer_to_handler:
1160 andi. r24,r23,0x3f00 /* get vector offset */
1164 mtspr SPRG2,r22 /* r1 is now kernel sp */
1165 lwz r24,0(r23) /* virtual address of handler */
1166 lwz r23,4(r23) /* where to go when done */
1171 rfi /* jump to handler, enable MMU */
1174 mfmsr r28 /* Disable interrupts */
1178 SYNC /* Some chip revs need this... */
1193 lwz r2,_NIP(r1) /* Restore environment */
1204 mfmsr r28 /* Disable interrupts */
1208 SYNC /* Some chip revs need this... */
1223 lwz r2,_NIP(r1) /* Restore environment */
1235 mfmsr r28 /* Disable interrupts */
1239 SYNC /* Some chip revs need this... */
1254 lwz r2,_NIP(r1) /* Restore environment */
1263 #endif /* CONFIG_440 */
1271 /*------------------------------------------------------------------------------- */
1272 /* Function: out16 */
1273 /* Description: Output 16 bits */
1274 /*------------------------------------------------------------------------------- */
1280 /*------------------------------------------------------------------------------- */
1281 /* Function: out16r */
1282 /* Description: Byte reverse and output 16 bits */
1283 /*------------------------------------------------------------------------------- */
1289 /*------------------------------------------------------------------------------- */
1290 /* Function: out32r */
1291 /* Description: Byte reverse and output 32 bits */
1292 /*------------------------------------------------------------------------------- */
1298 /*------------------------------------------------------------------------------- */
1299 /* Function: in16 */
1300 /* Description: Input 16 bits */
1301 /*------------------------------------------------------------------------------- */
1307 /*------------------------------------------------------------------------------- */
1308 /* Function: in16r */
1309 /* Description: Input 16 bits and byte reverse */
1310 /*------------------------------------------------------------------------------- */
1316 /*------------------------------------------------------------------------------- */
1317 /* Function: in32r */
1318 /* Description: Input 32 bits and byte reverse */
1319 /*------------------------------------------------------------------------------- */
1326 * void relocate_code (addr_sp, gd, addr_moni)
1328 * This "function" does not return, instead it continues in RAM
1329 * after relocating the monitor code.
1333 * r5 = length in bytes
1334 * r6 = cachelinesize
1336 .globl relocate_code
1338 #ifdef CONFIG_4xx_DCACHE
1340 * We need to flush the Init Data before the dcache will be
1350 addi r4,r4,0x200 /* should be enough for init data */
1351 bl flush_dcache_range
1359 #ifdef CFG_INIT_RAM_DCACHE
1361 * Unlock the previously locked d-cache
1365 /* set TFLOOR/NFLOOR to 0 again */
1381 #endif /* CFG_INIT_RAM_DCACHE */
1383 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1384 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1385 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
1386 defined(CONFIG_460EX) || defined(CONFIG_460GT)
1388 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1389 * to speed up the boot process. Now this cache needs to be disabled.
1391 iccci 0,0 /* Invalidate inst cache */
1392 dccci 0,0 /* Invalidate data cache, now no longer our stack */
1395 #ifdef CFG_TLB_FOR_BOOT_FLASH
1396 addi r1,r0,CFG_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1398 addi r1,r0,0x0000 /* Default TLB entry is #0 */
1400 tlbre r0,r1,0x0002 /* Read contents */
1401 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1402 tlbwe r0,r1,0x0002 /* Save it out */
1406 mr r1, r3 /* Set new stack pointer */
1407 mr r9, r4 /* Save copy of Init Data pointer */
1408 mr r10, r5 /* Save copy of Destination Address */
1410 mr r3, r5 /* Destination Address */
1411 lis r4, CFG_MONITOR_BASE@h /* Source Address */
1412 ori r4, r4, CFG_MONITOR_BASE@l
1413 lwz r5, GOT(__init_end)
1415 li r6, L1_CACHE_BYTES /* Cache Line Size */
1420 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
1426 /* First our own GOT */
1428 /* the the one used by the C code */
1438 beq cr1,4f /* In place copy is not necessary */
1439 beq 7f /* Protect against 0 count */
1458 * Now flush the cache: note that we must start from a cache aligned
1459 * address. Otherwise we might miss one cache line.
1463 beq 7f /* Always flush prefetch queue in any case */
1471 sync /* Wait for all dcbst to complete on bus */
1477 7: sync /* Wait for all icbi to complete on bus */
1481 * We are done. Do not return, instead branch to second part of board
1482 * initialization, now running from RAM.
1485 addi r0, r10, in_ram - _start + _START_OFFSET
1487 blr /* NEVER RETURNS! */
1492 * Relocation Function, r14 point to got2+0x8000
1494 * Adjust got2 pointers, no need to check for 0, this code
1495 * already puts a few entries in the table.
1497 li r0,__got2_entries@sectoff@l
1498 la r3,GOT(_GOT2_TABLE_)
1499 lwz r11,GOT(_GOT2_TABLE_)
1509 * Now adjust the fixups and the pointers to the fixups
1510 * in case we need to move ourselves again.
1512 2: li r0,__fixup_entries@sectoff@l
1513 lwz r3,GOT(_FIXUP_TABLE_)
1527 * Now clear BSS segment
1529 lwz r3,GOT(__bss_start)
1552 mr r3, r9 /* Init Data pointer */
1553 mr r4, r10 /* Destination Address */
1557 * Copy exception vector code to low memory
1560 * r7: source address, r8: end address, r9: target address
1564 lwz r7, GOT(_start_of_vectors)
1565 lwz r8, GOT(_end_of_vectors)
1567 li r9, 0x100 /* reset vector always at 0x100 */
1570 bgelr /* return if r7>=r8 - just in case */
1572 mflr r4 /* save link register */
1582 * relocate `hdlr' and `int_return' entries
1584 li r7, .L_MachineCheck - _start + _START_OFFSET
1585 li r8, Alignment - _start + _START_OFFSET
1588 addi r7, r7, 0x100 /* next exception vector */
1592 li r7, .L_Alignment - _start + _START_OFFSET
1595 li r7, .L_ProgramCheck - _start + _START_OFFSET
1599 li r7, .L_FPUnavailable - _start + _START_OFFSET
1602 li r7, .L_Decrementer - _start + _START_OFFSET
1605 li r7, .L_APU - _start + _START_OFFSET
1608 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1611 li r7, .L_DataTLBError - _start + _START_OFFSET
1613 #else /* CONFIG_440 */
1614 li r7, .L_PIT - _start + _START_OFFSET
1617 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1620 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1622 #endif /* CONFIG_440 */
1624 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1627 #if !defined(CONFIG_440)
1628 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1629 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1630 mtmsr r7 /* change MSR */
1633 b __440_msr_continue
1636 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1637 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1645 mtlr r4 /* restore link register */
1649 * Function: relocate entries for one exception vector
1652 lwz r0, 0(r7) /* hdlr ... */
1653 add r0, r0, r3 /* ... += dest_addr */
1656 lwz r0, 4(r7) /* int_return ... */
1657 add r0, r0, r3 /* ... += dest_addr */
1662 #if defined(CONFIG_440)
1663 /*----------------------------------------------------------------------------+
1665 +----------------------------------------------------------------------------*/
1666 function_prolog(dcbz_area)
1667 rlwinm. r5,r4,0,27,31
1668 rlwinm r5,r4,27,5,31
1677 function_epilog(dcbz_area)
1679 /*----------------------------------------------------------------------------+
1680 | dflush. Assume 32K at vector address is cachable.
1681 +----------------------------------------------------------------------------*/
1682 function_prolog(dflush)
1684 rlwinm r8,r9,0,15,13
1685 rlwinm r8,r8,0,17,15
1706 function_epilog(dflush)
1707 #endif /* CONFIG_440 */
1708 #endif /* CONFIG_NAND_SPL */
1710 /*------------------------------------------------------------------------------- */
1712 /* Description: Input 8 bits */
1713 /*------------------------------------------------------------------------------- */
1719 /*------------------------------------------------------------------------------- */
1720 /* Function: out8 */
1721 /* Description: Output 8 bits */
1722 /*------------------------------------------------------------------------------- */
1728 /*------------------------------------------------------------------------------- */
1729 /* Function: out32 */
1730 /* Description: Output 32 bits */
1731 /*------------------------------------------------------------------------------- */
1737 /*------------------------------------------------------------------------------- */
1738 /* Function: in32 */
1739 /* Description: Input 32 bits */
1740 /*------------------------------------------------------------------------------- */
1746 /**************************************************************************/
1747 /* PPC405EP specific stuff */
1748 /**************************************************************************/
1752 #ifdef CONFIG_BUBINGA
1754 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1755 * function) to support FPGA and NVRAM accesses below.
1758 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1759 ori r3,r3,GPIO0_OSRH@l
1760 lis r4,CFG_GPIO0_OSRH@h
1761 ori r4,r4,CFG_GPIO0_OSRH@l
1764 ori r3,r3,GPIO0_OSRL@l
1765 lis r4,CFG_GPIO0_OSRL@h
1766 ori r4,r4,CFG_GPIO0_OSRL@l
1769 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1770 ori r3,r3,GPIO0_ISR1H@l
1771 lis r4,CFG_GPIO0_ISR1H@h
1772 ori r4,r4,CFG_GPIO0_ISR1H@l
1774 lis r3,GPIO0_ISR1L@h
1775 ori r3,r3,GPIO0_ISR1L@l
1776 lis r4,CFG_GPIO0_ISR1L@h
1777 ori r4,r4,CFG_GPIO0_ISR1L@l
1780 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1781 ori r3,r3,GPIO0_TSRH@l
1782 lis r4,CFG_GPIO0_TSRH@h
1783 ori r4,r4,CFG_GPIO0_TSRH@l
1786 ori r3,r3,GPIO0_TSRL@l
1787 lis r4,CFG_GPIO0_TSRL@h
1788 ori r4,r4,CFG_GPIO0_TSRL@l
1791 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1792 ori r3,r3,GPIO0_TCR@l
1793 lis r4,CFG_GPIO0_TCR@h
1794 ori r4,r4,CFG_GPIO0_TCR@l
1797 li r3,pb1ap /* program EBC bank 1 for RTC access */
1799 lis r3,CFG_EBC_PB1AP@h
1800 ori r3,r3,CFG_EBC_PB1AP@l
1804 lis r3,CFG_EBC_PB1CR@h
1805 ori r3,r3,CFG_EBC_PB1CR@l
1808 li r3,pb1ap /* program EBC bank 1 for RTC access */
1810 lis r3,CFG_EBC_PB1AP@h
1811 ori r3,r3,CFG_EBC_PB1AP@l
1815 lis r3,CFG_EBC_PB1CR@h
1816 ori r3,r3,CFG_EBC_PB1CR@l
1819 li r3,pb4ap /* program EBC bank 4 for FPGA access */
1821 lis r3,CFG_EBC_PB4AP@h
1822 ori r3,r3,CFG_EBC_PB4AP@l
1826 lis r3,CFG_EBC_PB4CR@h
1827 ori r3,r3,CFG_EBC_PB4CR@l
1832 !-----------------------------------------------------------------------
1833 ! Check to see if chip is in bypass mode.
1834 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1835 ! CPU reset Otherwise, skip this step and keep going.
1836 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1837 ! will not be fast enough for the SDRAM (min 66MHz)
1838 !-----------------------------------------------------------------------
1840 mfdcr r5, CPC0_PLLMR1
1841 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1844 beq pll_done /* if SSCS =b'1' then PLL has */
1845 /* already been set */
1846 /* and CPU has been reset */
1847 /* so skip to next section */
1849 #ifdef CONFIG_BUBINGA
1851 !-----------------------------------------------------------------------
1852 ! Read NVRAM to get value to write in PLLMR.
1853 ! If value has not been correctly saved, write default value
1854 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1855 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1857 ! WARNING: This code assumes the first three words in the nvram_t
1858 ! structure in openbios.h. Changing the beginning of
1859 ! the structure will break this code.
1861 !-----------------------------------------------------------------------
1863 addis r3,0,NVRAM_BASE@h
1864 addi r3,r3,NVRAM_BASE@l
1867 addis r5,0,NVRVFY1@h
1868 addi r5,r5,NVRVFY1@l
1869 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1873 addis r5,0,NVRVFY2@h
1874 addi r5,r5,NVRVFY2@l
1875 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1877 addi r3,r3,8 /* Skip over conf_size */
1878 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1879 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1880 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1881 cmpi cr0,0,r5,1 /* See if PLL is locked */
1884 #endif /* CONFIG_BUBINGA */
1888 andi. r5, r4, CPC0_BOOT_SEP@l
1889 bne strap_1 /* serial eeprom present */
1890 addis r5,0,CPLD_REG0_ADDR@h
1891 ori r5,r5,CPLD_REG0_ADDR@l
1894 #endif /* CONFIG_TAIHU */
1896 #if defined(CONFIG_ZEUS)
1898 andi. r5, r4, CPC0_BOOT_SEP@l
1899 bne strap_1 /* serial eeprom present */
1906 mfdcr r3, CPC0_PLLMR0
1907 mfdcr r4, CPC0_PLLMR1
1911 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1912 ori r3,r3,PLLMR0_DEFAULT@l /* */
1913 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1914 ori r4,r4,PLLMR1_DEFAULT@l /* */
1919 addis r3,0,PLLMR0_DEFAULT_PCI66@h
1920 ori r3,r3,PLLMR0_DEFAULT_PCI66@l
1921 addis r4,0,PLLMR1_DEFAULT_PCI66@h
1922 ori r4,r4,PLLMR1_DEFAULT_PCI66@l
1925 mfdcr r3, CPC0_PLLMR0
1926 mfdcr r4, CPC0_PLLMR1
1927 #endif /* CONFIG_TAIHU */
1930 b pll_write /* Write the CPC0_PLLMR with new value */
1934 !-----------------------------------------------------------------------
1935 ! Clear Soft Reset Register
1936 ! This is needed to enable PCI if not booting from serial EPROM
1937 !-----------------------------------------------------------------------
1947 blr /* return to main code */
1950 !-----------------------------------------------------------------------------
1951 ! Function: pll_write
1952 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1954 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
1956 ! 3. Clock dividers are set while PLL is held in reset and bypassed
1957 ! 4. PLL Reset is cleared
1958 ! 5. Wait 100us for PLL to lock
1959 ! 6. A core reset is performed
1960 ! Input: r3 = Value to write to CPC0_PLLMR0
1961 ! Input: r4 = Value to write to CPC0_PLLMR1
1963 !-----------------------------------------------------------------------------
1968 ori r5,r5,0x0101 /* Stop the UART clocks */
1969 mtdcr CPC0_UCR,r5 /* Before changing PLL */
1971 mfdcr r5, CPC0_PLLMR1
1972 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
1973 mtdcr CPC0_PLLMR1,r5
1974 oris r5,r5,0x4000 /* Set PLL Reset */
1975 mtdcr CPC0_PLLMR1,r5
1977 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
1978 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
1979 oris r5,r5,0x4000 /* Set PLL Reset */
1980 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
1981 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
1982 mtdcr CPC0_PLLMR1,r5
1985 ! Wait min of 100us for PLL to lock.
1986 ! See CMOS 27E databook for more info.
1987 ! At 200MHz, that means waiting 20,000 instructions
1989 addi r3,0,20000 /* 2000 = 0x4e20 */
1994 oris r5,r5,0x8000 /* Enable PLL */
1995 mtdcr CPC0_PLLMR1,r5 /* Engage */
1998 * Reset CPU to guarantee timings are OK
1999 * Not sure if this is needed...
2002 mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
2003 /* execution will continue from the poweron */
2004 /* vector of 0xfffffffc */
2005 #endif /* CONFIG_405EP */
2007 #if defined(CONFIG_440)
2008 /*----------------------------------------------------------------------------+
2010 +----------------------------------------------------------------------------*/
2011 function_prolog(mttlb3)
2014 function_epilog(mttlb3)
2016 /*----------------------------------------------------------------------------+
2018 +----------------------------------------------------------------------------*/
2019 function_prolog(mftlb3)
2022 function_epilog(mftlb3)
2024 /*----------------------------------------------------------------------------+
2026 +----------------------------------------------------------------------------*/
2027 function_prolog(mttlb2)
2030 function_epilog(mttlb2)
2032 /*----------------------------------------------------------------------------+
2034 +----------------------------------------------------------------------------*/
2035 function_prolog(mftlb2)
2038 function_epilog(mftlb2)
2040 /*----------------------------------------------------------------------------+
2042 +----------------------------------------------------------------------------*/
2043 function_prolog(mttlb1)
2046 function_epilog(mttlb1)
2048 /*----------------------------------------------------------------------------+
2050 +----------------------------------------------------------------------------*/
2051 function_prolog(mftlb1)
2054 function_epilog(mftlb1)
2055 #endif /* CONFIG_440 */