2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 /*------------------------------------------------------------------------------+
27 * This source code has been made available to you by IBM on an AS-IS
28 * basis. Anyone receiving this source is licensed under IBM
29 * copyrights to use it in any way he or she deems fit, including
30 * copying it, modifying it, compiling it, and redistributing it either
31 * with or without modifications. No license under IBM patents or
32 * patent applications is to be implied by the copyright license.
34 * Any user of this software should understand that IBM cannot provide
35 * technical support for this software and will not be responsible for
36 * any consequences resulting from the use of this software.
38 * Any person who transfers this source code or any derivative work
39 * must include the IBM copyright notice, this paragraph, and the
40 * preceding two paragraphs in the transferred software.
42 * COPYRIGHT I B M CORPORATION 1995
43 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
44 *-------------------------------------------------------------------------------
47 /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
50 * The processor starts at 0xfffffffc and the code is executed
52 * in memory, but as long we don't jump around before relocating.
53 * board_init lies at a quite high address and when the cpu has
54 * jumped there, everything is ok.
55 * This works because the cpu gives the FLASH (CS0) the whole
56 * address space at startup, and board_init lies as a echo of
57 * the flash somewhere up there in the memorymap.
59 * board_init will change CS0 to be positioned at the correct
60 * address and (s)dram will be positioned at address 0
66 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
68 #include <ppc_asm.tmpl>
71 #include <asm/cache.h>
74 #ifndef CONFIG_IDENT_STRING
75 #define CONFIG_IDENT_STRING ""
78 #ifdef CFG_INIT_DCACHE_CS
79 # if (CFG_INIT_DCACHE_CS == 0)
83 # if (CFG_INIT_DCACHE_CS == 1)
87 # if (CFG_INIT_DCACHE_CS == 2)
91 # if (CFG_INIT_DCACHE_CS == 3)
95 # if (CFG_INIT_DCACHE_CS == 4)
99 # if (CFG_INIT_DCACHE_CS == 5)
103 # if (CFG_INIT_DCACHE_CS == 6)
107 # if (CFG_INIT_DCACHE_CS == 7)
111 #endif /* CFG_INIT_DCACHE_CS */
113 #define function_prolog(func_name) .text; \
117 #define function_epilog(func_name) .type func_name,@function; \
118 .size func_name,.-func_name
120 /* We don't want the MMU yet.
123 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
126 .extern ext_bus_cntlr_init
128 #ifdef CONFIG_NAND_U_BOOT
129 .extern reconfig_tlb0
133 * Set up GOT: Global Offset Table
135 * Use r14 to access the GOT
137 #if !defined(CONFIG_NAND_SPL)
139 GOT_ENTRY(_GOT2_TABLE_)
140 GOT_ENTRY(_FIXUP_TABLE_)
143 GOT_ENTRY(_start_of_vectors)
144 GOT_ENTRY(_end_of_vectors)
145 GOT_ENTRY(transfer_to_handler)
147 GOT_ENTRY(__init_end)
149 GOT_ENTRY(__bss_start)
151 #endif /* CONFIG_NAND_SPL */
153 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
155 * NAND U-Boot image is started from offset 0
158 #if defined(CONFIG_440)
162 bl cpu_init_f /* run low-level CPU init code (from Flash) */
167 * 440 Startup -- on reset only the top 4k of the effective
168 * address space is mapped in by an entry in the instruction
169 * and data shadow TLB. The .bootpg section is located in the
170 * top 4k & does only what's necessary to map in the the rest
171 * of the boot rom. Once the boot rom is mapped in we can
172 * proceed with normal startup.
174 * NOTE: CS0 only covers the top 2MB of the effective address
178 #if defined(CONFIG_440)
179 #if !defined(CONFIG_NAND_SPL)
180 .section .bootpg,"ax"
184 /**************************************************************************/
186 /*--------------------------------------------------------------------+
187 | 440EPX BUP Change - Hardware team request
188 +--------------------------------------------------------------------*/
189 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
194 /*----------------------------------------------------------------+
195 | Core bug fix. Clear the esr
196 +-----------------------------------------------------------------*/
199 /*----------------------------------------------------------------*/
200 /* Clear and set up some registers. */
201 /*----------------------------------------------------------------*/
202 iccci r0,r0 /* NOTE: operands not used for 440 */
203 dccci r0,r0 /* NOTE: operands not used for 440 */
210 /* NOTE: 440GX adds machine check status regs */
211 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
218 /*----------------------------------------------------------------*/
220 /*----------------------------------------------------------------*/
221 /* Disable store gathering & broadcast, guarantee inst/data
222 * cache block touch, force load/store alignment
223 * (see errata 1.12: 440_33)
225 lis r1,0x0030 /* store gathering & broadcast disable */
226 ori r1,r1,0x6000 /* cache touch */
229 /*----------------------------------------------------------------*/
230 /* Initialize debug */
231 /*----------------------------------------------------------------*/
233 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
234 bne skip_debug_init /* if set, don't clear debug register */
247 mtspr dbsr,r1 /* Clear all valid bits */
250 #if defined (CONFIG_440SPE)
251 /*----------------------------------------------------------------+
252 | Initialize Core Configuration Reg1.
253 | a. ICDPEI: Record even parity. Normal operation.
254 | b. ICTPEI: Record even parity. Normal operation.
255 | c. DCTPEI: Record even parity. Normal operation.
256 | d. DCDPEI: Record even parity. Normal operation.
257 | e. DCUPEI: Record even parity. Normal operation.
258 | f. DCMPEI: Record even parity. Normal operation.
259 | g. FCOM: Normal operation
260 | h. MMUPEI: Record even parity. Normal operation.
261 | i. FFF: Flush only as much data as necessary.
262 | j. TCS: Timebase increments from CPU clock.
263 +-----------------------------------------------------------------*/
267 /*----------------------------------------------------------------+
268 | Reset the timebase.
269 | The previous write to CCR1 sets the timebase source.
270 +-----------------------------------------------------------------*/
275 /*----------------------------------------------------------------*/
276 /* Setup interrupt vectors */
277 /*----------------------------------------------------------------*/
278 mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */
280 mtspr ivor0,r1 /* Critical input */
282 mtspr ivor1,r1 /* Machine check */
284 mtspr ivor2,r1 /* Data storage */
286 mtspr ivor3,r1 /* Instruction storage */
288 mtspr ivor4,r1 /* External interrupt */
290 mtspr ivor5,r1 /* Alignment */
292 mtspr ivor6,r1 /* Program check */
294 mtspr ivor7,r1 /* Floating point unavailable */
296 mtspr ivor8,r1 /* System call */
298 mtspr ivor9,r1 /* Auxiliary Processor unavailable */
300 mtspr ivor10,r1 /* Decrementer */
302 mtspr ivor13,r1 /* Data TLB error */
304 mtspr ivor14,r1 /* Instr TLB error */
306 mtspr ivor15,r1 /* Debug */
308 /*----------------------------------------------------------------*/
309 /* Configure cache regions */
310 /*----------------------------------------------------------------*/
328 /*----------------------------------------------------------------*/
329 /* Cache victim limits */
330 /*----------------------------------------------------------------*/
331 /* floors 0, ceiling max to use the entire cache -- nothing locked
338 /*----------------------------------------------------------------+
339 |Initialize MMUCR[STID] = 0.
340 +-----------------------------------------------------------------*/
347 /*----------------------------------------------------------------*/
348 /* Clear all TLB entries -- TID = 0, TS = 0 */
349 /*----------------------------------------------------------------*/
351 li r1,0x003f /* 64 TLB entries */
353 rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
359 /*----------------------------------------------------------------*/
360 /* TLB entry setup -- step thru tlbtab */
361 /*----------------------------------------------------------------*/
362 #if defined(CONFIG_440SPE)
363 /*----------------------------------------------------------------*/
364 /* We have different TLB tables for revA and rev B of 440SPe */
365 /*----------------------------------------------------------------*/
377 bl tlbtab /* Get tlbtab pointer */
380 li r1,0x003f /* 64 TLB entries max */
387 beq 2f /* 0 marks end */
390 tlbwe r0,r4,0 /* TLB Word 0 */
391 tlbwe r1,r4,1 /* TLB Word 1 */
392 tlbwe r2,r4,2 /* TLB Word 2 */
393 addi r4,r4,1 /* Next TLB */
396 /*----------------------------------------------------------------*/
397 /* Continue from 'normal' start */
398 /*----------------------------------------------------------------*/
401 #if defined(CONFIG_NAND_SPL)
402 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
404 * Enable internal SRAM (only on 440EPx/GRx, 440EP/GR have no OCM)
409 and r1,r1,r2 /* Disable parity check */
412 and r1,r1,r2 /* Disable pwr mgmt */
415 #if defined(CONFIG_440EP)
417 * On 440EP with no internal SRAM, we setup SDRAM very early
418 * and copy the NAND_SPL to SDRAM and jump to it
420 /* Clear Dcache to use as RAM */
421 addis r3,r0,CFG_INIT_RAM_ADDR@h
422 ori r3,r3,CFG_INIT_RAM_ADDR@l
423 addis r4,r0,CFG_INIT_RAM_END@h
424 ori r4,r4,CFG_INIT_RAM_END@l
425 rlwinm. r5,r4,0,27,31
435 /*----------------------------------------------------------------*/
436 /* Setup the stack in internal SRAM */
437 /*----------------------------------------------------------------*/
438 lis r1,CFG_INIT_RAM_ADDR@h
439 ori r1,r1,CFG_INIT_SP_OFFSET@l
442 stwu r0,-4(r1) /* Terminate call chain */
444 stwu r1,-8(r1) /* Save back chain and move SP */
445 lis r0,RESET_VECTOR@h /* Address of reset vector */
446 ori r0,r0, RESET_VECTOR@l
447 stwu r1,-8(r1) /* Save back chain and move SP */
448 stw r0,+12(r1) /* Save return addr (underflow vect) */
452 #endif /* CONFIG_440EP */
455 * Copy SPL from cache into internal SRAM
457 li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
459 lis r2,CFG_NAND_BOOT_SPL_SRC@h
460 ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
461 lis r3,CFG_NAND_BOOT_SPL_DST@h
462 ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
469 * Jump to code in RAM
473 lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
474 ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
483 #endif /* CONFIG_NAND_SPL */
489 mtspr srr1,r0 /* Keep things disabled for now */
493 #endif /* CONFIG_440 */
496 * r3 - 1st arg to board_init(): IMMP pointer
497 * r4 - 2nd arg to board_init(): boot flag
499 #ifndef CONFIG_NAND_SPL
501 .long 0x27051956 /* U-Boot Magic Number */
502 .globl version_string
504 .ascii U_BOOT_VERSION
505 .ascii " (", __DATE__, " - ", __TIME__, ")"
506 .ascii CONFIG_IDENT_STRING, "\0"
508 . = EXC_OFF_SYS_RESET
509 .globl _start_of_vectors
512 /* Critical input. */
513 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
517 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
519 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
520 #endif /* CONFIG_440 */
522 /* Data Storage exception. */
523 STD_EXCEPTION(0x300, DataStorage, UnknownException)
525 /* Instruction Storage exception. */
526 STD_EXCEPTION(0x400, InstStorage, UnknownException)
528 /* External Interrupt exception. */
529 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
531 /* Alignment exception. */
534 EXCEPTION_PROLOG(SRR0, SRR1)
539 addi r3,r1,STACK_FRAME_OVERHEAD
541 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
542 lwz r6,GOT(transfer_to_handler)
546 .long AlignmentException - _start + _START_OFFSET
547 .long int_return - _start + _START_OFFSET
549 /* Program check exception */
552 EXCEPTION_PROLOG(SRR0, SRR1)
553 addi r3,r1,STACK_FRAME_OVERHEAD
555 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
556 lwz r6,GOT(transfer_to_handler)
560 .long ProgramCheckException - _start + _START_OFFSET
561 .long int_return - _start + _START_OFFSET
564 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
565 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
566 STD_EXCEPTION(0xa00, APU, UnknownException)
568 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
571 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
572 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
574 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
575 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
576 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
578 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
580 .globl _end_of_vectors
587 /*****************************************************************************/
588 #if defined(CONFIG_440)
590 /*----------------------------------------------------------------*/
591 /* Clear and set up some registers. */
592 /*----------------------------------------------------------------*/
595 mtspr dec,r0 /* prevent dec exceptions */
596 mtspr tbl,r0 /* prevent fit & wdt exceptions */
598 mtspr tsr,r1 /* clear all timer exception status */
599 mtspr tcr,r0 /* disable all */
600 mtspr esr,r0 /* clear exception syndrome register */
601 mtxer r0 /* clear integer exception register */
603 /*----------------------------------------------------------------*/
604 /* Debug setup -- some (not very good) ice's need an event*/
605 /* to establish control :-( Define CFG_INIT_DBCR to the dbsr */
606 /* value you need in this case 0x8cff 0000 should do the trick */
607 /*----------------------------------------------------------------*/
608 #if defined(CFG_INIT_DBCR)
611 mtspr dbsr,r1 /* Clear all status bits */
612 lis r0,CFG_INIT_DBCR@h
613 ori r0,r0,CFG_INIT_DBCR@l
618 /*----------------------------------------------------------------*/
619 /* Setup the internal SRAM */
620 /*----------------------------------------------------------------*/
623 #ifdef CFG_INIT_RAM_DCACHE
624 /* Clear Dcache to use as RAM */
625 addis r3,r0,CFG_INIT_RAM_ADDR@h
626 ori r3,r3,CFG_INIT_RAM_ADDR@l
627 addis r4,r0,CFG_INIT_RAM_END@h
628 ori r4,r4,CFG_INIT_RAM_END@l
629 rlwinm. r5,r4,0,27,31
641 * Lock the init-ram/stack in d-cache, so that other regions
642 * may use d-cache as well
643 * Note, that this current implementation locks exactly 4k
644 * of d-cache, so please make sure that you don't define a
645 * bigger init-ram area. Take a look at the lwmon5 440EPx
646 * implementation as a reference.
650 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
666 #endif /* CFG_INIT_RAM_DCACHE */
668 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
669 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
670 /* not all PPC's have internal SRAM usable as L2-cache */
671 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
672 mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
678 and r1,r1,r2 /* Disable parity check */
681 and r1,r1,r2 /* Disable pwr mgmt */
684 lis r1,0x8000 /* BAS = 8000_0000 */
685 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
686 ori r1,r1,0x0980 /* first 64k */
687 mtdcr isram0_sb0cr,r1
689 ori r1,r1,0x0980 /* second 64k */
690 mtdcr isram0_sb1cr,r1
692 ori r1,r1, 0x0980 /* third 64k */
693 mtdcr isram0_sb2cr,r1
695 ori r1,r1, 0x0980 /* fourth 64k */
696 mtdcr isram0_sb3cr,r1
697 #elif defined(CONFIG_440SPE)
698 lis r1,0x0000 /* BAS = 0000_0000 */
699 ori r1,r1,0x0984 /* first 64k */
700 mtdcr isram0_sb0cr,r1
702 ori r1,r1,0x0984 /* second 64k */
703 mtdcr isram0_sb1cr,r1
705 ori r1,r1, 0x0984 /* third 64k */
706 mtdcr isram0_sb2cr,r1
708 ori r1,r1, 0x0984 /* fourth 64k */
709 mtdcr isram0_sb3cr,r1
710 #elif defined(CONFIG_440GP)
711 ori r1,r1,0x0380 /* 8k rw */
712 mtdcr isram0_sb0cr,r1
713 mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
715 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
717 /*----------------------------------------------------------------*/
718 /* Setup the stack in internal SRAM */
719 /*----------------------------------------------------------------*/
720 lis r1,CFG_INIT_RAM_ADDR@h
721 ori r1,r1,CFG_INIT_SP_OFFSET@l
724 stwu r0,-4(r1) /* Terminate call chain */
726 stwu r1,-8(r1) /* Save back chain and move SP */
727 lis r0,RESET_VECTOR@h /* Address of reset vector */
728 ori r0,r0, RESET_VECTOR@l
729 stwu r1,-8(r1) /* Save back chain and move SP */
730 stw r0,+12(r1) /* Save return addr (underflow vect) */
732 #ifdef CONFIG_NAND_SPL
733 bl nand_boot /* will not return */
737 bl cpu_init_f /* run low-level CPU init code (from Flash) */
741 #endif /* CONFIG_440 */
743 /*****************************************************************************/
745 /*----------------------------------------------------------------------- */
746 /* Set up some machine state registers. */
747 /*----------------------------------------------------------------------- */
748 addi r0,r0,0x0000 /* initialize r0 to zero */
749 mtspr esr,r0 /* clear Exception Syndrome Reg */
750 mttcr r0 /* timer control register */
751 mtexier r0 /* disable all interrupts */
752 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
753 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
754 mtdbsr r4 /* clear/reset the dbsr */
755 mtexisr r4 /* clear all pending interrupts */
757 mtexier r4 /* enable critical exceptions */
758 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
759 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
760 mtiocr r4 /* since bit not used) & DRC to latch */
761 /* data bus on rising edge of CAS */
762 /*----------------------------------------------------------------------- */
764 /*----------------------------------------------------------------------- */
766 /*----------------------------------------------------------------------- */
767 /* Invalidate i-cache and d-cache TAG arrays. */
768 /*----------------------------------------------------------------------- */
769 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
770 addi r4,0,1024 /* 1/4 of I-cache */
775 addic. r3,r3,-16 /* move back one cache line */
776 bne ..cloop /* loop back to do rest until r3 = 0 */
779 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
780 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
783 /* first copy IOP480 register base address into r3 */
784 addis r3,0,0x5000 /* IOP480 register base address hi */
785 /* ori r3,r3,0x0000 / IOP480 register base address lo */
788 /* use r4 as the working variable */
789 /* turn on CS3 (LOCCTL.7) */
790 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
791 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
792 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
795 #ifdef CONFIG_DASA_SIM
796 /* use r4 as the working variable */
797 /* turn on MA17 (LOCCTL.7) */
798 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
799 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
800 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
803 /* turn on MA16..13 (LCS0BRD.12 = 0) */
804 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
805 andi. r4,r4,0xefff /* make bit 12 = 0 */
806 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
808 /* make sure above stores all comlete before going on */
811 /* last thing, set local init status done bit (DEVINIT.31) */
812 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
813 oris r4,r4,0x8000 /* make bit 31 = 1 */
814 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
816 /* clear all pending interrupts and disable all interrupts */
817 li r4,-1 /* set p1 to 0xffffffff */
818 stw r4,0x1b0(r3) /* clear all pending interrupts */
819 stw r4,0x1b8(r3) /* clear all pending interrupts */
820 li r4,0 /* set r4 to 0 */
821 stw r4,0x1b4(r3) /* disable all interrupts */
822 stw r4,0x1bc(r3) /* disable all interrupts */
824 /* make sure above stores all comlete before going on */
827 /*----------------------------------------------------------------------- */
828 /* Enable two 128MB cachable regions. */
829 /*----------------------------------------------------------------------- */
832 mticcr r1 /* instruction cache */
836 mtdccr r1 /* data cache */
838 addis r1,r0,CFG_INIT_RAM_ADDR@h
839 ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */
840 li r0, 0 /* Make room for stack frame header and */
841 stwu r0, -4(r1) /* clear final stack frame so that */
842 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
844 GET_GOT /* initialize GOT access */
846 bl board_init_f /* run first part of init code (from Flash) */
848 #endif /* CONFIG_IOP480 */
850 /*****************************************************************************/
851 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
852 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
853 defined(CONFIG_405EX) || defined(CONFIG_405)
854 /*----------------------------------------------------------------------- */
855 /* Clear and set up some registers. */
856 /*----------------------------------------------------------------------- */
858 #if !defined(CONFIG_405EX)
862 * On 405EX, completely clearing the SGR leads to PPC hangup
863 * upon PCIe configuration access. The PCIe memory regions
864 * need to be guarded!
871 mtesr r4 /* clear Exception Syndrome Reg */
872 mttcr r4 /* clear Timer Control Reg */
873 mtxer r4 /* clear Fixed-Point Exception Reg */
874 mtevpr r4 /* clear Exception Vector Prefix Reg */
875 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
876 /* dbsr is cleared by setting bits to 1) */
877 mtdbsr r4 /* clear/reset the dbsr */
879 /*----------------------------------------------------------------------- */
880 /* Invalidate I and D caches. Enable I cache for defined memory regions */
881 /* to speed things up. Leave the D cache disabled for now. It will be */
882 /* enabled/left disabled later based on user selected menu options. */
883 /* Be aware that the I cache may be disabled later based on the menu */
884 /* options as well. See miscLib/main.c. */
885 /*----------------------------------------------------------------------- */
889 /*----------------------------------------------------------------------- */
890 /* Enable two 128MB cachable regions. */
891 /*----------------------------------------------------------------------- */
894 mticcr r4 /* instruction cache */
899 mtdccr r4 /* data cache */
901 #if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) || defined(CONFIG_405EX)
902 /*----------------------------------------------------------------------- */
903 /* Tune the speed and size for flash CS0 */
904 /*----------------------------------------------------------------------- */
905 bl ext_bus_cntlr_init
907 #if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
909 * Boards like the Kilauea (405EX) don't have OCM and can't use
910 * DCache for init-ram. So setup stack here directly after the
911 * SDRAM is initialized.
913 lis r1, CFG_INIT_RAM_ADDR@h
914 ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
916 li r0, 0 /* Make room for stack frame header and */
917 stwu r0, -4(r1) /* clear final stack frame so that */
918 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
920 * Set up a dummy frame to store reset vector as return address.
921 * this causes stack underflow to reset board.
923 stwu r1, -8(r1) /* Save back chain and move SP */
924 lis r0, RESET_VECTOR@h /* Address of reset vector */
925 ori r0, r0, RESET_VECTOR@l
926 stwu r1, -8(r1) /* Save back chain and move SP */
927 stw r0, +12(r1) /* Save return addr (underflow vect) */
928 #endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
930 #if defined(CONFIG_405EP)
931 /*----------------------------------------------------------------------- */
932 /* DMA Status, clear to come up clean */
933 /*----------------------------------------------------------------------- */
934 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
938 bl ppc405ep_init /* do ppc405ep specific init */
939 #endif /* CONFIG_405EP */
941 #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
942 #if defined(CONFIG_405EZ)
943 /********************************************************************
944 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
945 *******************************************************************/
947 * We can map the OCM on the PLB3, so map it at
948 * CFG_OCM_DATA_ADDR + 0x8000
950 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
951 ori r3,r3,CFG_OCM_DATA_ADDR@l
952 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
953 mtdcr ocmplb3cr1,r3 /* Set PLB Access */
954 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
955 mtdcr ocmplb3cr2,r3 /* Set PLB Access */
958 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
959 ori r3,r3,CFG_OCM_DATA_ADDR@l
960 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
961 mtdcr ocmdscr1, r3 /* Set Data Side */
962 mtdcr ocmiscr1, r3 /* Set Instruction Side */
963 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
964 mtdcr ocmdscr2, r3 /* Set Data Side */
965 mtdcr ocmiscr2, r3 /* Set Instruction Side */
966 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
970 #else /* CONFIG_405EZ */
971 /********************************************************************
972 * Setup OCM - On Chip Memory
973 *******************************************************************/
977 mfdcr r3, ocmiscntl /* get instr-side IRAM config */
978 mfdcr r4, ocmdscntl /* get data-side IRAM config */
979 and r3, r3, r0 /* disable data-side IRAM */
980 and r4, r4, r0 /* disable data-side IRAM */
981 mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
982 mtdcr ocmdscntl, r4 /* set data-side IRAM config */
985 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
986 ori r3,r3,CFG_OCM_DATA_ADDR@l
988 addis r4, 0, 0xC000 /* OCM data area enabled */
991 #endif /* CONFIG_405EZ */
994 #ifdef CONFIG_NAND_SPL
996 * Copy SPL from cache into internal SRAM
998 li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
1000 lis r2,CFG_NAND_BOOT_SPL_SRC@h
1001 ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
1002 lis r3,CFG_NAND_BOOT_SPL_DST@h
1003 ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
1010 * Jump to code in RAM
1014 lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
1015 ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
1024 #endif /* CONFIG_NAND_SPL */
1026 /*----------------------------------------------------------------------- */
1027 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
1028 /*----------------------------------------------------------------------- */
1029 #ifdef CFG_INIT_DCACHE_CS
1030 /*----------------------------------------------------------------------- */
1031 /* Memory Bank x (nothingness) initialization 1GB+64MEG */
1032 /* used as temporary stack pointer for stage0 */
1033 /*----------------------------------------------------------------------- */
1046 /* turn on data cache for this region */
1050 /* set stack pointer and clear stack to known value */
1052 lis r1,CFG_INIT_RAM_ADDR@h
1053 ori r1,r1,CFG_INIT_SP_OFFSET@l
1055 li r4,2048 /* we store 2048 words to stack */
1058 lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */
1059 ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */
1061 lis r4,0xdead /* we store 0xdeaddead in the stack */
1068 li r0, 0 /* Make room for stack frame header and */
1069 stwu r0, -4(r1) /* clear final stack frame so that */
1070 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
1072 * Set up a dummy frame to store reset vector as return address.
1073 * this causes stack underflow to reset board.
1075 stwu r1, -8(r1) /* Save back chain and move SP */
1076 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1077 ori r0, r0, RESET_VECTOR@l
1078 stwu r1, -8(r1) /* Save back chain and move SP */
1079 stw r0, +12(r1) /* Save return addr (underflow vect) */
1081 #elif defined(CFG_TEMP_STACK_OCM) && \
1082 (defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE))
1087 /* Set up Stack at top of OCM */
1088 lis r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h
1089 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l
1091 /* Set up a zeroized stack frame so that backtrace works right */
1097 * Set up a dummy frame to store reset vector as return address.
1098 * this causes stack underflow to reset board.
1100 stwu r1, -8(r1) /* Save back chain and move SP */
1101 lis r0, RESET_VECTOR@h /* Address of reset vector */
1102 ori r0, r0, RESET_VECTOR@l
1103 stwu r1, -8(r1) /* Save back chain and move SP */
1104 stw r0, +12(r1) /* Save return addr (underflow vect) */
1105 #endif /* CFG_INIT_DCACHE_CS */
1107 /*----------------------------------------------------------------------- */
1108 /* Initialize SDRAM Controller */
1109 /*----------------------------------------------------------------------- */
1112 #ifdef CONFIG_NAND_SPL
1113 bl nand_boot /* will not return */
1115 GET_GOT /* initialize GOT access */
1117 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1119 /* NEVER RETURNS! */
1120 bl board_init_f /* run first part of init code (from Flash) */
1121 #endif /* CONFIG_NAND_SPL */
1123 #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1124 /*----------------------------------------------------------------------- */
1127 #ifndef CONFIG_NAND_SPL
1129 * This code finishes saving the registers to the exception frame
1130 * and jumps to the appropriate handler for the exception.
1131 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1133 .globl transfer_to_handler
1134 transfer_to_handler:
1144 andi. r24,r23,0x3f00 /* get vector offset */
1148 mtspr SPRG2,r22 /* r1 is now kernel sp */
1149 lwz r24,0(r23) /* virtual address of handler */
1150 lwz r23,4(r23) /* where to go when done */
1155 rfi /* jump to handler, enable MMU */
1158 mfmsr r28 /* Disable interrupts */
1162 SYNC /* Some chip revs need this... */
1177 lwz r2,_NIP(r1) /* Restore environment */
1188 mfmsr r28 /* Disable interrupts */
1192 SYNC /* Some chip revs need this... */
1207 lwz r2,_NIP(r1) /* Restore environment */
1219 mfmsr r28 /* Disable interrupts */
1223 SYNC /* Some chip revs need this... */
1238 lwz r2,_NIP(r1) /* Restore environment */
1247 #endif /* CONFIG_440 */
1255 /*------------------------------------------------------------------------------- */
1256 /* Function: out16 */
1257 /* Description: Output 16 bits */
1258 /*------------------------------------------------------------------------------- */
1264 /*------------------------------------------------------------------------------- */
1265 /* Function: out16r */
1266 /* Description: Byte reverse and output 16 bits */
1267 /*------------------------------------------------------------------------------- */
1273 /*------------------------------------------------------------------------------- */
1274 /* Function: out32r */
1275 /* Description: Byte reverse and output 32 bits */
1276 /*------------------------------------------------------------------------------- */
1282 /*------------------------------------------------------------------------------- */
1283 /* Function: in16 */
1284 /* Description: Input 16 bits */
1285 /*------------------------------------------------------------------------------- */
1291 /*------------------------------------------------------------------------------- */
1292 /* Function: in16r */
1293 /* Description: Input 16 bits and byte reverse */
1294 /*------------------------------------------------------------------------------- */
1300 /*------------------------------------------------------------------------------- */
1301 /* Function: in32r */
1302 /* Description: Input 32 bits and byte reverse */
1303 /*------------------------------------------------------------------------------- */
1310 * void relocate_code (addr_sp, gd, addr_moni)
1312 * This "function" does not return, instead it continues in RAM
1313 * after relocating the monitor code.
1317 * r5 = length in bytes
1318 * r6 = cachelinesize
1320 .globl relocate_code
1322 #ifdef CONFIG_4xx_DCACHE
1324 * We need to flush the Init Data before the dcache will be
1334 addi r4,r4,0x200 /* should be enough for init data */
1335 bl flush_dcache_range
1343 #ifdef CFG_INIT_RAM_DCACHE
1345 * Unlock the previously locked d-cache
1349 /* set TFLOOR/NFLOOR to 0 again */
1365 #endif /* CFG_INIT_RAM_DCACHE */
1367 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1368 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1369 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1371 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1372 * to speed up the boot process. Now this cache needs to be disabled.
1374 iccci 0,0 /* Invalidate inst cache */
1375 dccci 0,0 /* Invalidate data cache, now no longer our stack */
1378 #ifdef CFG_TLB_FOR_BOOT_FLASH
1379 addi r1,r0,CFG_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1381 addi r1,r0,0x0000 /* Default TLB entry is #0 */
1383 tlbre r0,r1,0x0002 /* Read contents */
1384 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1385 tlbwe r0,r1,0x0002 /* Save it out */
1389 mr r1, r3 /* Set new stack pointer */
1390 mr r9, r4 /* Save copy of Init Data pointer */
1391 mr r10, r5 /* Save copy of Destination Address */
1393 mr r3, r5 /* Destination Address */
1394 lis r4, CFG_MONITOR_BASE@h /* Source Address */
1395 ori r4, r4, CFG_MONITOR_BASE@l
1396 lwz r5, GOT(__init_end)
1398 li r6, L1_CACHE_BYTES /* Cache Line Size */
1403 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
1409 /* First our own GOT */
1411 /* the the one used by the C code */
1421 beq cr1,4f /* In place copy is not necessary */
1422 beq 7f /* Protect against 0 count */
1441 * Now flush the cache: note that we must start from a cache aligned
1442 * address. Otherwise we might miss one cache line.
1446 beq 7f /* Always flush prefetch queue in any case */
1454 sync /* Wait for all dcbst to complete on bus */
1460 7: sync /* Wait for all icbi to complete on bus */
1464 * We are done. Do not return, instead branch to second part of board
1465 * initialization, now running from RAM.
1468 addi r0, r10, in_ram - _start + _START_OFFSET
1470 blr /* NEVER RETURNS! */
1475 * Relocation Function, r14 point to got2+0x8000
1477 * Adjust got2 pointers, no need to check for 0, this code
1478 * already puts a few entries in the table.
1480 li r0,__got2_entries@sectoff@l
1481 la r3,GOT(_GOT2_TABLE_)
1482 lwz r11,GOT(_GOT2_TABLE_)
1492 * Now adjust the fixups and the pointers to the fixups
1493 * in case we need to move ourselves again.
1495 2: li r0,__fixup_entries@sectoff@l
1496 lwz r3,GOT(_FIXUP_TABLE_)
1510 * Now clear BSS segment
1512 lwz r3,GOT(__bss_start)
1535 mr r3, r9 /* Init Data pointer */
1536 mr r4, r10 /* Destination Address */
1540 * Copy exception vector code to low memory
1543 * r7: source address, r8: end address, r9: target address
1547 lwz r7, GOT(_start_of_vectors)
1548 lwz r8, GOT(_end_of_vectors)
1550 li r9, 0x100 /* reset vector always at 0x100 */
1553 bgelr /* return if r7>=r8 - just in case */
1555 mflr r4 /* save link register */
1565 * relocate `hdlr' and `int_return' entries
1567 li r7, .L_MachineCheck - _start + _START_OFFSET
1568 li r8, Alignment - _start + _START_OFFSET
1571 addi r7, r7, 0x100 /* next exception vector */
1575 li r7, .L_Alignment - _start + _START_OFFSET
1578 li r7, .L_ProgramCheck - _start + _START_OFFSET
1582 li r7, .L_FPUnavailable - _start + _START_OFFSET
1585 li r7, .L_Decrementer - _start + _START_OFFSET
1588 li r7, .L_APU - _start + _START_OFFSET
1591 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1594 li r7, .L_DataTLBError - _start + _START_OFFSET
1596 #else /* CONFIG_440 */
1597 li r7, .L_PIT - _start + _START_OFFSET
1600 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1603 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1605 #endif /* CONFIG_440 */
1607 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1610 #if !defined(CONFIG_440)
1611 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1612 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1613 mtmsr r7 /* change MSR */
1616 b __440_msr_continue
1619 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1620 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1628 mtlr r4 /* restore link register */
1632 * Function: relocate entries for one exception vector
1635 lwz r0, 0(r7) /* hdlr ... */
1636 add r0, r0, r3 /* ... += dest_addr */
1639 lwz r0, 4(r7) /* int_return ... */
1640 add r0, r0, r3 /* ... += dest_addr */
1645 #if defined(CONFIG_440)
1646 /*----------------------------------------------------------------------------+
1648 +----------------------------------------------------------------------------*/
1649 function_prolog(dcbz_area)
1650 rlwinm. r5,r4,0,27,31
1651 rlwinm r5,r4,27,5,31
1660 function_epilog(dcbz_area)
1662 /*----------------------------------------------------------------------------+
1663 | dflush. Assume 32K at vector address is cachable.
1664 +----------------------------------------------------------------------------*/
1665 function_prolog(dflush)
1667 rlwinm r8,r9,0,15,13
1668 rlwinm r8,r8,0,17,15
1689 function_epilog(dflush)
1690 #endif /* CONFIG_440 */
1691 #endif /* CONFIG_NAND_SPL */
1693 /*------------------------------------------------------------------------------- */
1695 /* Description: Input 8 bits */
1696 /*------------------------------------------------------------------------------- */
1702 /*------------------------------------------------------------------------------- */
1703 /* Function: out8 */
1704 /* Description: Output 8 bits */
1705 /*------------------------------------------------------------------------------- */
1711 /*------------------------------------------------------------------------------- */
1712 /* Function: out32 */
1713 /* Description: Output 32 bits */
1714 /*------------------------------------------------------------------------------- */
1720 /*------------------------------------------------------------------------------- */
1721 /* Function: in32 */
1722 /* Description: Input 32 bits */
1723 /*------------------------------------------------------------------------------- */
1729 /**************************************************************************/
1730 /* PPC405EP specific stuff */
1731 /**************************************************************************/
1735 #ifdef CONFIG_BUBINGA
1737 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1738 * function) to support FPGA and NVRAM accesses below.
1741 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1742 ori r3,r3,GPIO0_OSRH@l
1743 lis r4,CFG_GPIO0_OSRH@h
1744 ori r4,r4,CFG_GPIO0_OSRH@l
1747 ori r3,r3,GPIO0_OSRL@l
1748 lis r4,CFG_GPIO0_OSRL@h
1749 ori r4,r4,CFG_GPIO0_OSRL@l
1752 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1753 ori r3,r3,GPIO0_ISR1H@l
1754 lis r4,CFG_GPIO0_ISR1H@h
1755 ori r4,r4,CFG_GPIO0_ISR1H@l
1757 lis r3,GPIO0_ISR1L@h
1758 ori r3,r3,GPIO0_ISR1L@l
1759 lis r4,CFG_GPIO0_ISR1L@h
1760 ori r4,r4,CFG_GPIO0_ISR1L@l
1763 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1764 ori r3,r3,GPIO0_TSRH@l
1765 lis r4,CFG_GPIO0_TSRH@h
1766 ori r4,r4,CFG_GPIO0_TSRH@l
1769 ori r3,r3,GPIO0_TSRL@l
1770 lis r4,CFG_GPIO0_TSRL@h
1771 ori r4,r4,CFG_GPIO0_TSRL@l
1774 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1775 ori r3,r3,GPIO0_TCR@l
1776 lis r4,CFG_GPIO0_TCR@h
1777 ori r4,r4,CFG_GPIO0_TCR@l
1780 li r3,pb1ap /* program EBC bank 1 for RTC access */
1782 lis r3,CFG_EBC_PB1AP@h
1783 ori r3,r3,CFG_EBC_PB1AP@l
1787 lis r3,CFG_EBC_PB1CR@h
1788 ori r3,r3,CFG_EBC_PB1CR@l
1791 li r3,pb1ap /* program EBC bank 1 for RTC access */
1793 lis r3,CFG_EBC_PB1AP@h
1794 ori r3,r3,CFG_EBC_PB1AP@l
1798 lis r3,CFG_EBC_PB1CR@h
1799 ori r3,r3,CFG_EBC_PB1CR@l
1802 li r3,pb4ap /* program EBC bank 4 for FPGA access */
1804 lis r3,CFG_EBC_PB4AP@h
1805 ori r3,r3,CFG_EBC_PB4AP@l
1809 lis r3,CFG_EBC_PB4CR@h
1810 ori r3,r3,CFG_EBC_PB4CR@l
1815 !-----------------------------------------------------------------------
1816 ! Check to see if chip is in bypass mode.
1817 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1818 ! CPU reset Otherwise, skip this step and keep going.
1819 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1820 ! will not be fast enough for the SDRAM (min 66MHz)
1821 !-----------------------------------------------------------------------
1823 mfdcr r5, CPC0_PLLMR1
1824 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1827 beq pll_done /* if SSCS =b'1' then PLL has */
1828 /* already been set */
1829 /* and CPU has been reset */
1830 /* so skip to next section */
1832 #ifdef CONFIG_BUBINGA
1834 !-----------------------------------------------------------------------
1835 ! Read NVRAM to get value to write in PLLMR.
1836 ! If value has not been correctly saved, write default value
1837 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1838 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1840 ! WARNING: This code assumes the first three words in the nvram_t
1841 ! structure in openbios.h. Changing the beginning of
1842 ! the structure will break this code.
1844 !-----------------------------------------------------------------------
1846 addis r3,0,NVRAM_BASE@h
1847 addi r3,r3,NVRAM_BASE@l
1850 addis r5,0,NVRVFY1@h
1851 addi r5,r5,NVRVFY1@l
1852 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1856 addis r5,0,NVRVFY2@h
1857 addi r5,r5,NVRVFY2@l
1858 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1860 addi r3,r3,8 /* Skip over conf_size */
1861 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1862 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1863 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1864 cmpi cr0,0,r5,1 /* See if PLL is locked */
1867 #endif /* CONFIG_BUBINGA */
1871 andi. r5, r4, CPC0_BOOT_SEP@l
1872 bne strap_1 /* serial eeprom present */
1873 addis r5,0,CPLD_REG0_ADDR@h
1874 ori r5,r5,CPLD_REG0_ADDR@l
1877 #endif /* CONFIG_TAIHU */
1879 #if defined(CONFIG_ZEUS)
1881 andi. r5, r4, CPC0_BOOT_SEP@l
1882 bne strap_1 /* serial eeprom present */
1889 mfdcr r3, CPC0_PLLMR0
1890 mfdcr r4, CPC0_PLLMR1
1894 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1895 ori r3,r3,PLLMR0_DEFAULT@l /* */
1896 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1897 ori r4,r4,PLLMR1_DEFAULT@l /* */
1902 addis r3,0,PLLMR0_DEFAULT_PCI66@h
1903 ori r3,r3,PLLMR0_DEFAULT_PCI66@l
1904 addis r4,0,PLLMR1_DEFAULT_PCI66@h
1905 ori r4,r4,PLLMR1_DEFAULT_PCI66@l
1908 mfdcr r3, CPC0_PLLMR0
1909 mfdcr r4, CPC0_PLLMR1
1910 #endif /* CONFIG_TAIHU */
1913 b pll_write /* Write the CPC0_PLLMR with new value */
1917 !-----------------------------------------------------------------------
1918 ! Clear Soft Reset Register
1919 ! This is needed to enable PCI if not booting from serial EPROM
1920 !-----------------------------------------------------------------------
1930 blr /* return to main code */
1933 !-----------------------------------------------------------------------------
1934 ! Function: pll_write
1935 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1937 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
1939 ! 3. Clock dividers are set while PLL is held in reset and bypassed
1940 ! 4. PLL Reset is cleared
1941 ! 5. Wait 100us for PLL to lock
1942 ! 6. A core reset is performed
1943 ! Input: r3 = Value to write to CPC0_PLLMR0
1944 ! Input: r4 = Value to write to CPC0_PLLMR1
1946 !-----------------------------------------------------------------------------
1951 ori r5,r5,0x0101 /* Stop the UART clocks */
1952 mtdcr CPC0_UCR,r5 /* Before changing PLL */
1954 mfdcr r5, CPC0_PLLMR1
1955 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
1956 mtdcr CPC0_PLLMR1,r5
1957 oris r5,r5,0x4000 /* Set PLL Reset */
1958 mtdcr CPC0_PLLMR1,r5
1960 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
1961 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
1962 oris r5,r5,0x4000 /* Set PLL Reset */
1963 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
1964 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
1965 mtdcr CPC0_PLLMR1,r5
1968 ! Wait min of 100us for PLL to lock.
1969 ! See CMOS 27E databook for more info.
1970 ! At 200MHz, that means waiting 20,000 instructions
1972 addi r3,0,20000 /* 2000 = 0x4e20 */
1977 oris r5,r5,0x8000 /* Enable PLL */
1978 mtdcr CPC0_PLLMR1,r5 /* Engage */
1981 * Reset CPU to guarantee timings are OK
1982 * Not sure if this is needed...
1985 mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
1986 /* execution will continue from the poweron */
1987 /* vector of 0xfffffffc */
1988 #endif /* CONFIG_405EP */
1990 #if defined(CONFIG_440)
1991 /*----------------------------------------------------------------------------+
1993 +----------------------------------------------------------------------------*/
1994 function_prolog(mttlb3)
1997 function_epilog(mttlb3)
1999 /*----------------------------------------------------------------------------+
2001 +----------------------------------------------------------------------------*/
2002 function_prolog(mftlb3)
2005 function_epilog(mftlb3)
2007 /*----------------------------------------------------------------------------+
2009 +----------------------------------------------------------------------------*/
2010 function_prolog(mttlb2)
2013 function_epilog(mttlb2)
2015 /*----------------------------------------------------------------------------+
2017 +----------------------------------------------------------------------------*/
2018 function_prolog(mftlb2)
2021 function_epilog(mftlb2)
2023 /*----------------------------------------------------------------------------+
2025 +----------------------------------------------------------------------------*/
2026 function_prolog(mttlb1)
2029 function_epilog(mttlb1)
2031 /*----------------------------------------------------------------------------+
2033 +----------------------------------------------------------------------------*/
2034 function_prolog(mftlb1)
2037 function_epilog(mftlb1)
2038 #endif /* CONFIG_440 */