2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 /*------------------------------------------------------------------------------+
27 * This source code has been made available to you by IBM on an AS-IS
28 * basis. Anyone receiving this source is licensed under IBM
29 * copyrights to use it in any way he or she deems fit, including
30 * copying it, modifying it, compiling it, and redistributing it either
31 * with or without modifications. No license under IBM patents or
32 * patent applications is to be implied by the copyright license.
34 * Any user of this software should understand that IBM cannot provide
35 * technical support for this software and will not be responsible for
36 * any consequences resulting from the use of this software.
38 * Any person who transfers this source code or any derivative work
39 * must include the IBM copyright notice, this paragraph, and the
40 * preceding two paragraphs in the transferred software.
42 * COPYRIGHT I B M CORPORATION 1995
43 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
44 *-------------------------------------------------------------------------------
47 /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
50 * The processor starts at 0xfffffffc and the code is executed
52 * in memory, but as long we don't jump around before relocating.
53 * board_init lies at a quite high address and when the cpu has
54 * jumped there, everything is ok.
55 * This works because the cpu gives the FLASH (CS0) the whole
56 * address space at startup, and board_init lies as a echo of
57 * the flash somewhere up there in the memorymap.
59 * board_init will change CS0 to be positioned at the correct
60 * address and (s)dram will be positioned at address 0
66 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
68 #include <ppc_asm.tmpl>
71 #include <asm/cache.h>
74 #ifndef CONFIG_IDENT_STRING
75 #define CONFIG_IDENT_STRING ""
78 #ifdef CFG_INIT_DCACHE_CS
79 # if (CFG_INIT_DCACHE_CS == 0)
83 # if (CFG_INIT_DCACHE_CS == 1)
87 # if (CFG_INIT_DCACHE_CS == 2)
91 # if (CFG_INIT_DCACHE_CS == 3)
95 # if (CFG_INIT_DCACHE_CS == 4)
99 # if (CFG_INIT_DCACHE_CS == 5)
103 # if (CFG_INIT_DCACHE_CS == 6)
107 # if (CFG_INIT_DCACHE_CS == 7)
111 #endif /* CFG_INIT_DCACHE_CS */
113 #define function_prolog(func_name) .text; \
117 #define function_epilog(func_name) .type func_name,@function; \
118 .size func_name,.-func_name
120 /* We don't want the MMU yet.
123 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
126 .extern ext_bus_cntlr_init
128 #ifdef CONFIG_NAND_U_BOOT
129 .extern reconfig_tlb0
133 * Set up GOT: Global Offset Table
135 * Use r14 to access the GOT
137 #if !defined(CONFIG_NAND_SPL)
139 GOT_ENTRY(_GOT2_TABLE_)
140 GOT_ENTRY(_FIXUP_TABLE_)
143 GOT_ENTRY(_start_of_vectors)
144 GOT_ENTRY(_end_of_vectors)
145 GOT_ENTRY(transfer_to_handler)
147 GOT_ENTRY(__init_end)
149 GOT_ENTRY(__bss_start)
151 #endif /* CONFIG_NAND_SPL */
153 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
155 * NAND U-Boot image is started from offset 0
158 #if defined(CONFIG_440)
162 bl cpu_init_f /* run low-level CPU init code (from Flash) */
167 * 440 Startup -- on reset only the top 4k of the effective
168 * address space is mapped in by an entry in the instruction
169 * and data shadow TLB. The .bootpg section is located in the
170 * top 4k & does only what's necessary to map in the the rest
171 * of the boot rom. Once the boot rom is mapped in we can
172 * proceed with normal startup.
174 * NOTE: CS0 only covers the top 2MB of the effective address
178 #if defined(CONFIG_440)
179 #if !defined(CONFIG_NAND_SPL)
180 .section .bootpg,"ax"
184 /**************************************************************************/
186 /*--------------------------------------------------------------------+
187 | 440EPX BUP Change - Hardware team request
188 +--------------------------------------------------------------------*/
189 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
194 /*----------------------------------------------------------------+
195 | Core bug fix. Clear the esr
196 +-----------------------------------------------------------------*/
199 /*----------------------------------------------------------------*/
200 /* Clear and set up some registers. */
201 /*----------------------------------------------------------------*/
202 iccci r0,r0 /* NOTE: operands not used for 440 */
203 dccci r0,r0 /* NOTE: operands not used for 440 */
210 /* NOTE: 440GX adds machine check status regs */
211 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
218 /*----------------------------------------------------------------*/
220 /*----------------------------------------------------------------*/
221 /* Disable store gathering & broadcast, guarantee inst/data
222 * cache block touch, force load/store alignment
223 * (see errata 1.12: 440_33)
225 lis r1,0x0030 /* store gathering & broadcast disable */
226 ori r1,r1,0x6000 /* cache touch */
229 /*----------------------------------------------------------------*/
230 /* Initialize debug */
231 /*----------------------------------------------------------------*/
233 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
234 bne skip_debug_init /* if set, don't clear debug register */
247 mtspr dbsr,r1 /* Clear all valid bits */
250 #if defined (CONFIG_440SPE)
251 /*----------------------------------------------------------------+
252 | Initialize Core Configuration Reg1.
253 | a. ICDPEI: Record even parity. Normal operation.
254 | b. ICTPEI: Record even parity. Normal operation.
255 | c. DCTPEI: Record even parity. Normal operation.
256 | d. DCDPEI: Record even parity. Normal operation.
257 | e. DCUPEI: Record even parity. Normal operation.
258 | f. DCMPEI: Record even parity. Normal operation.
259 | g. FCOM: Normal operation
260 | h. MMUPEI: Record even parity. Normal operation.
261 | i. FFF: Flush only as much data as necessary.
262 | j. TCS: Timebase increments from CPU clock.
263 +-----------------------------------------------------------------*/
267 /*----------------------------------------------------------------+
268 | Reset the timebase.
269 | The previous write to CCR1 sets the timebase source.
270 +-----------------------------------------------------------------*/
275 /*----------------------------------------------------------------*/
276 /* Setup interrupt vectors */
277 /*----------------------------------------------------------------*/
278 mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */
280 mtspr ivor0,r1 /* Critical input */
282 mtspr ivor1,r1 /* Machine check */
284 mtspr ivor2,r1 /* Data storage */
286 mtspr ivor3,r1 /* Instruction storage */
288 mtspr ivor4,r1 /* External interrupt */
290 mtspr ivor5,r1 /* Alignment */
292 mtspr ivor6,r1 /* Program check */
294 mtspr ivor7,r1 /* Floating point unavailable */
296 mtspr ivor8,r1 /* System call */
298 mtspr ivor9,r1 /* Auxiliary Processor unavailable */
300 mtspr ivor10,r1 /* Decrementer */
302 mtspr ivor13,r1 /* Data TLB error */
304 mtspr ivor14,r1 /* Instr TLB error */
306 mtspr ivor15,r1 /* Debug */
308 /*----------------------------------------------------------------*/
309 /* Configure cache regions */
310 /*----------------------------------------------------------------*/
328 /*----------------------------------------------------------------*/
329 /* Cache victim limits */
330 /*----------------------------------------------------------------*/
331 /* floors 0, ceiling max to use the entire cache -- nothing locked
338 /*----------------------------------------------------------------+
339 |Initialize MMUCR[STID] = 0.
340 +-----------------------------------------------------------------*/
347 /*----------------------------------------------------------------*/
348 /* Clear all TLB entries -- TID = 0, TS = 0 */
349 /*----------------------------------------------------------------*/
351 li r1,0x003f /* 64 TLB entries */
353 rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
359 /*----------------------------------------------------------------*/
360 /* TLB entry setup -- step thru tlbtab */
361 /*----------------------------------------------------------------*/
362 #if defined(CONFIG_440SPE)
363 /*----------------------------------------------------------------*/
364 /* We have different TLB tables for revA and rev B of 440SPe */
365 /*----------------------------------------------------------------*/
377 bl tlbtab /* Get tlbtab pointer */
380 li r1,0x003f /* 64 TLB entries max */
387 beq 2f /* 0 marks end */
390 tlbwe r0,r4,0 /* TLB Word 0 */
391 tlbwe r1,r4,1 /* TLB Word 1 */
392 tlbwe r2,r4,2 /* TLB Word 2 */
393 addi r4,r4,1 /* Next TLB */
396 /*----------------------------------------------------------------*/
397 /* Continue from 'normal' start */
398 /*----------------------------------------------------------------*/
401 #if defined(CONFIG_NAND_SPL)
402 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
404 * Enable internal SRAM (only on 440EPx/GRx, 440EP/GR have no OCM)
409 and r1,r1,r2 /* Disable parity check */
412 and r1,r1,r2 /* Disable pwr mgmt */
415 #if defined(CONFIG_440EP)
417 * On 440EP with no internal SRAM, we setup SDRAM very early
418 * and copy the NAND_SPL to SDRAM and jump to it
420 /* Clear Dcache to use as RAM */
421 addis r3,r0,CFG_INIT_RAM_ADDR@h
422 ori r3,r3,CFG_INIT_RAM_ADDR@l
423 addis r4,r0,CFG_INIT_RAM_END@h
424 ori r4,r4,CFG_INIT_RAM_END@l
425 rlwinm. r5,r4,0,27,31
435 /*----------------------------------------------------------------*/
436 /* Setup the stack in internal SRAM */
437 /*----------------------------------------------------------------*/
438 lis r1,CFG_INIT_RAM_ADDR@h
439 ori r1,r1,CFG_INIT_SP_OFFSET@l
442 stwu r0,-4(r1) /* Terminate call chain */
444 stwu r1,-8(r1) /* Save back chain and move SP */
445 lis r0,RESET_VECTOR@h /* Address of reset vector */
446 ori r0,r0, RESET_VECTOR@l
447 stwu r1,-8(r1) /* Save back chain and move SP */
448 stw r0,+12(r1) /* Save return addr (underflow vect) */
452 #endif /* CONFIG_440EP */
455 * Copy SPL from cache into internal SRAM
457 li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
459 lis r2,CFG_NAND_BOOT_SPL_SRC@h
460 ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
461 lis r3,CFG_NAND_BOOT_SPL_DST@h
462 ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
469 * Jump to code in RAM
473 lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
474 ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
483 #endif /* CONFIG_NAND_SPL */
489 mtspr srr1,r0 /* Keep things disabled for now */
493 #endif /* CONFIG_440 */
496 * r3 - 1st arg to board_init(): IMMP pointer
497 * r4 - 2nd arg to board_init(): boot flag
499 #ifndef CONFIG_NAND_SPL
501 .long 0x27051956 /* U-Boot Magic Number */
502 .globl version_string
504 .ascii U_BOOT_VERSION
505 .ascii " (", __DATE__, " - ", __TIME__, ")"
506 .ascii CONFIG_IDENT_STRING, "\0"
508 . = EXC_OFF_SYS_RESET
509 .globl _start_of_vectors
512 /* Critical input. */
513 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
517 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
519 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
520 #endif /* CONFIG_440 */
522 /* Data Storage exception. */
523 STD_EXCEPTION(0x300, DataStorage, UnknownException)
525 /* Instruction Storage exception. */
526 STD_EXCEPTION(0x400, InstStorage, UnknownException)
528 /* External Interrupt exception. */
529 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
531 /* Alignment exception. */
534 EXCEPTION_PROLOG(SRR0, SRR1)
539 addi r3,r1,STACK_FRAME_OVERHEAD
541 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
542 lwz r6,GOT(transfer_to_handler)
546 .long AlignmentException - _start + _START_OFFSET
547 .long int_return - _start + _START_OFFSET
549 /* Program check exception */
552 EXCEPTION_PROLOG(SRR0, SRR1)
553 addi r3,r1,STACK_FRAME_OVERHEAD
555 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
556 lwz r6,GOT(transfer_to_handler)
560 .long ProgramCheckException - _start + _START_OFFSET
561 .long int_return - _start + _START_OFFSET
564 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
565 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
566 STD_EXCEPTION(0xa00, APU, UnknownException)
568 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
571 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
572 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
574 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
575 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
576 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
578 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
580 .globl _end_of_vectors
587 /*****************************************************************************/
588 #if defined(CONFIG_440)
590 /*----------------------------------------------------------------*/
591 /* Clear and set up some registers. */
592 /*----------------------------------------------------------------*/
595 mtspr dec,r0 /* prevent dec exceptions */
596 mtspr tbl,r0 /* prevent fit & wdt exceptions */
598 mtspr tsr,r1 /* clear all timer exception status */
599 mtspr tcr,r0 /* disable all */
600 mtspr esr,r0 /* clear exception syndrome register */
601 mtxer r0 /* clear integer exception register */
603 /*----------------------------------------------------------------*/
604 /* Debug setup -- some (not very good) ice's need an event*/
605 /* to establish control :-( Define CFG_INIT_DBCR to the dbsr */
606 /* value you need in this case 0x8cff 0000 should do the trick */
607 /*----------------------------------------------------------------*/
608 #if defined(CFG_INIT_DBCR)
611 mtspr dbsr,r1 /* Clear all status bits */
612 lis r0,CFG_INIT_DBCR@h
613 ori r0,r0,CFG_INIT_DBCR@l
618 /*----------------------------------------------------------------*/
619 /* Setup the internal SRAM */
620 /*----------------------------------------------------------------*/
623 #ifdef CFG_INIT_RAM_DCACHE
624 /* Clear Dcache to use as RAM */
625 addis r3,r0,CFG_INIT_RAM_ADDR@h
626 ori r3,r3,CFG_INIT_RAM_ADDR@l
627 addis r4,r0,CFG_INIT_RAM_END@h
628 ori r4,r4,CFG_INIT_RAM_END@l
629 rlwinm. r5,r4,0,27,31
639 #endif /* CFG_INIT_RAM_DCACHE */
641 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
642 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
643 /* not all PPC's have internal SRAM usable as L2-cache */
644 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
645 mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
651 and r1,r1,r2 /* Disable parity check */
654 and r1,r1,r2 /* Disable pwr mgmt */
657 lis r1,0x8000 /* BAS = 8000_0000 */
658 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
659 ori r1,r1,0x0980 /* first 64k */
660 mtdcr isram0_sb0cr,r1
662 ori r1,r1,0x0980 /* second 64k */
663 mtdcr isram0_sb1cr,r1
665 ori r1,r1, 0x0980 /* third 64k */
666 mtdcr isram0_sb2cr,r1
668 ori r1,r1, 0x0980 /* fourth 64k */
669 mtdcr isram0_sb3cr,r1
670 #elif defined(CONFIG_440SPE)
671 lis r1,0x0000 /* BAS = 0000_0000 */
672 ori r1,r1,0x0984 /* first 64k */
673 mtdcr isram0_sb0cr,r1
675 ori r1,r1,0x0984 /* second 64k */
676 mtdcr isram0_sb1cr,r1
678 ori r1,r1, 0x0984 /* third 64k */
679 mtdcr isram0_sb2cr,r1
681 ori r1,r1, 0x0984 /* fourth 64k */
682 mtdcr isram0_sb3cr,r1
683 #elif defined(CONFIG_440GP)
684 ori r1,r1,0x0380 /* 8k rw */
685 mtdcr isram0_sb0cr,r1
686 mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
688 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
690 /*----------------------------------------------------------------*/
691 /* Setup the stack in internal SRAM */
692 /*----------------------------------------------------------------*/
693 lis r1,CFG_INIT_RAM_ADDR@h
694 ori r1,r1,CFG_INIT_SP_OFFSET@l
697 stwu r0,-4(r1) /* Terminate call chain */
699 stwu r1,-8(r1) /* Save back chain and move SP */
700 lis r0,RESET_VECTOR@h /* Address of reset vector */
701 ori r0,r0, RESET_VECTOR@l
702 stwu r1,-8(r1) /* Save back chain and move SP */
703 stw r0,+12(r1) /* Save return addr (underflow vect) */
705 #ifdef CONFIG_NAND_SPL
706 bl nand_boot /* will not return */
710 bl cpu_init_f /* run low-level CPU init code (from Flash) */
714 #endif /* CONFIG_440 */
716 /*****************************************************************************/
718 /*----------------------------------------------------------------------- */
719 /* Set up some machine state registers. */
720 /*----------------------------------------------------------------------- */
721 addi r0,r0,0x0000 /* initialize r0 to zero */
722 mtspr esr,r0 /* clear Exception Syndrome Reg */
723 mttcr r0 /* timer control register */
724 mtexier r0 /* disable all interrupts */
725 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
726 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
727 mtdbsr r4 /* clear/reset the dbsr */
728 mtexisr r4 /* clear all pending interrupts */
730 mtexier r4 /* enable critical exceptions */
731 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
732 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
733 mtiocr r4 /* since bit not used) & DRC to latch */
734 /* data bus on rising edge of CAS */
735 /*----------------------------------------------------------------------- */
737 /*----------------------------------------------------------------------- */
739 /*----------------------------------------------------------------------- */
740 /* Invalidate i-cache and d-cache TAG arrays. */
741 /*----------------------------------------------------------------------- */
742 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
743 addi r4,0,1024 /* 1/4 of I-cache */
748 addic. r3,r3,-16 /* move back one cache line */
749 bne ..cloop /* loop back to do rest until r3 = 0 */
752 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
753 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
756 /* first copy IOP480 register base address into r3 */
757 addis r3,0,0x5000 /* IOP480 register base address hi */
758 /* ori r3,r3,0x0000 / IOP480 register base address lo */
761 /* use r4 as the working variable */
762 /* turn on CS3 (LOCCTL.7) */
763 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
764 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
765 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
768 #ifdef CONFIG_DASA_SIM
769 /* use r4 as the working variable */
770 /* turn on MA17 (LOCCTL.7) */
771 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
772 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
773 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
776 /* turn on MA16..13 (LCS0BRD.12 = 0) */
777 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
778 andi. r4,r4,0xefff /* make bit 12 = 0 */
779 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
781 /* make sure above stores all comlete before going on */
784 /* last thing, set local init status done bit (DEVINIT.31) */
785 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
786 oris r4,r4,0x8000 /* make bit 31 = 1 */
787 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
789 /* clear all pending interrupts and disable all interrupts */
790 li r4,-1 /* set p1 to 0xffffffff */
791 stw r4,0x1b0(r3) /* clear all pending interrupts */
792 stw r4,0x1b8(r3) /* clear all pending interrupts */
793 li r4,0 /* set r4 to 0 */
794 stw r4,0x1b4(r3) /* disable all interrupts */
795 stw r4,0x1bc(r3) /* disable all interrupts */
797 /* make sure above stores all comlete before going on */
800 /*----------------------------------------------------------------------- */
801 /* Enable two 128MB cachable regions. */
802 /*----------------------------------------------------------------------- */
805 mticcr r1 /* instruction cache */
809 mtdccr r1 /* data cache */
811 addis r1,r0,CFG_INIT_RAM_ADDR@h
812 ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */
813 li r0, 0 /* Make room for stack frame header and */
814 stwu r0, -4(r1) /* clear final stack frame so that */
815 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
817 GET_GOT /* initialize GOT access */
819 bl board_init_f /* run first part of init code (from Flash) */
821 #endif /* CONFIG_IOP480 */
823 /*****************************************************************************/
824 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
825 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
827 /*----------------------------------------------------------------------- */
828 /* Clear and set up some registers. */
829 /*----------------------------------------------------------------------- */
833 mtesr r4 /* clear Exception Syndrome Reg */
834 mttcr r4 /* clear Timer Control Reg */
835 mtxer r4 /* clear Fixed-Point Exception Reg */
836 mtevpr r4 /* clear Exception Vector Prefix Reg */
837 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
838 /* dbsr is cleared by setting bits to 1) */
839 mtdbsr r4 /* clear/reset the dbsr */
841 /*----------------------------------------------------------------------- */
842 /* Invalidate I and D caches. Enable I cache for defined memory regions */
843 /* to speed things up. Leave the D cache disabled for now. It will be */
844 /* enabled/left disabled later based on user selected menu options. */
845 /* Be aware that the I cache may be disabled later based on the menu */
846 /* options as well. See miscLib/main.c. */
847 /*----------------------------------------------------------------------- */
851 /*----------------------------------------------------------------------- */
852 /* Enable two 128MB cachable regions. */
853 /*----------------------------------------------------------------------- */
856 mticcr r4 /* instruction cache */
861 mtdccr r4 /* data cache */
863 #if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
864 /*----------------------------------------------------------------------- */
865 /* Tune the speed and size for flash CS0 */
866 /*----------------------------------------------------------------------- */
867 bl ext_bus_cntlr_init
870 #if defined(CONFIG_405EP)
871 /*----------------------------------------------------------------------- */
872 /* DMA Status, clear to come up clean */
873 /*----------------------------------------------------------------------- */
874 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
878 bl ppc405ep_init /* do ppc405ep specific init */
879 #endif /* CONFIG_405EP */
881 #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
882 #if defined(CONFIG_405EZ)
883 /********************************************************************
884 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
885 *******************************************************************/
887 * We can map the OCM on the PLB3, so map it at
888 * CFG_OCM_DATA_ADDR + 0x8000
890 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
891 ori r3,r3,CFG_OCM_DATA_ADDR@l
892 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
893 mtdcr ocmplb3cr1,r3 /* Set PLB Access */
894 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
895 mtdcr ocmplb3cr2,r3 /* Set PLB Access */
898 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
899 ori r3,r3,CFG_OCM_DATA_ADDR@l
900 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
901 mtdcr ocmdscr1, r3 /* Set Data Side */
902 mtdcr ocmiscr1, r3 /* Set Instruction Side */
903 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
904 mtdcr ocmdscr2, r3 /* Set Data Side */
905 mtdcr ocmiscr2, r3 /* Set Instruction Side */
906 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
910 #else /* CONFIG_405EZ */
911 /********************************************************************
912 * Setup OCM - On Chip Memory
913 *******************************************************************/
917 mfdcr r3, ocmiscntl /* get instr-side IRAM config */
918 mfdcr r4, ocmdscntl /* get data-side IRAM config */
919 and r3, r3, r0 /* disable data-side IRAM */
920 and r4, r4, r0 /* disable data-side IRAM */
921 mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
922 mtdcr ocmdscntl, r4 /* set data-side IRAM config */
925 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
926 ori r3,r3,CFG_OCM_DATA_ADDR@l
928 addis r4, 0, 0xC000 /* OCM data area enabled */
931 #endif /* CONFIG_405EZ */
934 #ifdef CONFIG_NAND_SPL
936 * Copy SPL from cache into internal SRAM
938 li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
940 lis r2,CFG_NAND_BOOT_SPL_SRC@h
941 ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
942 lis r3,CFG_NAND_BOOT_SPL_DST@h
943 ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
950 * Jump to code in RAM
954 lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
955 ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
964 #endif /* CONFIG_NAND_SPL */
966 /*----------------------------------------------------------------------- */
967 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
968 /*----------------------------------------------------------------------- */
969 #ifdef CFG_INIT_DCACHE_CS
970 /*----------------------------------------------------------------------- */
971 /* Memory Bank x (nothingness) initialization 1GB+64MEG */
972 /* used as temporary stack pointer for stage0 */
973 /*----------------------------------------------------------------------- */
986 /* turn on data chache for this region */
990 /* set stack pointer and clear stack to known value */
992 lis r1,CFG_INIT_RAM_ADDR@h
993 ori r1,r1,CFG_INIT_SP_OFFSET@l
995 li r4,2048 /* we store 2048 words to stack */
998 lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */
999 ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */
1001 lis r4,0xdead /* we store 0xdeaddead in the stack */
1008 li r0, 0 /* Make room for stack frame header and */
1009 stwu r0, -4(r1) /* clear final stack frame so that */
1010 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
1012 * Set up a dummy frame to store reset vector as return address.
1013 * this causes stack underflow to reset board.
1015 stwu r1, -8(r1) /* Save back chain and move SP */
1016 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1017 ori r0, r0, RESET_VECTOR@l
1018 stwu r1, -8(r1) /* Save back chain and move SP */
1019 stw r0, +12(r1) /* Save return addr (underflow vect) */
1021 #elif defined(CFG_TEMP_STACK_OCM) && \
1022 (defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE))
1027 /* Set up Stack at top of OCM */
1028 lis r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h
1029 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l
1031 /* Set up a zeroized stack frame so that backtrace works right */
1037 * Set up a dummy frame to store reset vector as return address.
1038 * this causes stack underflow to reset board.
1040 stwu r1, -8(r1) /* Save back chain and move SP */
1041 lis r0, RESET_VECTOR@h /* Address of reset vector */
1042 ori r0, r0, RESET_VECTOR@l
1043 stwu r1, -8(r1) /* Save back chain and move SP */
1044 stw r0, +12(r1) /* Save return addr (underflow vect) */
1045 #endif /* CFG_INIT_DCACHE_CS */
1047 /*----------------------------------------------------------------------- */
1048 /* Initialize SDRAM Controller */
1049 /*----------------------------------------------------------------------- */
1053 * Setup temporary stack pointer only for boards
1054 * that do not use SDRAM SPD I2C stuff since it
1055 * is already initialized to use DCACHE or OCM
1058 #if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
1059 lis r1, CFG_INIT_RAM_ADDR@h
1060 ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
1062 li r0, 0 /* Make room for stack frame header and */
1063 stwu r0, -4(r1) /* clear final stack frame so that */
1064 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
1066 * Set up a dummy frame to store reset vector as return address.
1067 * this causes stack underflow to reset board.
1069 stwu r1, -8(r1) /* Save back chain and move SP */
1070 lis r0, RESET_VECTOR@h /* Address of reset vector */
1071 ori r0, r0, RESET_VECTOR@l
1072 stwu r1, -8(r1) /* Save back chain and move SP */
1073 stw r0, +12(r1) /* Save return addr (underflow vect) */
1074 #endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
1076 #ifdef CONFIG_NAND_SPL
1077 bl nand_boot /* will not return */
1079 GET_GOT /* initialize GOT access */
1081 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1083 /* NEVER RETURNS! */
1084 bl board_init_f /* run first part of init code (from Flash) */
1085 #endif /* CONFIG_NAND_SPL */
1087 #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1088 /*----------------------------------------------------------------------- */
1091 #ifndef CONFIG_NAND_SPL
1093 * This code finishes saving the registers to the exception frame
1094 * and jumps to the appropriate handler for the exception.
1095 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1097 .globl transfer_to_handler
1098 transfer_to_handler:
1108 andi. r24,r23,0x3f00 /* get vector offset */
1112 mtspr SPRG2,r22 /* r1 is now kernel sp */
1113 lwz r24,0(r23) /* virtual address of handler */
1114 lwz r23,4(r23) /* where to go when done */
1119 rfi /* jump to handler, enable MMU */
1122 mfmsr r28 /* Disable interrupts */
1126 SYNC /* Some chip revs need this... */
1141 lwz r2,_NIP(r1) /* Restore environment */
1152 mfmsr r28 /* Disable interrupts */
1156 SYNC /* Some chip revs need this... */
1171 lwz r2,_NIP(r1) /* Restore environment */
1183 mfmsr r28 /* Disable interrupts */
1187 SYNC /* Some chip revs need this... */
1202 lwz r2,_NIP(r1) /* Restore environment */
1211 #endif /* CONFIG_440 */
1217 * NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM,
1218 * although for some cache-ralated calls stubs have to be provided to satisfy
1219 * symbols resolution.
1220 * Icache-related functions are used in POST framework.
1224 .globl dcache_disable
1225 .globl icache_disable
1226 .globl icache_enable
1232 .globl dcache_status
1233 .globl icache_status
1240 addis r9,r0,0x0002 /* set mask for EE and CE msr bits */
1242 mfmsr r12 /* save msr */
1244 mtmsr r9 /* disable EE and CE */
1245 addi r10,r0,0x0001 /* enable data cache for unused memory */
1246 mfdccr r9 /* region 0xF8000000-0xFFFFFFFF via */
1247 or r10,r10,r9 /* bit 31 in dccr */
1250 /* do loop for # of congruence classes. */
1251 lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */
1252 ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
1253 lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
1254 ori r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
1256 addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
1257 add r11,r10,r11 /* add to get to other side of cache line */
1258 ..flush_dcache_loop:
1259 lwz r3,0(r10) /* least recently used side */
1260 lwz r3,0(r11) /* the other side */
1261 dccci r0,r11 /* invalidate both sides */
1262 addi r10,r10,CFG_CACHELINE_SIZE /* bump to next line */
1263 addi r11,r11,CFG_CACHELINE_SIZE /* bump to next line */
1264 bdnz ..flush_dcache_loop
1265 sync /* allow memory access to complete */
1266 mtdccr r9 /* restore dccr */
1267 mtmsr r12 /* restore msr */
1270 .globl icache_enable
1273 bl invalidate_icache
1276 addis r3,r0, 0x8000 /* set bit 0 */
1280 .globl icache_disable
1282 addis r3,r0, 0x0000 /* clear bit 0 */
1287 .globl icache_status
1290 srwi r3, r3, 31 /* >>31 => select bit 0 */
1293 .globl dcache_enable
1296 bl invalidate_dcache
1299 addis r3,r0, 0x8000 /* set bit 0 */
1303 .globl dcache_disable
1308 addis r3,r0, 0x0000 /* clear bit 0 */
1312 .globl dcache_status
1315 srwi r3, r3, 31 /* >>31 => select bit 0 */
1324 /*------------------------------------------------------------------------------- */
1325 /* Function: out16 */
1326 /* Description: Output 16 bits */
1327 /*------------------------------------------------------------------------------- */
1333 /*------------------------------------------------------------------------------- */
1334 /* Function: out16r */
1335 /* Description: Byte reverse and output 16 bits */
1336 /*------------------------------------------------------------------------------- */
1342 /*------------------------------------------------------------------------------- */
1343 /* Function: out32r */
1344 /* Description: Byte reverse and output 32 bits */
1345 /*------------------------------------------------------------------------------- */
1351 /*------------------------------------------------------------------------------- */
1352 /* Function: in16 */
1353 /* Description: Input 16 bits */
1354 /*------------------------------------------------------------------------------- */
1360 /*------------------------------------------------------------------------------- */
1361 /* Function: in16r */
1362 /* Description: Input 16 bits and byte reverse */
1363 /*------------------------------------------------------------------------------- */
1369 /*------------------------------------------------------------------------------- */
1370 /* Function: in32r */
1371 /* Description: Input 32 bits and byte reverse */
1372 /*------------------------------------------------------------------------------- */
1378 /*------------------------------------------------------------------------------- */
1379 /* Function: ppcDcbf */
1380 /* Description: Data Cache block flush */
1381 /* Input: r3 = effective address */
1383 /*------------------------------------------------------------------------------- */
1389 /*------------------------------------------------------------------------------- */
1390 /* Function: ppcDcbi */
1391 /* Description: Data Cache block Invalidate */
1392 /* Input: r3 = effective address */
1394 /*------------------------------------------------------------------------------- */
1400 /*------------------------------------------------------------------------------- */
1401 /* Function: ppcSync */
1402 /* Description: Processor Synchronize */
1405 /*------------------------------------------------------------------------------- */
1412 * void relocate_code (addr_sp, gd, addr_moni)
1414 * This "function" does not return, instead it continues in RAM
1415 * after relocating the monitor code.
1419 * r5 = length in bytes
1420 * r6 = cachelinesize
1422 .globl relocate_code
1424 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1425 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1426 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1428 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1429 * to speed up the boot process. Now this cache needs to be disabled.
1431 iccci 0,0 /* Invalidate inst cache */
1432 dccci 0,0 /* Invalidate data cache, now no longer our stack */
1435 addi r1,r0,0x0000 /* TLB entry #0 */
1436 tlbre r0,r1,0x0002 /* Read contents */
1437 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1438 tlbwe r0,r1,0x0002 /* Save it out */
1442 mr r1, r3 /* Set new stack pointer */
1443 mr r9, r4 /* Save copy of Init Data pointer */
1444 mr r10, r5 /* Save copy of Destination Address */
1446 mr r3, r5 /* Destination Address */
1447 lis r4, CFG_MONITOR_BASE@h /* Source Address */
1448 ori r4, r4, CFG_MONITOR_BASE@l
1449 lwz r5, GOT(__init_end)
1451 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
1456 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
1462 /* First our own GOT */
1464 /* the the one used by the C code */
1474 beq cr1,4f /* In place copy is not necessary */
1475 beq 7f /* Protect against 0 count */
1494 * Now flush the cache: note that we must start from a cache aligned
1495 * address. Otherwise we might miss one cache line.
1499 beq 7f /* Always flush prefetch queue in any case */
1507 sync /* Wait for all dcbst to complete on bus */
1513 7: sync /* Wait for all icbi to complete on bus */
1517 * We are done. Do not return, instead branch to second part of board
1518 * initialization, now running from RAM.
1521 addi r0, r10, in_ram - _start + _START_OFFSET
1523 blr /* NEVER RETURNS! */
1528 * Relocation Function, r14 point to got2+0x8000
1530 * Adjust got2 pointers, no need to check for 0, this code
1531 * already puts a few entries in the table.
1533 li r0,__got2_entries@sectoff@l
1534 la r3,GOT(_GOT2_TABLE_)
1535 lwz r11,GOT(_GOT2_TABLE_)
1545 * Now adjust the fixups and the pointers to the fixups
1546 * in case we need to move ourselves again.
1548 2: li r0,__fixup_entries@sectoff@l
1549 lwz r3,GOT(_FIXUP_TABLE_)
1563 * Now clear BSS segment
1565 lwz r3,GOT(__bss_start)
1579 mr r3, r9 /* Init Data pointer */
1580 mr r4, r10 /* Destination Address */
1584 * Copy exception vector code to low memory
1587 * r7: source address, r8: end address, r9: target address
1591 lwz r7, GOT(_start_of_vectors)
1592 lwz r8, GOT(_end_of_vectors)
1594 li r9, 0x100 /* reset vector always at 0x100 */
1597 bgelr /* return if r7>=r8 - just in case */
1599 mflr r4 /* save link register */
1609 * relocate `hdlr' and `int_return' entries
1611 li r7, .L_MachineCheck - _start + _START_OFFSET
1612 li r8, Alignment - _start + _START_OFFSET
1615 addi r7, r7, 0x100 /* next exception vector */
1619 li r7, .L_Alignment - _start + _START_OFFSET
1622 li r7, .L_ProgramCheck - _start + _START_OFFSET
1626 li r7, .L_FPUnavailable - _start + _START_OFFSET
1629 li r7, .L_Decrementer - _start + _START_OFFSET
1632 li r7, .L_APU - _start + _START_OFFSET
1635 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1638 li r7, .L_DataTLBError - _start + _START_OFFSET
1640 #else /* CONFIG_440 */
1641 li r7, .L_PIT - _start + _START_OFFSET
1644 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1647 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1649 #endif /* CONFIG_440 */
1651 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1654 #if !defined(CONFIG_440)
1655 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1656 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1657 mtmsr r7 /* change MSR */
1660 b __440_msr_continue
1663 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1664 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1672 mtlr r4 /* restore link register */
1676 * Function: relocate entries for one exception vector
1679 lwz r0, 0(r7) /* hdlr ... */
1680 add r0, r0, r3 /* ... += dest_addr */
1683 lwz r0, 4(r7) /* int_return ... */
1684 add r0, r0, r3 /* ... += dest_addr */
1689 #if defined(CONFIG_440)
1690 /*----------------------------------------------------------------------------+
1692 +----------------------------------------------------------------------------*/
1693 function_prolog(dcbz_area)
1694 rlwinm. r5,r4,0,27,31
1695 rlwinm r5,r4,27,5,31
1704 function_epilog(dcbz_area)
1706 /*----------------------------------------------------------------------------+
1707 | dflush. Assume 32K at vector address is cachable.
1708 +----------------------------------------------------------------------------*/
1709 function_prolog(dflush)
1711 rlwinm r8,r9,0,15,13
1712 rlwinm r8,r8,0,17,15
1731 function_epilog(dflush)
1732 #endif /* CONFIG_440 */
1733 #endif /* CONFIG_NAND_SPL */
1735 /*------------------------------------------------------------------------------- */
1737 /* Description: Input 8 bits */
1738 /*------------------------------------------------------------------------------- */
1744 /*------------------------------------------------------------------------------- */
1745 /* Function: out8 */
1746 /* Description: Output 8 bits */
1747 /*------------------------------------------------------------------------------- */
1753 /*------------------------------------------------------------------------------- */
1754 /* Function: out32 */
1755 /* Description: Output 32 bits */
1756 /*------------------------------------------------------------------------------- */
1762 /*------------------------------------------------------------------------------- */
1763 /* Function: in32 */
1764 /* Description: Input 32 bits */
1765 /*------------------------------------------------------------------------------- */
1772 iccci r0,r0 /* for 405, iccci invalidates the */
1773 blr /* entire I cache */
1776 addi r6,0,0x0000 /* clear GPR 6 */
1777 /* Do loop for # of dcache congruence classes. */
1778 lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */
1779 ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
1780 /* NOTE: dccci invalidates both */
1781 mtctr r7 /* ways in the D cache */
1783 dccci 0,r6 /* invalidate line */
1784 addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */
1788 /**************************************************************************/
1789 /* PPC405EP specific stuff */
1790 /**************************************************************************/
1794 #ifdef CONFIG_BUBINGA
1796 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1797 * function) to support FPGA and NVRAM accesses below.
1800 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1801 ori r3,r3,GPIO0_OSRH@l
1802 lis r4,CFG_GPIO0_OSRH@h
1803 ori r4,r4,CFG_GPIO0_OSRH@l
1806 ori r3,r3,GPIO0_OSRL@l
1807 lis r4,CFG_GPIO0_OSRL@h
1808 ori r4,r4,CFG_GPIO0_OSRL@l
1811 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1812 ori r3,r3,GPIO0_ISR1H@l
1813 lis r4,CFG_GPIO0_ISR1H@h
1814 ori r4,r4,CFG_GPIO0_ISR1H@l
1816 lis r3,GPIO0_ISR1L@h
1817 ori r3,r3,GPIO0_ISR1L@l
1818 lis r4,CFG_GPIO0_ISR1L@h
1819 ori r4,r4,CFG_GPIO0_ISR1L@l
1822 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1823 ori r3,r3,GPIO0_TSRH@l
1824 lis r4,CFG_GPIO0_TSRH@h
1825 ori r4,r4,CFG_GPIO0_TSRH@l
1828 ori r3,r3,GPIO0_TSRL@l
1829 lis r4,CFG_GPIO0_TSRL@h
1830 ori r4,r4,CFG_GPIO0_TSRL@l
1833 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1834 ori r3,r3,GPIO0_TCR@l
1835 lis r4,CFG_GPIO0_TCR@h
1836 ori r4,r4,CFG_GPIO0_TCR@l
1839 li r3,pb1ap /* program EBC bank 1 for RTC access */
1841 lis r3,CFG_EBC_PB1AP@h
1842 ori r3,r3,CFG_EBC_PB1AP@l
1846 lis r3,CFG_EBC_PB1CR@h
1847 ori r3,r3,CFG_EBC_PB1CR@l
1850 li r3,pb1ap /* program EBC bank 1 for RTC access */
1852 lis r3,CFG_EBC_PB1AP@h
1853 ori r3,r3,CFG_EBC_PB1AP@l
1857 lis r3,CFG_EBC_PB1CR@h
1858 ori r3,r3,CFG_EBC_PB1CR@l
1861 li r3,pb4ap /* program EBC bank 4 for FPGA access */
1863 lis r3,CFG_EBC_PB4AP@h
1864 ori r3,r3,CFG_EBC_PB4AP@l
1868 lis r3,CFG_EBC_PB4CR@h
1869 ori r3,r3,CFG_EBC_PB4CR@l
1874 !-----------------------------------------------------------------------
1875 ! Check to see if chip is in bypass mode.
1876 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1877 ! CPU reset Otherwise, skip this step and keep going.
1878 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1879 ! will not be fast enough for the SDRAM (min 66MHz)
1880 !-----------------------------------------------------------------------
1882 mfdcr r5, CPC0_PLLMR1
1883 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1886 beq pll_done /* if SSCS =b'1' then PLL has */
1887 /* already been set */
1888 /* and CPU has been reset */
1889 /* so skip to next section */
1891 #ifdef CONFIG_BUBINGA
1893 !-----------------------------------------------------------------------
1894 ! Read NVRAM to get value to write in PLLMR.
1895 ! If value has not been correctly saved, write default value
1896 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1897 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1899 ! WARNING: This code assumes the first three words in the nvram_t
1900 ! structure in openbios.h. Changing the beginning of
1901 ! the structure will break this code.
1903 !-----------------------------------------------------------------------
1905 addis r3,0,NVRAM_BASE@h
1906 addi r3,r3,NVRAM_BASE@l
1909 addis r5,0,NVRVFY1@h
1910 addi r5,r5,NVRVFY1@l
1911 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1915 addis r5,0,NVRVFY2@h
1916 addi r5,r5,NVRVFY2@l
1917 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1919 addi r3,r3,8 /* Skip over conf_size */
1920 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1921 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1922 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1923 cmpi cr0,0,r5,1 /* See if PLL is locked */
1926 #endif /* CONFIG_BUBINGA */
1930 andi. r5, r4, CPC0_BOOT_SEP@l
1931 bne strap_1 /* serial eeprom present */
1932 addis r5,0,CPLD_REG0_ADDR@h
1933 ori r5,r5,CPLD_REG0_ADDR@l
1936 #endif /* CONFIG_TAIHU */
1938 #if defined(CONFIG_ZEUS)
1940 andi. r5, r4, CPC0_BOOT_SEP@l
1941 bne strap_1 /* serial eeprom present */
1948 mfdcr r3, CPC0_PLLMR0
1949 mfdcr r4, CPC0_PLLMR1
1953 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1954 ori r3,r3,PLLMR0_DEFAULT@l /* */
1955 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1956 ori r4,r4,PLLMR1_DEFAULT@l /* */
1961 addis r3,0,PLLMR0_DEFAULT_PCI66@h
1962 ori r3,r3,PLLMR0_DEFAULT_PCI66@l
1963 addis r4,0,PLLMR1_DEFAULT_PCI66@h
1964 ori r4,r4,PLLMR1_DEFAULT_PCI66@l
1967 mfdcr r3, CPC0_PLLMR0
1968 mfdcr r4, CPC0_PLLMR1
1969 #endif /* CONFIG_TAIHU */
1972 b pll_write /* Write the CPC0_PLLMR with new value */
1976 !-----------------------------------------------------------------------
1977 ! Clear Soft Reset Register
1978 ! This is needed to enable PCI if not booting from serial EPROM
1979 !-----------------------------------------------------------------------
1989 blr /* return to main code */
1992 !-----------------------------------------------------------------------------
1993 ! Function: pll_write
1994 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1996 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
1998 ! 3. Clock dividers are set while PLL is held in reset and bypassed
1999 ! 4. PLL Reset is cleared
2000 ! 5. Wait 100us for PLL to lock
2001 ! 6. A core reset is performed
2002 ! Input: r3 = Value to write to CPC0_PLLMR0
2003 ! Input: r4 = Value to write to CPC0_PLLMR1
2005 !-----------------------------------------------------------------------------
2010 ori r5,r5,0x0101 /* Stop the UART clocks */
2011 mtdcr CPC0_UCR,r5 /* Before changing PLL */
2013 mfdcr r5, CPC0_PLLMR1
2014 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
2015 mtdcr CPC0_PLLMR1,r5
2016 oris r5,r5,0x4000 /* Set PLL Reset */
2017 mtdcr CPC0_PLLMR1,r5
2019 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
2020 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
2021 oris r5,r5,0x4000 /* Set PLL Reset */
2022 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
2023 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
2024 mtdcr CPC0_PLLMR1,r5
2027 ! Wait min of 100us for PLL to lock.
2028 ! See CMOS 27E databook for more info.
2029 ! At 200MHz, that means waiting 20,000 instructions
2031 addi r3,0,20000 /* 2000 = 0x4e20 */
2036 oris r5,r5,0x8000 /* Enable PLL */
2037 mtdcr CPC0_PLLMR1,r5 /* Engage */
2040 * Reset CPU to guarantee timings are OK
2041 * Not sure if this is needed...
2044 mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
2045 /* execution will continue from the poweron */
2046 /* vector of 0xfffffffc */
2047 #endif /* CONFIG_405EP */
2049 #if defined(CONFIG_440)
2050 /*----------------------------------------------------------------------------+
2052 +----------------------------------------------------------------------------*/
2053 function_prolog(mttlb3)
2056 function_epilog(mttlb3)
2058 /*----------------------------------------------------------------------------+
2060 +----------------------------------------------------------------------------*/
2061 function_prolog(mftlb3)
2064 function_epilog(mftlb3)
2066 /*----------------------------------------------------------------------------+
2068 +----------------------------------------------------------------------------*/
2069 function_prolog(mttlb2)
2072 function_epilog(mttlb2)
2074 /*----------------------------------------------------------------------------+
2076 +----------------------------------------------------------------------------*/
2077 function_prolog(mftlb2)
2080 function_epilog(mftlb2)
2082 /*----------------------------------------------------------------------------+
2084 +----------------------------------------------------------------------------*/
2085 function_prolog(mttlb1)
2088 function_epilog(mttlb1)
2090 /*----------------------------------------------------------------------------+
2092 +----------------------------------------------------------------------------*/
2093 function_prolog(mftlb1)
2096 function_epilog(mftlb1)
2097 #endif /* CONFIG_440 */