2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright (c) 2008 Nuovation System Designs, LLC
7 * Grant Erickson <gerickson@nuovations.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 /*------------------------------------------------------------------------------+
29 * This source code has been made available to you by IBM on an AS-IS
30 * basis. Anyone receiving this source is licensed under IBM
31 * copyrights to use it in any way he or she deems fit, including
32 * copying it, modifying it, compiling it, and redistributing it either
33 * with or without modifications. No license under IBM patents or
34 * patent applications is to be implied by the copyright license.
36 * Any user of this software should understand that IBM cannot provide
37 * technical support for this software and will not be responsible for
38 * any consequences resulting from the use of this software.
40 * Any person who transfers this source code or any derivative work
41 * must include the IBM copyright notice, this paragraph, and the
42 * preceding two paragraphs in the transferred software.
44 * COPYRIGHT I B M CORPORATION 1995
45 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
46 *-------------------------------------------------------------------------------
49 /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
52 * The processor starts at 0xfffffffc and the code is executed
54 * in memory, but as long we don't jump around before relocating.
55 * board_init lies at a quite high address and when the cpu has
56 * jumped there, everything is ok.
57 * This works because the cpu gives the FLASH (CS0) the whole
58 * address space at startup, and board_init lies as a echo of
59 * the flash somewhere up there in the memorymap.
61 * board_init will change CS0 to be positioned at the correct
62 * address and (s)dram will be positioned at address 0
68 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
70 #include <ppc_asm.tmpl>
73 #include <asm/cache.h>
76 #ifndef CONFIG_IDENT_STRING
77 #define CONFIG_IDENT_STRING ""
80 #ifdef CFG_INIT_DCACHE_CS
81 # if (CFG_INIT_DCACHE_CS == 0)
84 # if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
85 # define PBxAP_VAL CFG_EBC_PB0AP
86 # define PBxCR_VAL CFG_EBC_PB0CR
89 # if (CFG_INIT_DCACHE_CS == 1)
92 # if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
93 # define PBxAP_VAL CFG_EBC_PB1AP
94 # define PBxCR_VAL CFG_EBC_PB1CR
97 # if (CFG_INIT_DCACHE_CS == 2)
100 # if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
101 # define PBxAP_VAL CFG_EBC_PB2AP
102 # define PBxCR_VAL CFG_EBC_PB2CR
105 # if (CFG_INIT_DCACHE_CS == 3)
108 # if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
109 # define PBxAP_VAL CFG_EBC_PB3AP
110 # define PBxCR_VAL CFG_EBC_PB3CR
113 # if (CFG_INIT_DCACHE_CS == 4)
116 # if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
117 # define PBxAP_VAL CFG_EBC_PB4AP
118 # define PBxCR_VAL CFG_EBC_PB4CR
121 # if (CFG_INIT_DCACHE_CS == 5)
124 # if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
125 # define PBxAP_VAL CFG_EBC_PB5AP
126 # define PBxCR_VAL CFG_EBC_PB5CR
129 # if (CFG_INIT_DCACHE_CS == 6)
132 # if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
133 # define PBxAP_VAL CFG_EBC_PB6AP
134 # define PBxCR_VAL CFG_EBC_PB6CR
137 # if (CFG_INIT_DCACHE_CS == 7)
140 # if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
141 # define PBxAP_VAL CFG_EBC_PB7AP
142 # define PBxCR_VAL CFG_EBC_PB7CR
152 * Memory Bank x (nothingness) initialization CFG_INIT_RAM_ADDR + 64 MiB
153 * used as temporary stack pointer for the primordial stack
155 # ifndef CFG_INIT_DCACHE_PBxAR
156 # define CFG_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
157 EBC_BXAP_TWT_ENCODE(7) | \
158 EBC_BXAP_BCE_DISABLE | \
159 EBC_BXAP_BCT_2TRANS | \
160 EBC_BXAP_CSN_ENCODE(0) | \
161 EBC_BXAP_OEN_ENCODE(0) | \
162 EBC_BXAP_WBN_ENCODE(0) | \
163 EBC_BXAP_WBF_ENCODE(0) | \
164 EBC_BXAP_TH_ENCODE(2) | \
165 EBC_BXAP_RE_DISABLED | \
166 EBC_BXAP_SOR_NONDELAYED | \
167 EBC_BXAP_BEM_WRITEONLY | \
168 EBC_BXAP_PEN_DISABLED)
169 # endif /* CFG_INIT_DCACHE_PBxAR */
170 # ifndef CFG_INIT_DCACHE_PBxCR
171 # define CFG_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CFG_INIT_RAM_ADDR) | \
175 # endif /* CFG_INIT_DCACHE_PBxCR */
176 # ifndef CFG_INIT_RAM_PATTERN
177 # define CFG_INIT_RAM_PATTERN 0xDEADDEAD
179 #endif /* CFG_INIT_DCACHE_CS */
181 #if (defined(CFG_INIT_RAM_DCACHE) && (CFG_INIT_RAM_END > (4 << 10)))
182 #error Only 4k of init-ram is supported - please adjust CFG_INIT_RAM_END!
186 * Unless otherwise overriden, enable two 128MB cachable instruction regions
187 * at CFG_SDRAM_BASE and another 128MB cacheable instruction region covering
188 * NOR flash at CFG_FLASH_BASE. Disable all cacheable data regions.
190 #if !defined(CFG_FLASH_BASE)
191 /* If not already defined, set it to the "last" 128MByte region */
192 # define CFG_FLASH_BASE 0xf8000000
194 #if !defined(CFG_ICACHE_SACR_VALUE)
195 # define CFG_ICACHE_SACR_VALUE \
196 (PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + ( 0 << 20)) | \
197 PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + (128 << 20)) | \
198 PPC_128MB_SACR_VALUE(CFG_FLASH_BASE))
199 #endif /* !defined(CFG_ICACHE_SACR_VALUE) */
201 #if !defined(CFG_DCACHE_SACR_VALUE)
202 # define CFG_DCACHE_SACR_VALUE \
204 #endif /* !defined(CFG_DCACHE_SACR_VALUE) */
206 #define function_prolog(func_name) .text; \
210 #define function_epilog(func_name) .type func_name,@function; \
211 .size func_name,.-func_name
213 /* We don't want the MMU yet.
216 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
219 .extern ext_bus_cntlr_init
221 #ifdef CONFIG_NAND_U_BOOT
222 .extern reconfig_tlb0
226 * Set up GOT: Global Offset Table
228 * Use r14 to access the GOT
230 #if !defined(CONFIG_NAND_SPL)
232 GOT_ENTRY(_GOT2_TABLE_)
233 GOT_ENTRY(_FIXUP_TABLE_)
236 GOT_ENTRY(_start_of_vectors)
237 GOT_ENTRY(_end_of_vectors)
238 GOT_ENTRY(transfer_to_handler)
240 GOT_ENTRY(__init_end)
242 GOT_ENTRY(__bss_start)
244 #endif /* CONFIG_NAND_SPL */
246 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
248 * NAND U-Boot image is started from offset 0
251 #if defined(CONFIG_440)
255 bl cpu_init_f /* run low-level CPU init code (from Flash) */
260 * 440 Startup -- on reset only the top 4k of the effective
261 * address space is mapped in by an entry in the instruction
262 * and data shadow TLB. The .bootpg section is located in the
263 * top 4k & does only what's necessary to map in the the rest
264 * of the boot rom. Once the boot rom is mapped in we can
265 * proceed with normal startup.
267 * NOTE: CS0 only covers the top 2MB of the effective address
271 #if defined(CONFIG_440)
272 #if !defined(CONFIG_NAND_SPL)
273 .section .bootpg,"ax"
277 /**************************************************************************/
279 /*--------------------------------------------------------------------+
280 | 440EPX BUP Change - Hardware team request
281 +--------------------------------------------------------------------*/
282 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
287 /*----------------------------------------------------------------+
288 | Core bug fix. Clear the esr
289 +-----------------------------------------------------------------*/
292 /*----------------------------------------------------------------*/
293 /* Clear and set up some registers. */
294 /*----------------------------------------------------------------*/
295 iccci r0,r0 /* NOTE: operands not used for 440 */
296 dccci r0,r0 /* NOTE: operands not used for 440 */
303 /* NOTE: 440GX adds machine check status regs */
304 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
311 /*----------------------------------------------------------------*/
313 /*----------------------------------------------------------------*/
314 /* Disable store gathering & broadcast, guarantee inst/data
315 * cache block touch, force load/store alignment
316 * (see errata 1.12: 440_33)
318 lis r1,0x0030 /* store gathering & broadcast disable */
319 ori r1,r1,0x6000 /* cache touch */
322 /*----------------------------------------------------------------*/
323 /* Initialize debug */
324 /*----------------------------------------------------------------*/
326 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
327 bne skip_debug_init /* if set, don't clear debug register */
340 mtspr dbsr,r1 /* Clear all valid bits */
343 #if defined (CONFIG_440SPE)
344 /*----------------------------------------------------------------+
345 | Initialize Core Configuration Reg1.
346 | a. ICDPEI: Record even parity. Normal operation.
347 | b. ICTPEI: Record even parity. Normal operation.
348 | c. DCTPEI: Record even parity. Normal operation.
349 | d. DCDPEI: Record even parity. Normal operation.
350 | e. DCUPEI: Record even parity. Normal operation.
351 | f. DCMPEI: Record even parity. Normal operation.
352 | g. FCOM: Normal operation
353 | h. MMUPEI: Record even parity. Normal operation.
354 | i. FFF: Flush only as much data as necessary.
355 | j. TCS: Timebase increments from CPU clock.
356 +-----------------------------------------------------------------*/
360 /*----------------------------------------------------------------+
361 | Reset the timebase.
362 | The previous write to CCR1 sets the timebase source.
363 +-----------------------------------------------------------------*/
368 /*----------------------------------------------------------------*/
369 /* Setup interrupt vectors */
370 /*----------------------------------------------------------------*/
371 mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */
373 mtspr ivor0,r1 /* Critical input */
375 mtspr ivor1,r1 /* Machine check */
377 mtspr ivor2,r1 /* Data storage */
379 mtspr ivor3,r1 /* Instruction storage */
381 mtspr ivor4,r1 /* External interrupt */
383 mtspr ivor5,r1 /* Alignment */
385 mtspr ivor6,r1 /* Program check */
387 mtspr ivor7,r1 /* Floating point unavailable */
389 mtspr ivor8,r1 /* System call */
391 mtspr ivor9,r1 /* Auxiliary Processor unavailable */
393 mtspr ivor10,r1 /* Decrementer */
395 mtspr ivor13,r1 /* Data TLB error */
397 mtspr ivor14,r1 /* Instr TLB error */
399 mtspr ivor15,r1 /* Debug */
401 /*----------------------------------------------------------------*/
402 /* Configure cache regions */
403 /*----------------------------------------------------------------*/
421 /*----------------------------------------------------------------*/
422 /* Cache victim limits */
423 /*----------------------------------------------------------------*/
424 /* floors 0, ceiling max to use the entire cache -- nothing locked
431 /*----------------------------------------------------------------+
432 |Initialize MMUCR[STID] = 0.
433 +-----------------------------------------------------------------*/
440 /*----------------------------------------------------------------*/
441 /* Clear all TLB entries -- TID = 0, TS = 0 */
442 /*----------------------------------------------------------------*/
444 li r1,0x003f /* 64 TLB entries */
446 rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
452 /*----------------------------------------------------------------*/
453 /* TLB entry setup -- step thru tlbtab */
454 /*----------------------------------------------------------------*/
455 #if defined(CONFIG_440SPE)
456 /*----------------------------------------------------------------*/
457 /* We have different TLB tables for revA and rev B of 440SPe */
458 /*----------------------------------------------------------------*/
470 bl tlbtab /* Get tlbtab pointer */
473 li r1,0x003f /* 64 TLB entries max */
480 beq 2f /* 0 marks end */
483 tlbwe r0,r4,0 /* TLB Word 0 */
484 tlbwe r1,r4,1 /* TLB Word 1 */
485 tlbwe r2,r4,2 /* TLB Word 2 */
486 addi r4,r4,1 /* Next TLB */
489 /*----------------------------------------------------------------*/
490 /* Continue from 'normal' start */
491 /*----------------------------------------------------------------*/
497 mtspr srr1,r0 /* Keep things disabled for now */
501 #endif /* CONFIG_440 */
504 * r3 - 1st arg to board_init(): IMMP pointer
505 * r4 - 2nd arg to board_init(): boot flag
507 #ifndef CONFIG_NAND_SPL
509 .long 0x27051956 /* U-Boot Magic Number */
510 .globl version_string
512 .ascii U_BOOT_VERSION
513 .ascii " (", __DATE__, " - ", __TIME__, ")"
514 .ascii CONFIG_IDENT_STRING, "\0"
516 . = EXC_OFF_SYS_RESET
517 .globl _start_of_vectors
520 /* Critical input. */
521 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
525 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
527 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
528 #endif /* CONFIG_440 */
530 /* Data Storage exception. */
531 STD_EXCEPTION(0x300, DataStorage, UnknownException)
533 /* Instruction Storage exception. */
534 STD_EXCEPTION(0x400, InstStorage, UnknownException)
536 /* External Interrupt exception. */
537 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
539 /* Alignment exception. */
542 EXCEPTION_PROLOG(SRR0, SRR1)
547 addi r3,r1,STACK_FRAME_OVERHEAD
549 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
550 lwz r6,GOT(transfer_to_handler)
554 .long AlignmentException - _start + _START_OFFSET
555 .long int_return - _start + _START_OFFSET
557 /* Program check exception */
560 EXCEPTION_PROLOG(SRR0, SRR1)
561 addi r3,r1,STACK_FRAME_OVERHEAD
563 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
564 lwz r6,GOT(transfer_to_handler)
568 .long ProgramCheckException - _start + _START_OFFSET
569 .long int_return - _start + _START_OFFSET
572 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
573 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
574 STD_EXCEPTION(0xa00, APU, UnknownException)
576 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
579 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
580 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
582 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
583 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
584 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
586 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
588 .globl _end_of_vectors
595 /*****************************************************************************/
596 #if defined(CONFIG_440)
598 /*----------------------------------------------------------------*/
599 /* Clear and set up some registers. */
600 /*----------------------------------------------------------------*/
603 mtspr dec,r0 /* prevent dec exceptions */
604 mtspr tbl,r0 /* prevent fit & wdt exceptions */
606 mtspr tsr,r1 /* clear all timer exception status */
607 mtspr tcr,r0 /* disable all */
608 mtspr esr,r0 /* clear exception syndrome register */
609 mtxer r0 /* clear integer exception register */
611 /*----------------------------------------------------------------*/
612 /* Debug setup -- some (not very good) ice's need an event*/
613 /* to establish control :-( Define CFG_INIT_DBCR to the dbsr */
614 /* value you need in this case 0x8cff 0000 should do the trick */
615 /*----------------------------------------------------------------*/
616 #if defined(CFG_INIT_DBCR)
619 mtspr dbsr,r1 /* Clear all status bits */
620 lis r0,CFG_INIT_DBCR@h
621 ori r0,r0,CFG_INIT_DBCR@l
626 /*----------------------------------------------------------------*/
627 /* Setup the internal SRAM */
628 /*----------------------------------------------------------------*/
631 #ifdef CFG_INIT_RAM_DCACHE
632 /* Clear Dcache to use as RAM */
633 addis r3,r0,CFG_INIT_RAM_ADDR@h
634 ori r3,r3,CFG_INIT_RAM_ADDR@l
635 addis r4,r0,CFG_INIT_RAM_END@h
636 ori r4,r4,CFG_INIT_RAM_END@l
637 rlwinm. r5,r4,0,27,31
649 * Lock the init-ram/stack in d-cache, so that other regions
650 * may use d-cache as well
651 * Note, that this current implementation locks exactly 4k
652 * of d-cache, so please make sure that you don't define a
653 * bigger init-ram area. Take a look at the lwmon5 440EPx
654 * implementation as a reference.
658 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
674 #endif /* CFG_INIT_RAM_DCACHE */
676 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
677 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
678 /* not all PPC's have internal SRAM usable as L2-cache */
679 #if defined(CONFIG_440GX) || \
680 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
681 defined(CONFIG_460EX) || defined(CONFIG_460GT)
682 mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
688 and r1,r1,r2 /* Disable parity check */
691 and r1,r1,r2 /* Disable pwr mgmt */
694 lis r1,0x8000 /* BAS = 8000_0000 */
695 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
696 ori r1,r1,0x0980 /* first 64k */
697 mtdcr isram0_sb0cr,r1
699 ori r1,r1,0x0980 /* second 64k */
700 mtdcr isram0_sb1cr,r1
702 ori r1,r1, 0x0980 /* third 64k */
703 mtdcr isram0_sb2cr,r1
705 ori r1,r1, 0x0980 /* fourth 64k */
706 mtdcr isram0_sb3cr,r1
707 #elif defined(CONFIG_440SPE)
708 lis r1,0x0000 /* BAS = 0000_0000 */
709 ori r1,r1,0x0984 /* first 64k */
710 mtdcr isram0_sb0cr,r1
712 ori r1,r1,0x0984 /* second 64k */
713 mtdcr isram0_sb1cr,r1
715 ori r1,r1, 0x0984 /* third 64k */
716 mtdcr isram0_sb2cr,r1
718 ori r1,r1, 0x0984 /* fourth 64k */
719 mtdcr isram0_sb3cr,r1
720 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
721 lis r1,0x4000 /* BAS = 8000_0000 */
722 ori r1,r1,0x4580 /* 16k */
723 mtdcr isram0_sb0cr,r1
724 #elif defined(CONFIG_440GP)
725 ori r1,r1,0x0380 /* 8k rw */
726 mtdcr isram0_sb0cr,r1
727 mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
729 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
731 /*----------------------------------------------------------------*/
732 /* Setup the stack in internal SRAM */
733 /*----------------------------------------------------------------*/
734 lis r1,CFG_INIT_RAM_ADDR@h
735 ori r1,r1,CFG_INIT_SP_OFFSET@l
738 stwu r0,-4(r1) /* Terminate call chain */
740 stwu r1,-8(r1) /* Save back chain and move SP */
741 lis r0,RESET_VECTOR@h /* Address of reset vector */
742 ori r0,r0, RESET_VECTOR@l
743 stwu r1,-8(r1) /* Save back chain and move SP */
744 stw r0,+12(r1) /* Save return addr (underflow vect) */
746 #ifdef CONFIG_NAND_SPL
747 bl nand_boot_common /* will not return */
751 bl cpu_init_f /* run low-level CPU init code (from Flash) */
755 #endif /* CONFIG_440 */
757 /*****************************************************************************/
759 /*----------------------------------------------------------------------- */
760 /* Set up some machine state registers. */
761 /*----------------------------------------------------------------------- */
762 addi r0,r0,0x0000 /* initialize r0 to zero */
763 mtspr esr,r0 /* clear Exception Syndrome Reg */
764 mttcr r0 /* timer control register */
765 mtexier r0 /* disable all interrupts */
766 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
767 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
768 mtdbsr r4 /* clear/reset the dbsr */
769 mtexisr r4 /* clear all pending interrupts */
771 mtexier r4 /* enable critical exceptions */
772 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
773 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
774 mtiocr r4 /* since bit not used) & DRC to latch */
775 /* data bus on rising edge of CAS */
776 /*----------------------------------------------------------------------- */
778 /*----------------------------------------------------------------------- */
780 /*----------------------------------------------------------------------- */
781 /* Invalidate i-cache and d-cache TAG arrays. */
782 /*----------------------------------------------------------------------- */
783 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
784 addi r4,0,1024 /* 1/4 of I-cache */
789 addic. r3,r3,-16 /* move back one cache line */
790 bne ..cloop /* loop back to do rest until r3 = 0 */
793 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
794 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
797 /* first copy IOP480 register base address into r3 */
798 addis r3,0,0x5000 /* IOP480 register base address hi */
799 /* ori r3,r3,0x0000 / IOP480 register base address lo */
802 /* use r4 as the working variable */
803 /* turn on CS3 (LOCCTL.7) */
804 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
805 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
806 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
809 #ifdef CONFIG_DASA_SIM
810 /* use r4 as the working variable */
811 /* turn on MA17 (LOCCTL.7) */
812 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
813 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
814 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
817 /* turn on MA16..13 (LCS0BRD.12 = 0) */
818 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
819 andi. r4,r4,0xefff /* make bit 12 = 0 */
820 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
822 /* make sure above stores all comlete before going on */
825 /* last thing, set local init status done bit (DEVINIT.31) */
826 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
827 oris r4,r4,0x8000 /* make bit 31 = 1 */
828 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
830 /* clear all pending interrupts and disable all interrupts */
831 li r4,-1 /* set p1 to 0xffffffff */
832 stw r4,0x1b0(r3) /* clear all pending interrupts */
833 stw r4,0x1b8(r3) /* clear all pending interrupts */
834 li r4,0 /* set r4 to 0 */
835 stw r4,0x1b4(r3) /* disable all interrupts */
836 stw r4,0x1bc(r3) /* disable all interrupts */
838 /* make sure above stores all comlete before going on */
841 /* Set-up icache cacheability. */
842 lis r1, CFG_ICACHE_SACR_VALUE@h
843 ori r1, r1, CFG_ICACHE_SACR_VALUE@l
847 /* Set-up dcache cacheability. */
848 lis r1, CFG_DCACHE_SACR_VALUE@h
849 ori r1, r1, CFG_DCACHE_SACR_VALUE@l
852 addis r1,r0,CFG_INIT_RAM_ADDR@h
853 ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */
854 li r0, 0 /* Make room for stack frame header and */
855 stwu r0, -4(r1) /* clear final stack frame so that */
856 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
858 GET_GOT /* initialize GOT access */
860 bl board_init_f /* run first part of init code (from Flash) */
862 #endif /* CONFIG_IOP480 */
864 /*****************************************************************************/
865 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
866 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
867 defined(CONFIG_405EX) || defined(CONFIG_405)
868 /*----------------------------------------------------------------------- */
869 /* Clear and set up some registers. */
870 /*----------------------------------------------------------------------- */
872 #if !defined(CONFIG_405EX)
876 * On 405EX, completely clearing the SGR leads to PPC hangup
877 * upon PCIe configuration access. The PCIe memory regions
878 * need to be guarded!
885 mtesr r4 /* clear Exception Syndrome Reg */
886 mttcr r4 /* clear Timer Control Reg */
887 mtxer r4 /* clear Fixed-Point Exception Reg */
888 mtevpr r4 /* clear Exception Vector Prefix Reg */
889 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
890 /* dbsr is cleared by setting bits to 1) */
891 mtdbsr r4 /* clear/reset the dbsr */
893 /* Invalidate the i- and d-caches. */
897 /* Set-up icache cacheability. */
898 lis r4, CFG_ICACHE_SACR_VALUE@h
899 ori r4, r4, CFG_ICACHE_SACR_VALUE@l
903 /* Set-up dcache cacheability. */
904 lis r4, CFG_DCACHE_SACR_VALUE@h
905 ori r4, r4, CFG_DCACHE_SACR_VALUE@l
908 #if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
909 /*----------------------------------------------------------------------- */
910 /* Tune the speed and size for flash CS0 */
911 /*----------------------------------------------------------------------- */
912 bl ext_bus_cntlr_init
915 #if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
917 * For boards that don't have OCM and can't use the data cache
918 * for their primordial stack, setup stack here directly after the
919 * SDRAM is initialized in ext_bus_cntlr_init.
921 lis r1, CFG_INIT_RAM_ADDR@h
922 ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
924 li r0, 0 /* Make room for stack frame header and */
925 stwu r0, -4(r1) /* clear final stack frame so that */
926 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
928 * Set up a dummy frame to store reset vector as return address.
929 * this causes stack underflow to reset board.
931 stwu r1, -8(r1) /* Save back chain and move SP */
932 lis r0, RESET_VECTOR@h /* Address of reset vector */
933 ori r0, r0, RESET_VECTOR@l
934 stwu r1, -8(r1) /* Save back chain and move SP */
935 stw r0, +12(r1) /* Save return addr (underflow vect) */
936 #endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
938 #if defined(CONFIG_405EP)
939 /*----------------------------------------------------------------------- */
940 /* DMA Status, clear to come up clean */
941 /*----------------------------------------------------------------------- */
942 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
946 bl ppc405ep_init /* do ppc405ep specific init */
947 #endif /* CONFIG_405EP */
949 #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
950 #if defined(CONFIG_405EZ)
951 /********************************************************************
952 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
953 *******************************************************************/
955 * We can map the OCM on the PLB3, so map it at
956 * CFG_OCM_DATA_ADDR + 0x8000
958 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
959 ori r3,r3,CFG_OCM_DATA_ADDR@l
960 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
961 mtdcr ocmplb3cr1,r3 /* Set PLB Access */
962 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
963 mtdcr ocmplb3cr2,r3 /* Set PLB Access */
966 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
967 ori r3,r3,CFG_OCM_DATA_ADDR@l
968 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
969 mtdcr ocmdscr1, r3 /* Set Data Side */
970 mtdcr ocmiscr1, r3 /* Set Instruction Side */
971 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
972 mtdcr ocmdscr2, r3 /* Set Data Side */
973 mtdcr ocmiscr2, r3 /* Set Instruction Side */
974 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
978 #else /* CONFIG_405EZ */
979 /********************************************************************
980 * Setup OCM - On Chip Memory
981 *******************************************************************/
985 mfdcr r3, ocmiscntl /* get instr-side IRAM config */
986 mfdcr r4, ocmdscntl /* get data-side IRAM config */
987 and r3, r3, r0 /* disable data-side IRAM */
988 and r4, r4, r0 /* disable data-side IRAM */
989 mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
990 mtdcr ocmdscntl, r4 /* set data-side IRAM config */
993 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
994 ori r3,r3,CFG_OCM_DATA_ADDR@l
996 addis r4, 0, 0xC000 /* OCM data area enabled */
999 #endif /* CONFIG_405EZ */
1002 /*----------------------------------------------------------------------- */
1003 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
1004 /*----------------------------------------------------------------------- */
1005 #ifdef CFG_INIT_DCACHE_CS
1008 lis r4, CFG_INIT_DCACHE_PBxAR@h
1009 ori r4, r4, CFG_INIT_DCACHE_PBxAR@l
1014 lis r4, CFG_INIT_DCACHE_PBxCR@h
1015 ori r4, r4, CFG_INIT_DCACHE_PBxCR@l
1019 * Enable the data cache for the 128MB storage access control region
1020 * at CFG_INIT_RAM_ADDR.
1023 oris r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h
1024 ori r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l
1028 * Preallocate data cache lines to be used to avoid a subsequent
1029 * cache miss and an ensuing machine check exception when exceptions
1034 lis r3, CFG_INIT_RAM_ADDR@h
1035 ori r3, r3, CFG_INIT_RAM_ADDR@l
1037 lis r4, CFG_INIT_RAM_END@h
1038 ori r4, r4, CFG_INIT_RAM_END@l
1041 * Convert the size, in bytes, to the number of cache lines/blocks
1044 clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
1045 srwi r5, r4, L1_CACHE_SHIFT
1051 /* Preallocate the computed number of cache blocks. */
1052 ..alloc_dcache_block:
1054 addi r3, r3, L1_CACHE_BYTES
1055 bdnz ..alloc_dcache_block
1059 * Load the initial stack pointer and data area and convert the size,
1060 * in bytes, to the number of words to initialize to a known value.
1062 lis r1, CFG_INIT_RAM_ADDR@h
1063 ori r1, r1, CFG_INIT_SP_OFFSET@l
1065 lis r4, (CFG_INIT_RAM_END >> 2)@h
1066 ori r4, r4, (CFG_INIT_RAM_END >> 2)@l
1069 lis r2, CFG_INIT_RAM_ADDR@h
1070 ori r2, r2, CFG_INIT_RAM_END@l
1072 lis r4, CFG_INIT_RAM_PATTERN@h
1073 ori r4, r4, CFG_INIT_RAM_PATTERN@l
1080 * Make room for stack frame header and clear final stack frame so
1081 * that stack backtraces terminate cleanly.
1087 * Set up a dummy frame to store reset vector as return address.
1088 * this causes stack underflow to reset board.
1090 stwu r1, -8(r1) /* Save back chain and move SP */
1091 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1092 ori r0, r0, RESET_VECTOR@l
1093 stwu r1, -8(r1) /* Save back chain and move SP */
1094 stw r0, +12(r1) /* Save return addr (underflow vect) */
1096 #elif defined(CFG_TEMP_STACK_OCM) && \
1097 (defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE))
1102 /* Set up Stack at top of OCM */
1103 lis r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h
1104 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l
1106 /* Set up a zeroized stack frame so that backtrace works right */
1112 * Set up a dummy frame to store reset vector as return address.
1113 * this causes stack underflow to reset board.
1115 stwu r1, -8(r1) /* Save back chain and move SP */
1116 lis r0, RESET_VECTOR@h /* Address of reset vector */
1117 ori r0, r0, RESET_VECTOR@l
1118 stwu r1, -8(r1) /* Save back chain and move SP */
1119 stw r0, +12(r1) /* Save return addr (underflow vect) */
1120 #endif /* CFG_INIT_DCACHE_CS */
1122 /*----------------------------------------------------------------------- */
1123 /* Initialize SDRAM Controller */
1124 /*----------------------------------------------------------------------- */
1127 #ifdef CONFIG_NAND_SPL
1128 bl nand_boot_common /* will not return */
1130 GET_GOT /* initialize GOT access */
1132 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1134 /* NEVER RETURNS! */
1135 bl board_init_f /* run first part of init code (from Flash) */
1136 #endif /* CONFIG_NAND_SPL */
1138 #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1139 /*----------------------------------------------------------------------- */
1142 #ifndef CONFIG_NAND_SPL
1144 * This code finishes saving the registers to the exception frame
1145 * and jumps to the appropriate handler for the exception.
1146 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1148 .globl transfer_to_handler
1149 transfer_to_handler:
1159 andi. r24,r23,0x3f00 /* get vector offset */
1163 mtspr SPRG2,r22 /* r1 is now kernel sp */
1164 lwz r24,0(r23) /* virtual address of handler */
1165 lwz r23,4(r23) /* where to go when done */
1170 rfi /* jump to handler, enable MMU */
1173 mfmsr r28 /* Disable interrupts */
1177 SYNC /* Some chip revs need this... */
1192 lwz r2,_NIP(r1) /* Restore environment */
1203 mfmsr r28 /* Disable interrupts */
1207 SYNC /* Some chip revs need this... */
1222 lwz r2,_NIP(r1) /* Restore environment */
1234 mfmsr r28 /* Disable interrupts */
1238 SYNC /* Some chip revs need this... */
1253 lwz r2,_NIP(r1) /* Restore environment */
1262 #endif /* CONFIG_440 */
1270 /*------------------------------------------------------------------------------- */
1271 /* Function: out16 */
1272 /* Description: Output 16 bits */
1273 /*------------------------------------------------------------------------------- */
1279 /*------------------------------------------------------------------------------- */
1280 /* Function: out16r */
1281 /* Description: Byte reverse and output 16 bits */
1282 /*------------------------------------------------------------------------------- */
1288 /*------------------------------------------------------------------------------- */
1289 /* Function: out32r */
1290 /* Description: Byte reverse and output 32 bits */
1291 /*------------------------------------------------------------------------------- */
1297 /*------------------------------------------------------------------------------- */
1298 /* Function: in16 */
1299 /* Description: Input 16 bits */
1300 /*------------------------------------------------------------------------------- */
1306 /*------------------------------------------------------------------------------- */
1307 /* Function: in16r */
1308 /* Description: Input 16 bits and byte reverse */
1309 /*------------------------------------------------------------------------------- */
1315 /*------------------------------------------------------------------------------- */
1316 /* Function: in32r */
1317 /* Description: Input 32 bits and byte reverse */
1318 /*------------------------------------------------------------------------------- */
1325 * void relocate_code (addr_sp, gd, addr_moni)
1327 * This "function" does not return, instead it continues in RAM
1328 * after relocating the monitor code.
1330 * r3 = Relocated stack pointer
1331 * r4 = Relocated global data pointer
1332 * r5 = Relocated text pointer
1334 .globl relocate_code
1336 #if defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS)
1338 * We need to flush the initial global data (gd_t) before the dcache
1339 * will be invalidated.
1342 /* Save registers */
1347 /* Flush initial global data range */
1349 addi r4, r4, CFG_GBL_DATA_SIZE@l
1350 bl flush_dcache_range
1352 #if defined(CFG_INIT_DCACHE_CS)
1354 * Undo the earlier data cache set-up for the primordial stack and
1355 * data area. First, invalidate the data cache and then disable data
1356 * cacheability for that area. Finally, restore the EBC values, if
1360 /* Invalidate the primordial stack and data area in cache */
1361 lis r3, CFG_INIT_RAM_ADDR@h
1362 ori r3, r3, CFG_INIT_RAM_ADDR@l
1364 lis r4, CFG_INIT_RAM_END@h
1365 ori r4, r4, CFG_INIT_RAM_END@l
1368 bl invalidate_dcache_range
1370 /* Disable cacheability for the region */
1372 lis r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h
1373 ori r4, r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l
1377 /* Restore the EBC parameters */
1381 ori r3, r3, PBxAP_VAL@l
1387 ori r3, r3, PBxCR_VAL@l
1389 #endif /* defined(CFG_INIT_DCACHE_CS) */
1391 /* Restore registers */
1395 #endif /* defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS) */
1397 #ifdef CFG_INIT_RAM_DCACHE
1399 * Unlock the previously locked d-cache
1403 /* set TFLOOR/NFLOOR to 0 again */
1419 #endif /* CFG_INIT_RAM_DCACHE */
1421 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1422 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1423 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
1424 defined(CONFIG_460EX) || defined(CONFIG_460GT)
1426 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1427 * to speed up the boot process. Now this cache needs to be disabled.
1429 iccci 0,0 /* Invalidate inst cache */
1430 dccci 0,0 /* Invalidate data cache, now no longer our stack */
1433 #ifdef CFG_TLB_FOR_BOOT_FLASH
1434 addi r1,r0,CFG_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1436 addi r1,r0,0x0000 /* Default TLB entry is #0 */
1437 #endif /* CFG_TLB_FOR_BOOT_FLASH */
1438 tlbre r0,r1,0x0002 /* Read contents */
1439 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1440 tlbwe r0,r1,0x0002 /* Save it out */
1443 #endif /* defined(CONFIG_440EP) || ... || defined(CONFIG_460GT) */
1444 mr r1, r3 /* Set new stack pointer */
1445 mr r9, r4 /* Save copy of Init Data pointer */
1446 mr r10, r5 /* Save copy of Destination Address */
1448 mr r3, r5 /* Destination Address */
1449 lis r4, CFG_MONITOR_BASE@h /* Source Address */
1450 ori r4, r4, CFG_MONITOR_BASE@l
1451 lwz r5, GOT(__init_end)
1453 li r6, L1_CACHE_BYTES /* Cache Line Size */
1458 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
1464 /* First our own GOT */
1466 /* then the one used by the C code */
1476 beq cr1,4f /* In place copy is not necessary */
1477 beq 7f /* Protect against 0 count */
1496 * Now flush the cache: note that we must start from a cache aligned
1497 * address. Otherwise we might miss one cache line.
1501 beq 7f /* Always flush prefetch queue in any case */
1509 sync /* Wait for all dcbst to complete on bus */
1515 7: sync /* Wait for all icbi to complete on bus */
1519 * We are done. Do not return, instead branch to second part of board
1520 * initialization, now running from RAM.
1523 addi r0, r10, in_ram - _start + _START_OFFSET
1525 blr /* NEVER RETURNS! */
1530 * Relocation Function, r14 point to got2+0x8000
1532 * Adjust got2 pointers, no need to check for 0, this code
1533 * already puts a few entries in the table.
1535 li r0,__got2_entries@sectoff@l
1536 la r3,GOT(_GOT2_TABLE_)
1537 lwz r11,GOT(_GOT2_TABLE_)
1547 * Now adjust the fixups and the pointers to the fixups
1548 * in case we need to move ourselves again.
1550 2: li r0,__fixup_entries@sectoff@l
1551 lwz r3,GOT(_FIXUP_TABLE_)
1565 * Now clear BSS segment
1567 lwz r3,GOT(__bss_start)
1590 mr r3, r9 /* Init Data pointer */
1591 mr r4, r10 /* Destination Address */
1595 * Copy exception vector code to low memory
1598 * r7: source address, r8: end address, r9: target address
1602 lwz r7, GOT(_start_of_vectors)
1603 lwz r8, GOT(_end_of_vectors)
1605 li r9, 0x100 /* reset vector always at 0x100 */
1608 bgelr /* return if r7>=r8 - just in case */
1610 mflr r4 /* save link register */
1620 * relocate `hdlr' and `int_return' entries
1622 li r7, .L_MachineCheck - _start + _START_OFFSET
1623 li r8, Alignment - _start + _START_OFFSET
1626 addi r7, r7, 0x100 /* next exception vector */
1630 li r7, .L_Alignment - _start + _START_OFFSET
1633 li r7, .L_ProgramCheck - _start + _START_OFFSET
1637 li r7, .L_FPUnavailable - _start + _START_OFFSET
1640 li r7, .L_Decrementer - _start + _START_OFFSET
1643 li r7, .L_APU - _start + _START_OFFSET
1646 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1649 li r7, .L_DataTLBError - _start + _START_OFFSET
1651 #else /* CONFIG_440 */
1652 li r7, .L_PIT - _start + _START_OFFSET
1655 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1658 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1660 #endif /* CONFIG_440 */
1662 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1665 #if !defined(CONFIG_440)
1666 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1667 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1668 mtmsr r7 /* change MSR */
1671 b __440_msr_continue
1674 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1675 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1683 mtlr r4 /* restore link register */
1687 * Function: relocate entries for one exception vector
1690 lwz r0, 0(r7) /* hdlr ... */
1691 add r0, r0, r3 /* ... += dest_addr */
1694 lwz r0, 4(r7) /* int_return ... */
1695 add r0, r0, r3 /* ... += dest_addr */
1700 #if defined(CONFIG_440)
1701 /*----------------------------------------------------------------------------+
1703 +----------------------------------------------------------------------------*/
1704 function_prolog(dcbz_area)
1705 rlwinm. r5,r4,0,27,31
1706 rlwinm r5,r4,27,5,31
1715 function_epilog(dcbz_area)
1716 #endif /* CONFIG_440 */
1717 #endif /* CONFIG_NAND_SPL */
1719 /*------------------------------------------------------------------------------- */
1721 /* Description: Input 8 bits */
1722 /*------------------------------------------------------------------------------- */
1728 /*------------------------------------------------------------------------------- */
1729 /* Function: out8 */
1730 /* Description: Output 8 bits */
1731 /*------------------------------------------------------------------------------- */
1737 /*------------------------------------------------------------------------------- */
1738 /* Function: out32 */
1739 /* Description: Output 32 bits */
1740 /*------------------------------------------------------------------------------- */
1746 /*------------------------------------------------------------------------------- */
1747 /* Function: in32 */
1748 /* Description: Input 32 bits */
1749 /*------------------------------------------------------------------------------- */
1755 /**************************************************************************/
1756 /* PPC405EP specific stuff */
1757 /**************************************************************************/
1761 #ifdef CONFIG_BUBINGA
1763 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1764 * function) to support FPGA and NVRAM accesses below.
1767 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1768 ori r3,r3,GPIO0_OSRH@l
1769 lis r4,CFG_GPIO0_OSRH@h
1770 ori r4,r4,CFG_GPIO0_OSRH@l
1773 ori r3,r3,GPIO0_OSRL@l
1774 lis r4,CFG_GPIO0_OSRL@h
1775 ori r4,r4,CFG_GPIO0_OSRL@l
1778 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1779 ori r3,r3,GPIO0_ISR1H@l
1780 lis r4,CFG_GPIO0_ISR1H@h
1781 ori r4,r4,CFG_GPIO0_ISR1H@l
1783 lis r3,GPIO0_ISR1L@h
1784 ori r3,r3,GPIO0_ISR1L@l
1785 lis r4,CFG_GPIO0_ISR1L@h
1786 ori r4,r4,CFG_GPIO0_ISR1L@l
1789 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1790 ori r3,r3,GPIO0_TSRH@l
1791 lis r4,CFG_GPIO0_TSRH@h
1792 ori r4,r4,CFG_GPIO0_TSRH@l
1795 ori r3,r3,GPIO0_TSRL@l
1796 lis r4,CFG_GPIO0_TSRL@h
1797 ori r4,r4,CFG_GPIO0_TSRL@l
1800 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1801 ori r3,r3,GPIO0_TCR@l
1802 lis r4,CFG_GPIO0_TCR@h
1803 ori r4,r4,CFG_GPIO0_TCR@l
1806 li r3,pb1ap /* program EBC bank 1 for RTC access */
1808 lis r3,CFG_EBC_PB1AP@h
1809 ori r3,r3,CFG_EBC_PB1AP@l
1813 lis r3,CFG_EBC_PB1CR@h
1814 ori r3,r3,CFG_EBC_PB1CR@l
1817 li r3,pb1ap /* program EBC bank 1 for RTC access */
1819 lis r3,CFG_EBC_PB1AP@h
1820 ori r3,r3,CFG_EBC_PB1AP@l
1824 lis r3,CFG_EBC_PB1CR@h
1825 ori r3,r3,CFG_EBC_PB1CR@l
1828 li r3,pb4ap /* program EBC bank 4 for FPGA access */
1830 lis r3,CFG_EBC_PB4AP@h
1831 ori r3,r3,CFG_EBC_PB4AP@l
1835 lis r3,CFG_EBC_PB4CR@h
1836 ori r3,r3,CFG_EBC_PB4CR@l
1841 !-----------------------------------------------------------------------
1842 ! Check to see if chip is in bypass mode.
1843 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1844 ! CPU reset Otherwise, skip this step and keep going.
1845 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1846 ! will not be fast enough for the SDRAM (min 66MHz)
1847 !-----------------------------------------------------------------------
1849 mfdcr r5, CPC0_PLLMR1
1850 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1853 beq pll_done /* if SSCS =b'1' then PLL has */
1854 /* already been set */
1855 /* and CPU has been reset */
1856 /* so skip to next section */
1858 #ifdef CONFIG_BUBINGA
1860 !-----------------------------------------------------------------------
1861 ! Read NVRAM to get value to write in PLLMR.
1862 ! If value has not been correctly saved, write default value
1863 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1864 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1866 ! WARNING: This code assumes the first three words in the nvram_t
1867 ! structure in openbios.h. Changing the beginning of
1868 ! the structure will break this code.
1870 !-----------------------------------------------------------------------
1872 addis r3,0,NVRAM_BASE@h
1873 addi r3,r3,NVRAM_BASE@l
1876 addis r5,0,NVRVFY1@h
1877 addi r5,r5,NVRVFY1@l
1878 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1882 addis r5,0,NVRVFY2@h
1883 addi r5,r5,NVRVFY2@l
1884 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1886 addi r3,r3,8 /* Skip over conf_size */
1887 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1888 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1889 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1890 cmpi cr0,0,r5,1 /* See if PLL is locked */
1893 #endif /* CONFIG_BUBINGA */
1897 andi. r5, r4, CPC0_BOOT_SEP@l
1898 bne strap_1 /* serial eeprom present */
1899 addis r5,0,CPLD_REG0_ADDR@h
1900 ori r5,r5,CPLD_REG0_ADDR@l
1903 #endif /* CONFIG_TAIHU */
1905 #if defined(CONFIG_ZEUS)
1907 andi. r5, r4, CPC0_BOOT_SEP@l
1908 bne strap_1 /* serial eeprom present */
1915 mfdcr r3, CPC0_PLLMR0
1916 mfdcr r4, CPC0_PLLMR1
1920 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1921 ori r3,r3,PLLMR0_DEFAULT@l /* */
1922 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1923 ori r4,r4,PLLMR1_DEFAULT@l /* */
1928 addis r3,0,PLLMR0_DEFAULT_PCI66@h
1929 ori r3,r3,PLLMR0_DEFAULT_PCI66@l
1930 addis r4,0,PLLMR1_DEFAULT_PCI66@h
1931 ori r4,r4,PLLMR1_DEFAULT_PCI66@l
1934 mfdcr r3, CPC0_PLLMR0
1935 mfdcr r4, CPC0_PLLMR1
1936 #endif /* CONFIG_TAIHU */
1939 b pll_write /* Write the CPC0_PLLMR with new value */
1943 !-----------------------------------------------------------------------
1944 ! Clear Soft Reset Register
1945 ! This is needed to enable PCI if not booting from serial EPROM
1946 !-----------------------------------------------------------------------
1956 blr /* return to main code */
1959 !-----------------------------------------------------------------------------
1960 ! Function: pll_write
1961 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1963 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
1965 ! 3. Clock dividers are set while PLL is held in reset and bypassed
1966 ! 4. PLL Reset is cleared
1967 ! 5. Wait 100us for PLL to lock
1968 ! 6. A core reset is performed
1969 ! Input: r3 = Value to write to CPC0_PLLMR0
1970 ! Input: r4 = Value to write to CPC0_PLLMR1
1972 !-----------------------------------------------------------------------------
1977 ori r5,r5,0x0101 /* Stop the UART clocks */
1978 mtdcr CPC0_UCR,r5 /* Before changing PLL */
1980 mfdcr r5, CPC0_PLLMR1
1981 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
1982 mtdcr CPC0_PLLMR1,r5
1983 oris r5,r5,0x4000 /* Set PLL Reset */
1984 mtdcr CPC0_PLLMR1,r5
1986 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
1987 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
1988 oris r5,r5,0x4000 /* Set PLL Reset */
1989 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
1990 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
1991 mtdcr CPC0_PLLMR1,r5
1994 ! Wait min of 100us for PLL to lock.
1995 ! See CMOS 27E databook for more info.
1996 ! At 200MHz, that means waiting 20,000 instructions
1998 addi r3,0,20000 /* 2000 = 0x4e20 */
2003 oris r5,r5,0x8000 /* Enable PLL */
2004 mtdcr CPC0_PLLMR1,r5 /* Engage */
2007 * Reset CPU to guarantee timings are OK
2008 * Not sure if this is needed...
2011 mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
2012 /* execution will continue from the poweron */
2013 /* vector of 0xfffffffc */
2014 #endif /* CONFIG_405EP */
2016 #if defined(CONFIG_440)
2017 /*----------------------------------------------------------------------------+
2019 +----------------------------------------------------------------------------*/
2020 function_prolog(mttlb3)
2023 function_epilog(mttlb3)
2025 /*----------------------------------------------------------------------------+
2027 +----------------------------------------------------------------------------*/
2028 function_prolog(mftlb3)
2031 function_epilog(mftlb3)
2033 /*----------------------------------------------------------------------------+
2035 +----------------------------------------------------------------------------*/
2036 function_prolog(mttlb2)
2039 function_epilog(mttlb2)
2041 /*----------------------------------------------------------------------------+
2043 +----------------------------------------------------------------------------*/
2044 function_prolog(mftlb2)
2047 function_epilog(mftlb2)
2049 /*----------------------------------------------------------------------------+
2051 +----------------------------------------------------------------------------*/
2052 function_prolog(mttlb1)
2055 function_epilog(mttlb1)
2057 /*----------------------------------------------------------------------------+
2059 +----------------------------------------------------------------------------*/
2060 function_prolog(mftlb1)
2063 function_epilog(mftlb1)
2064 #endif /* CONFIG_440 */
2066 #if defined(CONFIG_NAND_SPL)
2068 * void nand_boot_relocate(dst, src, bytes)
2070 * r3 = Destination address to copy code to (in SDRAM)
2071 * r4 = Source address to copy code from
2072 * r5 = size to copy in bytes
2080 * Copy SPL from icache into SDRAM
2092 * Calculate "corrected" link register, so that we "continue"
2093 * in execution in destination range
2095 sub r3,r7,r6 /* r3 = src - dst */
2096 sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
2102 * First initialize SDRAM. It has to be available *before* calling
2105 lis r3,CFG_SDRAM_BASE@h
2106 ori r3,r3,CFG_SDRAM_BASE@l
2110 * Now copy the 4k SPL code into SDRAM and continue execution
2113 lis r3,CFG_NAND_BOOT_SPL_DST@h
2114 ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
2115 lis r4,CFG_NAND_BOOT_SPL_SRC@h
2116 ori r4,r4,CFG_NAND_BOOT_SPL_SRC@l
2117 lis r5,CFG_NAND_BOOT_SPL_SIZE@h
2118 ori r5,r5,CFG_NAND_BOOT_SPL_SIZE@l
2119 bl nand_boot_relocate
2122 * We're running from SDRAM now!!!
2124 * It is necessary for 4xx systems to relocate from running at
2125 * the original location (0xfffffxxx) to somewhere else (SDRAM
2126 * preferably). This is because CS0 needs to be reconfigured for
2127 * NAND access. And we can't reconfigure this CS when currently
2128 * "running" from it.
2132 * Finally call nand_boot() to load main NAND U-Boot image from
2133 * NAND and jump to it.
2135 bl nand_boot /* will not return */
2136 #endif /* CONFIG_NAND_SPL */