2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright (c) 2008 Nuovation System Designs, LLC
7 * Grant Erickson <gerickson@nuovations.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 /*------------------------------------------------------------------------------+
29 * This source code has been made available to you by IBM on an AS-IS
30 * basis. Anyone receiving this source is licensed under IBM
31 * copyrights to use it in any way he or she deems fit, including
32 * copying it, modifying it, compiling it, and redistributing it either
33 * with or without modifications. No license under IBM patents or
34 * patent applications is to be implied by the copyright license.
36 * Any user of this software should understand that IBM cannot provide
37 * technical support for this software and will not be responsible for
38 * any consequences resulting from the use of this software.
40 * Any person who transfers this source code or any derivative work
41 * must include the IBM copyright notice, this paragraph, and the
42 * preceding two paragraphs in the transferred software.
44 * COPYRIGHT I B M CORPORATION 1995
45 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
46 *-------------------------------------------------------------------------------
49 /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
52 * The processor starts at 0xfffffffc and the code is executed
54 * in memory, but as long we don't jump around before relocating.
55 * board_init lies at a quite high address and when the cpu has
56 * jumped there, everything is ok.
57 * This works because the cpu gives the FLASH (CS0) the whole
58 * address space at startup, and board_init lies as a echo of
59 * the flash somewhere up there in the memorymap.
61 * board_init will change CS0 to be positioned at the correct
62 * address and (s)dram will be positioned at address 0
66 #include <timestamp.h>
69 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
71 #include <ppc_asm.tmpl>
74 #include <asm/cache.h>
76 #include <asm/ppc4xx-isram.h>
78 #ifndef CONFIG_IDENT_STRING
79 #define CONFIG_IDENT_STRING ""
82 #ifdef CONFIG_SYS_INIT_DCACHE_CS
83 # if (CONFIG_SYS_INIT_DCACHE_CS == 0)
86 # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
87 # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
88 # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
91 # if (CONFIG_SYS_INIT_DCACHE_CS == 1)
94 # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
95 # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
96 # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
99 # if (CONFIG_SYS_INIT_DCACHE_CS == 2)
102 # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
103 # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
104 # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
107 # if (CONFIG_SYS_INIT_DCACHE_CS == 3)
110 # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
111 # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
112 # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
115 # if (CONFIG_SYS_INIT_DCACHE_CS == 4)
118 # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
119 # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
120 # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
123 # if (CONFIG_SYS_INIT_DCACHE_CS == 5)
126 # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
127 # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
128 # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
131 # if (CONFIG_SYS_INIT_DCACHE_CS == 6)
134 # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
135 # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
136 # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
139 # if (CONFIG_SYS_INIT_DCACHE_CS == 7)
142 # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
143 # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
144 # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
154 * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
155 * used as temporary stack pointer for the primordial stack
157 # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
158 # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
159 EBC_BXAP_TWT_ENCODE(7) | \
160 EBC_BXAP_BCE_DISABLE | \
161 EBC_BXAP_BCT_2TRANS | \
162 EBC_BXAP_CSN_ENCODE(0) | \
163 EBC_BXAP_OEN_ENCODE(0) | \
164 EBC_BXAP_WBN_ENCODE(0) | \
165 EBC_BXAP_WBF_ENCODE(0) | \
166 EBC_BXAP_TH_ENCODE(2) | \
167 EBC_BXAP_RE_DISABLED | \
168 EBC_BXAP_SOR_NONDELAYED | \
169 EBC_BXAP_BEM_WRITEONLY | \
170 EBC_BXAP_PEN_DISABLED)
171 # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
172 # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
173 # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \
177 # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
178 # ifndef CONFIG_SYS_INIT_RAM_PATTERN
179 # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD
181 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
183 #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10)))
184 #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END!
188 * Unless otherwise overriden, enable two 128MB cachable instruction regions
189 * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
190 * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
192 #if !defined(CONFIG_SYS_FLASH_BASE)
193 /* If not already defined, set it to the "last" 128MByte region */
194 # define CONFIG_SYS_FLASH_BASE 0xf8000000
196 #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
197 # define CONFIG_SYS_ICACHE_SACR_VALUE \
198 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
199 PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
200 PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
201 #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
203 #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
204 # define CONFIG_SYS_DCACHE_SACR_VALUE \
206 #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
208 #define function_prolog(func_name) .text; \
212 #define function_epilog(func_name) .type func_name,@function; \
213 .size func_name,.-func_name
215 /* We don't want the MMU yet.
218 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
221 .extern ext_bus_cntlr_init
222 #ifdef CONFIG_NAND_U_BOOT
223 .extern reconfig_tlb0
227 * Set up GOT: Global Offset Table
229 * Use r14 to access the GOT
231 #if !defined(CONFIG_NAND_SPL)
233 GOT_ENTRY(_GOT2_TABLE_)
234 GOT_ENTRY(_FIXUP_TABLE_)
237 GOT_ENTRY(_start_of_vectors)
238 GOT_ENTRY(_end_of_vectors)
239 GOT_ENTRY(transfer_to_handler)
241 GOT_ENTRY(__init_end)
243 GOT_ENTRY(__bss_start)
245 #endif /* CONFIG_NAND_SPL */
247 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
249 * NAND U-Boot image is started from offset 0
252 #if defined(CONFIG_440)
256 bl cpu_init_f /* run low-level CPU init code (from Flash) */
261 * 440 Startup -- on reset only the top 4k of the effective
262 * address space is mapped in by an entry in the instruction
263 * and data shadow TLB. The .bootpg section is located in the
264 * top 4k & does only what's necessary to map in the the rest
265 * of the boot rom. Once the boot rom is mapped in we can
266 * proceed with normal startup.
268 * NOTE: CS0 only covers the top 2MB of the effective address
272 #if defined(CONFIG_440)
273 #if !defined(CONFIG_NAND_SPL)
274 .section .bootpg,"ax"
278 /**************************************************************************/
280 /*--------------------------------------------------------------------+
281 | 440EPX BUP Change - Hardware team request
282 +--------------------------------------------------------------------*/
283 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
288 /*----------------------------------------------------------------+
289 | Core bug fix. Clear the esr
290 +-----------------------------------------------------------------*/
293 /*----------------------------------------------------------------*/
294 /* Clear and set up some registers. */
295 /*----------------------------------------------------------------*/
296 iccci r0,r0 /* NOTE: operands not used for 440 */
297 dccci r0,r0 /* NOTE: operands not used for 440 */
304 /* NOTE: 440GX adds machine check status regs */
305 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
312 /*----------------------------------------------------------------*/
314 /*----------------------------------------------------------------*/
315 /* Disable store gathering & broadcast, guarantee inst/data
316 * cache block touch, force load/store alignment
317 * (see errata 1.12: 440_33)
319 lis r1,0x0030 /* store gathering & broadcast disable */
320 ori r1,r1,0x6000 /* cache touch */
323 /*----------------------------------------------------------------*/
324 /* Initialize debug */
325 /*----------------------------------------------------------------*/
327 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
328 bne skip_debug_init /* if set, don't clear debug register */
341 mtspr dbsr,r1 /* Clear all valid bits */
344 #if defined (CONFIG_440SPE)
345 /*----------------------------------------------------------------+
346 | Initialize Core Configuration Reg1.
347 | a. ICDPEI: Record even parity. Normal operation.
348 | b. ICTPEI: Record even parity. Normal operation.
349 | c. DCTPEI: Record even parity. Normal operation.
350 | d. DCDPEI: Record even parity. Normal operation.
351 | e. DCUPEI: Record even parity. Normal operation.
352 | f. DCMPEI: Record even parity. Normal operation.
353 | g. FCOM: Normal operation
354 | h. MMUPEI: Record even parity. Normal operation.
355 | i. FFF: Flush only as much data as necessary.
356 | j. TCS: Timebase increments from CPU clock.
357 +-----------------------------------------------------------------*/
361 /*----------------------------------------------------------------+
362 | Reset the timebase.
363 | The previous write to CCR1 sets the timebase source.
364 +-----------------------------------------------------------------*/
369 /*----------------------------------------------------------------*/
370 /* Setup interrupt vectors */
371 /*----------------------------------------------------------------*/
372 mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */
374 mtspr ivor0,r1 /* Critical input */
376 mtspr ivor1,r1 /* Machine check */
378 mtspr ivor2,r1 /* Data storage */
380 mtspr ivor3,r1 /* Instruction storage */
382 mtspr ivor4,r1 /* External interrupt */
384 mtspr ivor5,r1 /* Alignment */
386 mtspr ivor6,r1 /* Program check */
388 mtspr ivor7,r1 /* Floating point unavailable */
390 mtspr ivor8,r1 /* System call */
392 mtspr ivor9,r1 /* Auxiliary Processor unavailable */
394 mtspr ivor10,r1 /* Decrementer */
396 mtspr ivor13,r1 /* Data TLB error */
398 mtspr ivor14,r1 /* Instr TLB error */
400 mtspr ivor15,r1 /* Debug */
402 /*----------------------------------------------------------------*/
403 /* Configure cache regions */
404 /*----------------------------------------------------------------*/
422 /*----------------------------------------------------------------*/
423 /* Cache victim limits */
424 /*----------------------------------------------------------------*/
425 /* floors 0, ceiling max to use the entire cache -- nothing locked
432 /*----------------------------------------------------------------+
433 |Initialize MMUCR[STID] = 0.
434 +-----------------------------------------------------------------*/
441 /*----------------------------------------------------------------*/
442 /* Clear all TLB entries -- TID = 0, TS = 0 */
443 /*----------------------------------------------------------------*/
445 li r1,0x003f /* 64 TLB entries */
447 rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
453 /*----------------------------------------------------------------*/
454 /* TLB entry setup -- step thru tlbtab */
455 /*----------------------------------------------------------------*/
456 #if defined(CONFIG_440SPE)
457 /*----------------------------------------------------------------*/
458 /* We have different TLB tables for revA and rev B of 440SPe */
459 /*----------------------------------------------------------------*/
471 bl tlbtab /* Get tlbtab pointer */
474 li r1,0x003f /* 64 TLB entries max */
481 beq 2f /* 0 marks end */
484 tlbwe r0,r4,0 /* TLB Word 0 */
485 tlbwe r1,r4,1 /* TLB Word 1 */
486 tlbwe r2,r4,2 /* TLB Word 2 */
487 addi r4,r4,1 /* Next TLB */
490 /*----------------------------------------------------------------*/
491 /* Continue from 'normal' start */
492 /*----------------------------------------------------------------*/
498 mtspr srr1,r0 /* Keep things disabled for now */
502 #endif /* CONFIG_440 */
505 * r3 - 1st arg to board_init(): IMMP pointer
506 * r4 - 2nd arg to board_init(): boot flag
508 #ifndef CONFIG_NAND_SPL
510 .long 0x27051956 /* U-Boot Magic Number */
511 .globl version_string
513 .ascii U_BOOT_VERSION
514 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
515 .ascii CONFIG_IDENT_STRING, "\0"
517 . = EXC_OFF_SYS_RESET
518 .globl _start_of_vectors
521 /* Critical input. */
522 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
526 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
528 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
529 #endif /* CONFIG_440 */
531 /* Data Storage exception. */
532 STD_EXCEPTION(0x300, DataStorage, UnknownException)
534 /* Instruction Storage exception. */
535 STD_EXCEPTION(0x400, InstStorage, UnknownException)
537 /* External Interrupt exception. */
538 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
540 /* Alignment exception. */
543 EXCEPTION_PROLOG(SRR0, SRR1)
548 addi r3,r1,STACK_FRAME_OVERHEAD
550 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
551 lwz r6,GOT(transfer_to_handler)
555 .long AlignmentException - _start + _START_OFFSET
556 .long int_return - _start + _START_OFFSET
558 /* Program check exception */
561 EXCEPTION_PROLOG(SRR0, SRR1)
562 addi r3,r1,STACK_FRAME_OVERHEAD
564 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
565 lwz r6,GOT(transfer_to_handler)
569 .long ProgramCheckException - _start + _START_OFFSET
570 .long int_return - _start + _START_OFFSET
573 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
574 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
575 STD_EXCEPTION(0xa00, APU, UnknownException)
577 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
580 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
581 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
583 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
584 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
585 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
587 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
589 .globl _end_of_vectors
596 /*****************************************************************************/
597 #if defined(CONFIG_440)
599 /*----------------------------------------------------------------*/
600 /* Clear and set up some registers. */
601 /*----------------------------------------------------------------*/
604 mtspr dec,r0 /* prevent dec exceptions */
605 mtspr tbl,r0 /* prevent fit & wdt exceptions */
607 mtspr tsr,r1 /* clear all timer exception status */
608 mtspr tcr,r0 /* disable all */
609 mtspr esr,r0 /* clear exception syndrome register */
610 mtxer r0 /* clear integer exception register */
612 /*----------------------------------------------------------------*/
613 /* Debug setup -- some (not very good) ice's need an event*/
614 /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
615 /* value you need in this case 0x8cff 0000 should do the trick */
616 /*----------------------------------------------------------------*/
617 #if defined(CONFIG_SYS_INIT_DBCR)
620 mtspr dbsr,r1 /* Clear all status bits */
621 lis r0,CONFIG_SYS_INIT_DBCR@h
622 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
627 /*----------------------------------------------------------------*/
628 /* Setup the internal SRAM */
629 /*----------------------------------------------------------------*/
632 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
633 /* Clear Dcache to use as RAM */
634 addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
635 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
636 addis r4,r0,CONFIG_SYS_INIT_RAM_END@h
637 ori r4,r4,CONFIG_SYS_INIT_RAM_END@l
638 rlwinm. r5,r4,0,27,31
650 * Lock the init-ram/stack in d-cache, so that other regions
651 * may use d-cache as well
652 * Note, that this current implementation locks exactly 4k
653 * of d-cache, so please make sure that you don't define a
654 * bigger init-ram area. Take a look at the lwmon5 440EPx
655 * implementation as a reference.
659 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
675 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
677 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
678 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
679 /* not all PPC's have internal SRAM usable as L2-cache */
680 #if defined(CONFIG_440GX) || \
681 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
682 defined(CONFIG_460SX)
683 mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
684 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
686 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
687 mtdcr L2_CACHE_CFG,r1
693 and r1,r1,r2 /* Disable parity check */
696 and r1,r1,r2 /* Disable pwr mgmt */
699 lis r1,0x8000 /* BAS = 8000_0000 */
700 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
701 ori r1,r1,0x0980 /* first 64k */
702 mtdcr ISRAM0_SB0CR,r1
704 ori r1,r1,0x0980 /* second 64k */
705 mtdcr ISRAM0_SB1CR,r1
707 ori r1,r1, 0x0980 /* third 64k */
708 mtdcr ISRAM0_SB2CR,r1
710 ori r1,r1, 0x0980 /* fourth 64k */
711 mtdcr ISRAM0_SB3CR,r1
712 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
713 lis r1,0x0000 /* BAS = X_0000_0000 */
714 ori r1,r1,0x0984 /* first 64k */
715 mtdcr ISRAM0_SB0CR,r1
717 ori r1,r1,0x0984 /* second 64k */
718 mtdcr ISRAM0_SB1CR,r1
720 ori r1,r1, 0x0984 /* third 64k */
721 mtdcr ISRAM0_SB2CR,r1
723 ori r1,r1, 0x0984 /* fourth 64k */
724 mtdcr ISRAM0_SB3CR,r1
725 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
729 and r1,r1,r2 /* Disable parity check */
732 and r1,r1,r2 /* Disable pwr mgmt */
735 lis r1,0x0004 /* BAS = 4_0004_0000 */
736 ori r1,r1,0x0984 /* 64k */
737 mtdcr ISRAM1_SB0CR,r1
739 #elif defined(CONFIG_460SX)
740 lis r1,0x0000 /* BAS = 0000_0000 */
741 ori r1,r1,0x0B84 /* first 128k */
742 mtdcr ISRAM0_SB0CR,r1
744 ori r1,r1,0x0B84 /* second 128k */
745 mtdcr ISRAM0_SB1CR,r1
747 ori r1,r1, 0x0B84 /* third 128k */
748 mtdcr ISRAM0_SB2CR,r1
750 ori r1,r1, 0x0B84 /* fourth 128k */
751 mtdcr ISRAM0_SB3CR,r1
752 #elif defined(CONFIG_440GP)
753 ori r1,r1,0x0380 /* 8k rw */
754 mtdcr ISRAM0_SB0CR,r1
755 mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
757 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
759 /*----------------------------------------------------------------*/
760 /* Setup the stack in internal SRAM */
761 /*----------------------------------------------------------------*/
762 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
763 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
766 stwu r0,-4(r1) /* Terminate call chain */
768 stwu r1,-8(r1) /* Save back chain and move SP */
769 lis r0,RESET_VECTOR@h /* Address of reset vector */
770 ori r0,r0, RESET_VECTOR@l
771 stwu r1,-8(r1) /* Save back chain and move SP */
772 stw r0,+12(r1) /* Save return addr (underflow vect) */
774 #ifdef CONFIG_NAND_SPL
775 bl nand_boot_common /* will not return */
779 bl cpu_init_f /* run low-level CPU init code (from Flash) */
783 #endif /* CONFIG_440 */
785 /*****************************************************************************/
787 /*----------------------------------------------------------------------- */
788 /* Set up some machine state registers. */
789 /*----------------------------------------------------------------------- */
790 addi r0,r0,0x0000 /* initialize r0 to zero */
791 mtspr esr,r0 /* clear Exception Syndrome Reg */
792 mttcr r0 /* timer control register */
793 mtexier r0 /* disable all interrupts */
794 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
795 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
796 mtdbsr r4 /* clear/reset the dbsr */
797 mtexisr r4 /* clear all pending interrupts */
799 mtexier r4 /* enable critical exceptions */
800 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
801 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
802 mtiocr r4 /* since bit not used) & DRC to latch */
803 /* data bus on rising edge of CAS */
804 /*----------------------------------------------------------------------- */
806 /*----------------------------------------------------------------------- */
808 /*----------------------------------------------------------------------- */
809 /* Invalidate i-cache and d-cache TAG arrays. */
810 /*----------------------------------------------------------------------- */
811 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
812 addi r4,0,1024 /* 1/4 of I-cache */
817 addic. r3,r3,-16 /* move back one cache line */
818 bne ..cloop /* loop back to do rest until r3 = 0 */
821 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
822 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
825 /* first copy IOP480 register base address into r3 */
826 addis r3,0,0x5000 /* IOP480 register base address hi */
827 /* ori r3,r3,0x0000 / IOP480 register base address lo */
830 /* use r4 as the working variable */
831 /* turn on CS3 (LOCCTL.7) */
832 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
833 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
834 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
837 #ifdef CONFIG_DASA_SIM
838 /* use r4 as the working variable */
839 /* turn on MA17 (LOCCTL.7) */
840 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
841 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
842 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
845 /* turn on MA16..13 (LCS0BRD.12 = 0) */
846 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
847 andi. r4,r4,0xefff /* make bit 12 = 0 */
848 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
850 /* make sure above stores all comlete before going on */
853 /* last thing, set local init status done bit (DEVINIT.31) */
854 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
855 oris r4,r4,0x8000 /* make bit 31 = 1 */
856 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
858 /* clear all pending interrupts and disable all interrupts */
859 li r4,-1 /* set p1 to 0xffffffff */
860 stw r4,0x1b0(r3) /* clear all pending interrupts */
861 stw r4,0x1b8(r3) /* clear all pending interrupts */
862 li r4,0 /* set r4 to 0 */
863 stw r4,0x1b4(r3) /* disable all interrupts */
864 stw r4,0x1bc(r3) /* disable all interrupts */
866 /* make sure above stores all comlete before going on */
869 /* Set-up icache cacheability. */
870 lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h
871 ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l
875 /* Set-up dcache cacheability. */
876 lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h
877 ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l
880 addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h
881 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */
882 li r0, 0 /* Make room for stack frame header and */
883 stwu r0, -4(r1) /* clear final stack frame so that */
884 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
886 GET_GOT /* initialize GOT access */
888 bl board_init_f /* run first part of init code (from Flash) */
890 #endif /* CONFIG_IOP480 */
892 /*****************************************************************************/
893 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
894 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
895 defined(CONFIG_405EX) || defined(CONFIG_405)
896 /*----------------------------------------------------------------------- */
897 /* Clear and set up some registers. */
898 /*----------------------------------------------------------------------- */
900 #if !defined(CONFIG_405EX)
904 * On 405EX, completely clearing the SGR leads to PPC hangup
905 * upon PCIe configuration access. The PCIe memory regions
906 * need to be guarded!
913 mtesr r4 /* clear Exception Syndrome Reg */
914 mttcr r4 /* clear Timer Control Reg */
915 mtxer r4 /* clear Fixed-Point Exception Reg */
916 mtevpr r4 /* clear Exception Vector Prefix Reg */
917 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
918 /* dbsr is cleared by setting bits to 1) */
919 mtdbsr r4 /* clear/reset the dbsr */
921 /* Invalidate the i- and d-caches. */
925 /* Set-up icache cacheability. */
926 lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
927 ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
931 /* Set-up dcache cacheability. */
932 lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
933 ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
936 #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
937 && !defined (CONFIG_XILINX_405)
938 /*----------------------------------------------------------------------- */
939 /* Tune the speed and size for flash CS0 */
940 /*----------------------------------------------------------------------- */
941 bl ext_bus_cntlr_init
944 #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
946 * For boards that don't have OCM and can't use the data cache
947 * for their primordial stack, setup stack here directly after the
948 * SDRAM is initialized in ext_bus_cntlr_init.
950 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
951 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
953 li r0, 0 /* Make room for stack frame header and */
954 stwu r0, -4(r1) /* clear final stack frame so that */
955 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
957 * Set up a dummy frame to store reset vector as return address.
958 * this causes stack underflow to reset board.
960 stwu r1, -8(r1) /* Save back chain and move SP */
961 lis r0, RESET_VECTOR@h /* Address of reset vector */
962 ori r0, r0, RESET_VECTOR@l
963 stwu r1, -8(r1) /* Save back chain and move SP */
964 stw r0, +12(r1) /* Save return addr (underflow vect) */
965 #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
967 #if defined(CONFIG_405EP)
968 /*----------------------------------------------------------------------- */
969 /* DMA Status, clear to come up clean */
970 /*----------------------------------------------------------------------- */
971 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
975 bl ppc405ep_init /* do ppc405ep specific init */
976 #endif /* CONFIG_405EP */
978 #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
979 #if defined(CONFIG_405EZ)
980 /********************************************************************
981 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
982 *******************************************************************/
984 * We can map the OCM on the PLB3, so map it at
985 * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
987 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
988 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
989 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
990 mtdcr ocmplb3cr1,r3 /* Set PLB Access */
991 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
992 mtdcr ocmplb3cr2,r3 /* Set PLB Access */
995 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
996 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
997 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
998 mtdcr ocmdscr1, r3 /* Set Data Side */
999 mtdcr ocmiscr1, r3 /* Set Instruction Side */
1000 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
1001 mtdcr ocmdscr2, r3 /* Set Data Side */
1002 mtdcr ocmiscr2, r3 /* Set Instruction Side */
1003 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
1007 #else /* CONFIG_405EZ */
1008 /********************************************************************
1009 * Setup OCM - On Chip Memory
1010 *******************************************************************/
1014 mfdcr r3, ocmiscntl /* get instr-side IRAM config */
1015 mfdcr r4, ocmdscntl /* get data-side IRAM config */
1016 and r3, r3, r0 /* disable data-side IRAM */
1017 and r4, r4, r0 /* disable data-side IRAM */
1018 mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
1019 mtdcr ocmdscntl, r4 /* set data-side IRAM config */
1022 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1023 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1025 addis r4, 0, 0xC000 /* OCM data area enabled */
1028 #endif /* CONFIG_405EZ */
1031 /*----------------------------------------------------------------------- */
1032 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
1033 /*----------------------------------------------------------------------- */
1034 #ifdef CONFIG_SYS_INIT_DCACHE_CS
1037 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
1038 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
1043 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
1044 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
1048 * Enable the data cache for the 128MB storage access control region
1049 * at CONFIG_SYS_INIT_RAM_ADDR.
1052 oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1053 ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1057 * Preallocate data cache lines to be used to avoid a subsequent
1058 * cache miss and an ensuing machine check exception when exceptions
1063 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1064 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1066 lis r4, CONFIG_SYS_INIT_RAM_END@h
1067 ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
1070 * Convert the size, in bytes, to the number of cache lines/blocks
1073 clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
1074 srwi r5, r4, L1_CACHE_SHIFT
1080 /* Preallocate the computed number of cache blocks. */
1081 ..alloc_dcache_block:
1083 addi r3, r3, L1_CACHE_BYTES
1084 bdnz ..alloc_dcache_block
1088 * Load the initial stack pointer and data area and convert the size,
1089 * in bytes, to the number of words to initialize to a known value.
1091 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
1092 ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
1094 lis r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h
1095 ori r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l
1098 lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
1099 ori r2, r2, CONFIG_SYS_INIT_RAM_END@l
1101 lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
1102 ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
1109 * Make room for stack frame header and clear final stack frame so
1110 * that stack backtraces terminate cleanly.
1116 * Set up a dummy frame to store reset vector as return address.
1117 * this causes stack underflow to reset board.
1119 stwu r1, -8(r1) /* Save back chain and move SP */
1120 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1121 ori r0, r0, RESET_VECTOR@l
1122 stwu r1, -8(r1) /* Save back chain and move SP */
1123 stw r0, +12(r1) /* Save return addr (underflow vect) */
1125 #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
1126 (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
1131 /* Set up Stack at top of OCM */
1132 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
1133 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
1135 /* Set up a zeroized stack frame so that backtrace works right */
1141 * Set up a dummy frame to store reset vector as return address.
1142 * this causes stack underflow to reset board.
1144 stwu r1, -8(r1) /* Save back chain and move SP */
1145 lis r0, RESET_VECTOR@h /* Address of reset vector */
1146 ori r0, r0, RESET_VECTOR@l
1147 stwu r1, -8(r1) /* Save back chain and move SP */
1148 stw r0, +12(r1) /* Save return addr (underflow vect) */
1149 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
1151 #ifdef CONFIG_NAND_SPL
1152 bl nand_boot_common /* will not return */
1154 GET_GOT /* initialize GOT access */
1156 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1158 /* NEVER RETURNS! */
1159 bl board_init_f /* run first part of init code (from Flash) */
1160 #endif /* CONFIG_NAND_SPL */
1162 #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1163 /*----------------------------------------------------------------------- */
1166 #ifndef CONFIG_NAND_SPL
1168 * This code finishes saving the registers to the exception frame
1169 * and jumps to the appropriate handler for the exception.
1170 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1172 .globl transfer_to_handler
1173 transfer_to_handler:
1183 andi. r24,r23,0x3f00 /* get vector offset */
1187 mtspr SPRG2,r22 /* r1 is now kernel sp */
1188 lwz r24,0(r23) /* virtual address of handler */
1189 lwz r23,4(r23) /* where to go when done */
1194 rfi /* jump to handler, enable MMU */
1197 mfmsr r28 /* Disable interrupts */
1201 SYNC /* Some chip revs need this... */
1216 lwz r2,_NIP(r1) /* Restore environment */
1227 mfmsr r28 /* Disable interrupts */
1231 SYNC /* Some chip revs need this... */
1246 lwz r2,_NIP(r1) /* Restore environment */
1258 mfmsr r28 /* Disable interrupts */
1262 SYNC /* Some chip revs need this... */
1277 lwz r2,_NIP(r1) /* Restore environment */
1286 #endif /* CONFIG_440 */
1294 /*------------------------------------------------------------------------------- */
1295 /* Function: out16 */
1296 /* Description: Output 16 bits */
1297 /*------------------------------------------------------------------------------- */
1303 /*------------------------------------------------------------------------------- */
1304 /* Function: out16r */
1305 /* Description: Byte reverse and output 16 bits */
1306 /*------------------------------------------------------------------------------- */
1312 /*------------------------------------------------------------------------------- */
1313 /* Function: out32r */
1314 /* Description: Byte reverse and output 32 bits */
1315 /*------------------------------------------------------------------------------- */
1321 /*------------------------------------------------------------------------------- */
1322 /* Function: in16 */
1323 /* Description: Input 16 bits */
1324 /*------------------------------------------------------------------------------- */
1330 /*------------------------------------------------------------------------------- */
1331 /* Function: in16r */
1332 /* Description: Input 16 bits and byte reverse */
1333 /*------------------------------------------------------------------------------- */
1339 /*------------------------------------------------------------------------------- */
1340 /* Function: in32r */
1341 /* Description: Input 32 bits and byte reverse */
1342 /*------------------------------------------------------------------------------- */
1349 * void relocate_code (addr_sp, gd, addr_moni)
1351 * This "function" does not return, instead it continues in RAM
1352 * after relocating the monitor code.
1354 * r3 = Relocated stack pointer
1355 * r4 = Relocated global data pointer
1356 * r5 = Relocated text pointer
1358 .globl relocate_code
1360 #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
1362 * We need to flush the initial global data (gd_t) before the dcache
1363 * will be invalidated.
1366 /* Save registers */
1371 /* Flush initial global data range */
1373 addi r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l
1374 bl flush_dcache_range
1376 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
1378 * Undo the earlier data cache set-up for the primordial stack and
1379 * data area. First, invalidate the data cache and then disable data
1380 * cacheability for that area. Finally, restore the EBC values, if
1384 /* Invalidate the primordial stack and data area in cache */
1385 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1386 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1388 lis r4, CONFIG_SYS_INIT_RAM_END@h
1389 ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
1392 bl invalidate_dcache_range
1394 /* Disable cacheability for the region */
1396 lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1397 ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1401 /* Restore the EBC parameters */
1405 ori r3, r3, PBxAP_VAL@l
1411 ori r3, r3, PBxCR_VAL@l
1413 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
1415 /* Restore registers */
1419 #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
1421 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
1423 * Unlock the previously locked d-cache
1427 /* set TFLOOR/NFLOOR to 0 again */
1443 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
1445 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1446 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1447 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
1448 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1449 defined(CONFIG_460SX)
1451 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1452 * to speed up the boot process. Now this cache needs to be disabled.
1454 iccci 0,0 /* Invalidate inst cache */
1455 dccci 0,0 /* Invalidate data cache, now no longer our stack */
1459 /* Clear all potential pending exceptions */
1462 #ifdef CONFIG_SYS_TLB_FOR_BOOT_FLASH
1463 addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1465 addi r1,r0,0x0000 /* Default TLB entry is #0 */
1466 #endif /* CONFIG_SYS_TLB_FOR_BOOT_FLASH */
1467 tlbre r0,r1,0x0002 /* Read contents */
1468 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1469 tlbwe r0,r1,0x0002 /* Save it out */
1472 #endif /* defined(CONFIG_440EP) || ... || defined(CONFIG_460GT) */
1473 mr r1, r3 /* Set new stack pointer */
1474 mr r9, r4 /* Save copy of Init Data pointer */
1475 mr r10, r5 /* Save copy of Destination Address */
1477 mr r3, r5 /* Destination Address */
1478 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1479 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
1480 lwz r5, GOT(__init_end)
1482 li r6, L1_CACHE_BYTES /* Cache Line Size */
1487 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1493 /* First our own GOT */
1495 /* then the one used by the C code */
1505 beq cr1,4f /* In place copy is not necessary */
1506 beq 7f /* Protect against 0 count */
1525 * Now flush the cache: note that we must start from a cache aligned
1526 * address. Otherwise we might miss one cache line.
1530 beq 7f /* Always flush prefetch queue in any case */
1538 sync /* Wait for all dcbst to complete on bus */
1544 7: sync /* Wait for all icbi to complete on bus */
1548 * We are done. Do not return, instead branch to second part of board
1549 * initialization, now running from RAM.
1552 addi r0, r10, in_ram - _start + _START_OFFSET
1554 blr /* NEVER RETURNS! */
1559 * Relocation Function, r14 point to got2+0x8000
1561 * Adjust got2 pointers, no need to check for 0, this code
1562 * already puts a few entries in the table.
1564 li r0,__got2_entries@sectoff@l
1565 la r3,GOT(_GOT2_TABLE_)
1566 lwz r11,GOT(_GOT2_TABLE_)
1576 * Now adjust the fixups and the pointers to the fixups
1577 * in case we need to move ourselves again.
1579 2: li r0,__fixup_entries@sectoff@l
1580 lwz r3,GOT(_FIXUP_TABLE_)
1594 * Now clear BSS segment
1596 lwz r3,GOT(__bss_start)
1619 mr r3, r9 /* Init Data pointer */
1620 mr r4, r10 /* Destination Address */
1624 * Copy exception vector code to low memory
1627 * r7: source address, r8: end address, r9: target address
1631 lwz r7, GOT(_start_of_vectors)
1632 lwz r8, GOT(_end_of_vectors)
1634 li r9, 0x100 /* reset vector always at 0x100 */
1637 bgelr /* return if r7>=r8 - just in case */
1639 mflr r4 /* save link register */
1649 * relocate `hdlr' and `int_return' entries
1651 li r7, .L_MachineCheck - _start + _START_OFFSET
1652 li r8, Alignment - _start + _START_OFFSET
1655 addi r7, r7, 0x100 /* next exception vector */
1659 li r7, .L_Alignment - _start + _START_OFFSET
1662 li r7, .L_ProgramCheck - _start + _START_OFFSET
1666 li r7, .L_FPUnavailable - _start + _START_OFFSET
1669 li r7, .L_Decrementer - _start + _START_OFFSET
1672 li r7, .L_APU - _start + _START_OFFSET
1675 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1678 li r7, .L_DataTLBError - _start + _START_OFFSET
1680 #else /* CONFIG_440 */
1681 li r7, .L_PIT - _start + _START_OFFSET
1684 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1687 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1689 #endif /* CONFIG_440 */
1691 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1694 #if !defined(CONFIG_440)
1695 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1696 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1697 mtmsr r7 /* change MSR */
1700 b __440_msr_continue
1703 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1704 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1712 mtlr r4 /* restore link register */
1716 * Function: relocate entries for one exception vector
1719 lwz r0, 0(r7) /* hdlr ... */
1720 add r0, r0, r3 /* ... += dest_addr */
1723 lwz r0, 4(r7) /* int_return ... */
1724 add r0, r0, r3 /* ... += dest_addr */
1729 #if defined(CONFIG_440)
1730 /*----------------------------------------------------------------------------+
1732 +----------------------------------------------------------------------------*/
1733 function_prolog(dcbz_area)
1734 rlwinm. r5,r4,0,27,31
1735 rlwinm r5,r4,27,5,31
1744 function_epilog(dcbz_area)
1745 #endif /* CONFIG_440 */
1746 #endif /* CONFIG_NAND_SPL */
1748 /*------------------------------------------------------------------------------- */
1750 /* Description: Input 8 bits */
1751 /*------------------------------------------------------------------------------- */
1757 /*------------------------------------------------------------------------------- */
1758 /* Function: out8 */
1759 /* Description: Output 8 bits */
1760 /*------------------------------------------------------------------------------- */
1766 /*------------------------------------------------------------------------------- */
1767 /* Function: out32 */
1768 /* Description: Output 32 bits */
1769 /*------------------------------------------------------------------------------- */
1775 /*------------------------------------------------------------------------------- */
1776 /* Function: in32 */
1777 /* Description: Input 32 bits */
1778 /*------------------------------------------------------------------------------- */
1784 /**************************************************************************/
1785 /* PPC405EP specific stuff */
1786 /**************************************************************************/
1790 #ifdef CONFIG_BUBINGA
1792 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1793 * function) to support FPGA and NVRAM accesses below.
1796 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1797 ori r3,r3,GPIO0_OSRH@l
1798 lis r4,CONFIG_SYS_GPIO0_OSRH@h
1799 ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l
1802 ori r3,r3,GPIO0_OSRL@l
1803 lis r4,CONFIG_SYS_GPIO0_OSRL@h
1804 ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l
1807 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1808 ori r3,r3,GPIO0_ISR1H@l
1809 lis r4,CONFIG_SYS_GPIO0_ISR1H@h
1810 ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
1812 lis r3,GPIO0_ISR1L@h
1813 ori r3,r3,GPIO0_ISR1L@l
1814 lis r4,CONFIG_SYS_GPIO0_ISR1L@h
1815 ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
1818 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1819 ori r3,r3,GPIO0_TSRH@l
1820 lis r4,CONFIG_SYS_GPIO0_TSRH@h
1821 ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l
1824 ori r3,r3,GPIO0_TSRL@l
1825 lis r4,CONFIG_SYS_GPIO0_TSRL@h
1826 ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l
1829 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1830 ori r3,r3,GPIO0_TCR@l
1831 lis r4,CONFIG_SYS_GPIO0_TCR@h
1832 ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
1835 li r3,pb1ap /* program EBC bank 1 for RTC access */
1837 lis r3,CONFIG_SYS_EBC_PB1AP@h
1838 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1842 lis r3,CONFIG_SYS_EBC_PB1CR@h
1843 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1846 li r3,pb1ap /* program EBC bank 1 for RTC access */
1848 lis r3,CONFIG_SYS_EBC_PB1AP@h
1849 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1853 lis r3,CONFIG_SYS_EBC_PB1CR@h
1854 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1857 li r3,pb4ap /* program EBC bank 4 for FPGA access */
1859 lis r3,CONFIG_SYS_EBC_PB4AP@h
1860 ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
1864 lis r3,CONFIG_SYS_EBC_PB4CR@h
1865 ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
1870 !-----------------------------------------------------------------------
1871 ! Check to see if chip is in bypass mode.
1872 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1873 ! CPU reset Otherwise, skip this step and keep going.
1874 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1875 ! will not be fast enough for the SDRAM (min 66MHz)
1876 !-----------------------------------------------------------------------
1878 mfdcr r5, CPC0_PLLMR1
1879 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1882 beq pll_done /* if SSCS =b'1' then PLL has */
1883 /* already been set */
1884 /* and CPU has been reset */
1885 /* so skip to next section */
1887 #ifdef CONFIG_BUBINGA
1889 !-----------------------------------------------------------------------
1890 ! Read NVRAM to get value to write in PLLMR.
1891 ! If value has not been correctly saved, write default value
1892 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1893 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1895 ! WARNING: This code assumes the first three words in the nvram_t
1896 ! structure in openbios.h. Changing the beginning of
1897 ! the structure will break this code.
1899 !-----------------------------------------------------------------------
1901 addis r3,0,NVRAM_BASE@h
1902 addi r3,r3,NVRAM_BASE@l
1905 addis r5,0,NVRVFY1@h
1906 addi r5,r5,NVRVFY1@l
1907 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1911 addis r5,0,NVRVFY2@h
1912 addi r5,r5,NVRVFY2@l
1913 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1915 addi r3,r3,8 /* Skip over conf_size */
1916 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1917 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1918 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1919 cmpi cr0,0,r5,1 /* See if PLL is locked */
1922 #endif /* CONFIG_BUBINGA */
1926 andi. r5, r4, CPC0_BOOT_SEP@l
1927 bne strap_1 /* serial eeprom present */
1928 addis r5,0,CPLD_REG0_ADDR@h
1929 ori r5,r5,CPLD_REG0_ADDR@l
1932 #endif /* CONFIG_TAIHU */
1934 #if defined(CONFIG_ZEUS)
1936 andi. r5, r4, CPC0_BOOT_SEP@l
1937 bne strap_1 /* serial eeprom present */
1944 mfdcr r3, CPC0_PLLMR0
1945 mfdcr r4, CPC0_PLLMR1
1949 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1950 ori r3,r3,PLLMR0_DEFAULT@l /* */
1951 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1952 ori r4,r4,PLLMR1_DEFAULT@l /* */
1957 addis r3,0,PLLMR0_DEFAULT_PCI66@h
1958 ori r3,r3,PLLMR0_DEFAULT_PCI66@l
1959 addis r4,0,PLLMR1_DEFAULT_PCI66@h
1960 ori r4,r4,PLLMR1_DEFAULT_PCI66@l
1963 mfdcr r3, CPC0_PLLMR0
1964 mfdcr r4, CPC0_PLLMR1
1965 #endif /* CONFIG_TAIHU */
1968 b pll_write /* Write the CPC0_PLLMR with new value */
1972 !-----------------------------------------------------------------------
1973 ! Clear Soft Reset Register
1974 ! This is needed to enable PCI if not booting from serial EPROM
1975 !-----------------------------------------------------------------------
1985 blr /* return to main code */
1988 !-----------------------------------------------------------------------------
1989 ! Function: pll_write
1990 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1992 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
1994 ! 3. Clock dividers are set while PLL is held in reset and bypassed
1995 ! 4. PLL Reset is cleared
1996 ! 5. Wait 100us for PLL to lock
1997 ! 6. A core reset is performed
1998 ! Input: r3 = Value to write to CPC0_PLLMR0
1999 ! Input: r4 = Value to write to CPC0_PLLMR1
2001 !-----------------------------------------------------------------------------
2006 ori r5,r5,0x0101 /* Stop the UART clocks */
2007 mtdcr CPC0_UCR,r5 /* Before changing PLL */
2009 mfdcr r5, CPC0_PLLMR1
2010 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
2011 mtdcr CPC0_PLLMR1,r5
2012 oris r5,r5,0x4000 /* Set PLL Reset */
2013 mtdcr CPC0_PLLMR1,r5
2015 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
2016 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
2017 oris r5,r5,0x4000 /* Set PLL Reset */
2018 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
2019 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
2020 mtdcr CPC0_PLLMR1,r5
2023 ! Wait min of 100us for PLL to lock.
2024 ! See CMOS 27E databook for more info.
2025 ! At 200MHz, that means waiting 20,000 instructions
2027 addi r3,0,20000 /* 2000 = 0x4e20 */
2032 oris r5,r5,0x8000 /* Enable PLL */
2033 mtdcr CPC0_PLLMR1,r5 /* Engage */
2036 * Reset CPU to guarantee timings are OK
2037 * Not sure if this is needed...
2040 mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
2041 /* execution will continue from the poweron */
2042 /* vector of 0xfffffffc */
2043 #endif /* CONFIG_405EP */
2045 #if defined(CONFIG_440)
2046 /*----------------------------------------------------------------------------+
2048 +----------------------------------------------------------------------------*/
2049 function_prolog(mttlb3)
2052 function_epilog(mttlb3)
2054 /*----------------------------------------------------------------------------+
2056 +----------------------------------------------------------------------------*/
2057 function_prolog(mftlb3)
2060 function_epilog(mftlb3)
2062 /*----------------------------------------------------------------------------+
2064 +----------------------------------------------------------------------------*/
2065 function_prolog(mttlb2)
2068 function_epilog(mttlb2)
2070 /*----------------------------------------------------------------------------+
2072 +----------------------------------------------------------------------------*/
2073 function_prolog(mftlb2)
2076 function_epilog(mftlb2)
2078 /*----------------------------------------------------------------------------+
2080 +----------------------------------------------------------------------------*/
2081 function_prolog(mttlb1)
2084 function_epilog(mttlb1)
2086 /*----------------------------------------------------------------------------+
2088 +----------------------------------------------------------------------------*/
2089 function_prolog(mftlb1)
2092 function_epilog(mftlb1)
2093 #endif /* CONFIG_440 */
2095 #if defined(CONFIG_NAND_SPL)
2097 * void nand_boot_relocate(dst, src, bytes)
2099 * r3 = Destination address to copy code to (in SDRAM)
2100 * r4 = Source address to copy code from
2101 * r5 = size to copy in bytes
2109 * Copy SPL from icache into SDRAM
2121 * Calculate "corrected" link register, so that we "continue"
2122 * in execution in destination range
2124 sub r3,r7,r6 /* r3 = src - dst */
2125 sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
2131 * First initialize SDRAM. It has to be available *before* calling
2134 lis r3,CONFIG_SYS_SDRAM_BASE@h
2135 ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
2139 * Now copy the 4k SPL code into SDRAM and continue execution
2142 lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
2143 ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
2144 lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
2145 ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
2146 lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
2147 ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
2148 bl nand_boot_relocate
2151 * We're running from SDRAM now!!!
2153 * It is necessary for 4xx systems to relocate from running at
2154 * the original location (0xfffffxxx) to somewhere else (SDRAM
2155 * preferably). This is because CS0 needs to be reconfigured for
2156 * NAND access. And we can't reconfigure this CS when currently
2157 * "running" from it.
2161 * Finally call nand_boot() to load main NAND U-Boot image from
2162 * NAND and jump to it.
2164 bl nand_boot /* will not return */
2165 #endif /* CONFIG_NAND_SPL */