2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /*------------------------------------------------------------------------------+ */
26 /* This source code has been made available to you by IBM on an AS-IS */
27 /* basis. Anyone receiving this source is licensed under IBM */
28 /* copyrights to use it in any way he or she deems fit, including */
29 /* copying it, modifying it, compiling it, and redistributing it either */
30 /* with or without modifications. No license under IBM patents or */
31 /* patent applications is to be implied by the copyright license. */
33 /* Any user of this software should understand that IBM cannot provide */
34 /* technical support for this software and will not be responsible for */
35 /* any consequences resulting from the use of this software. */
37 /* Any person who transfers this source code or any derivative work */
38 /* must include the IBM copyright notice, this paragraph, and the */
39 /* preceding two paragraphs in the transferred software. */
41 /* COPYRIGHT I B M CORPORATION 1995 */
42 /* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
43 /*------------------------------------------------------------------------------- */
45 /* U-Boot - Startup Code for IBM 4xx PowerPC based Embedded Boards
48 * The processor starts at 0xfffffffc and the code is executed
50 * in memory, but as long we don't jump around before relocating.
51 * board_init lies at a quite high address and when the cpu has
52 * jumped there, everything is ok.
53 * This works because the cpu gives the FLASH (CS0) the whole
54 * address space at startup, and board_init lies as a echo of
55 * the flash somewhere up there in the memorymap.
57 * board_init will change CS0 to be positioned at the correct
58 * address and (s)dram will be positioned at address 0
65 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
67 #include <ppc_asm.tmpl>
70 #include <asm/cache.h>
73 #ifndef CONFIG_IDENT_STRING
74 #define CONFIG_IDENT_STRING ""
77 #ifdef CFG_INIT_DCACHE_CS
78 # if (CFG_INIT_DCACHE_CS == 0)
82 # if (CFG_INIT_DCACHE_CS == 1)
86 # if (CFG_INIT_DCACHE_CS == 2)
90 # if (CFG_INIT_DCACHE_CS == 3)
94 # if (CFG_INIT_DCACHE_CS == 4)
98 # if (CFG_INIT_DCACHE_CS == 5)
102 # if (CFG_INIT_DCACHE_CS == 6)
106 # if (CFG_INIT_DCACHE_CS == 7)
110 #endif /* CFG_INIT_DCACHE_CS */
112 /* We don't want the MMU yet.
115 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
118 .extern ext_bus_cntlr_init
122 * Set up GOT: Global Offset Table
124 * Use r14 to access the GOT
127 GOT_ENTRY(_GOT2_TABLE_)
128 GOT_ENTRY(_FIXUP_TABLE_)
131 GOT_ENTRY(_start_of_vectors)
132 GOT_ENTRY(_end_of_vectors)
133 GOT_ENTRY(transfer_to_handler)
136 GOT_ENTRY(__bss_start)
140 * 440 Startup -- on reset only the top 4k of the effective
141 * address space is mapped in by an entry in the instruction
142 * and data shadow TLB. The .bootpg section is located in the
143 * top 4k & does only what's necessary to map in the the rest
144 * of the boot rom. Once the boot rom is mapped in we can
145 * proceed with normal startup.
147 * NOTE: CS0 only covers the top 2MB of the effective address
151 #if defined(CONFIG_440)
152 .section .bootpg,"ax"
155 /**************************************************************************/
157 /*----------------------------------------------------------------*/
158 /* Clear and set up some registers. */
159 /*----------------------------------------------------------------*/
160 iccci r0,r0 /* NOTE: operands not used for 440 */
161 dccci r0,r0 /* NOTE: operands not used for 440 */
169 /*----------------------------------------------------------------*/
170 /* Initialize debug */
171 /*----------------------------------------------------------------*/
184 mtspr dbsr,r1 /* Clear all valid bits */
186 /*----------------------------------------------------------------*/
188 /*----------------------------------------------------------------*/
189 /* Disable store gathering & broadcast, guarantee inst/data
190 * cache block touch, force load/store alignment
191 * (see errata 1.12: 440_33)
193 lis r1,0x0030 /* store gathering & broadcast disable */
194 ori r1,r1,0x6000 /* cache touch */
197 /*----------------------------------------------------------------*/
198 /* Setup interrupt vectors */
199 /*----------------------------------------------------------------*/
200 mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */
202 mtspr ivor0,r1 /* Critical input */
204 mtspr ivor1,r1 /* Machine check */
206 mtspr ivor2,r1 /* Data storage */
208 mtspr ivor3,r1 /* Instruction storage */
210 mtspr ivor4,r1 /* External interrupt */
212 mtspr ivor5,r1 /* Alignment */
214 mtspr ivor6,r1 /* Program check */
216 mtspr ivor7,r1 /* Floating point unavailable */
218 mtspr ivor8,r1 /* System call */
220 mtspr ivor10,r1 /* Decrementer (PIT for 440) */
222 mtspr ivor13,r1 /* Data TLB error */
224 mtspr ivor14,r1 /* Instr TLB error */
226 mtspr ivor15,r1 /* Debug */
228 /*----------------------------------------------------------------*/
229 /* Configure cache regions */
230 /*----------------------------------------------------------------*/
248 /*----------------------------------------------------------------*/
249 /* Cache victim limits */
250 /*----------------------------------------------------------------*/
251 /* floors 0, ceiling max to use the entire cache -- nothing locked
258 /*----------------------------------------------------------------*/
259 /* Clear all TLB entries -- TID = 0, TS = 0 */
260 /*----------------------------------------------------------------*/
262 li r1,0x003f /* 64 TLB entries */
264 0: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
268 /*----------------------------------------------------------------*/
269 /* TLB entry setup -- step thru tlbtab */
270 /*----------------------------------------------------------------*/
271 bl tlbtab /* Get tlbtab pointer */
273 li r1,0x003f /* 64 TLB entries max */
280 beq 2f /* 0 marks end */
283 tlbwe r0,r4,0 /* TLB Word 0 */
284 tlbwe r1,r4,1 /* TLB Word 1 */
285 tlbwe r2,r4,2 /* TLB Word 2 */
286 addi r4,r4,1 /* Next TLB */
289 /*----------------------------------------------------------------*/
290 /* Continue from 'normal' start */
291 /*----------------------------------------------------------------*/
296 mtspr srr1,r0 /* Keep things disabled for now */
300 #endif /* CONFIG_440 */
303 * r3 - 1st arg to board_init(): IMMP pointer
304 * r4 - 2nd arg to board_init(): boot flag
307 .long 0x27051956 /* U-Boot Magic Number */
308 .globl version_string
310 .ascii U_BOOT_VERSION
311 .ascii " (", __DATE__, " - ", __TIME__, ")"
312 .ascii CONFIG_IDENT_STRING, "\0"
315 * Maybe this should be moved somewhere else because the current
316 * location (0x100) is where the CriticalInput Execption should be.
318 . = EXC_OFF_SYS_RESET
322 /*****************************************************************************/
323 #if defined(CONFIG_440)
325 /*----------------------------------------------------------------*/
326 /* Clear and set up some registers. */
327 /*----------------------------------------------------------------*/
330 mtspr dec,r0 /* prevent dec exceptions */
331 mtspr tbl,r0 /* prevent fit & wdt exceptions */
333 mtspr tsr,r1 /* clear all timer exception status */
334 mtspr tcr,r0 /* disable all */
335 mtspr esr,r0 /* clear exception syndrome register */
336 mtxer r0 /* clear integer exception register */
337 lis r1,0x0002 /* set CE bit (Critical Exceptions) */
338 ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */
339 mtmsr r1 /* change MSR */
341 /*----------------------------------------------------------------*/
342 /* Debug setup -- some (not very good) ice's need an event*/
343 /* to establish control :-( Define CFG_INIT_DBCR to the dbsr */
344 /* value you need in this case 0x8cff 0000 should do the trick */
345 /*----------------------------------------------------------------*/
346 #if defined(CFG_INIT_DBCR)
349 mtspr dbsr,r1 /* Clear all status bits */
350 lis r0,CFG_INIT_DBCR@h
351 ori r0,r0,CFG_INIT_DBCR@l
356 /*----------------------------------------------------------------*/
357 /* Setup the internal SRAM */
358 /*----------------------------------------------------------------*/
360 mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
365 and r1,r1,r2 /* Disable parity check */
368 andis. r1,r1,r2 /* Disable pwr mgmt */
371 lis r1,0x8000 /* BAS = 8000_0000 */
372 ori r1,r1,0x0380 /* 8k rw */
373 mtdcr isram0_sb0cr,r1
375 /*----------------------------------------------------------------*/
376 /* Setup the stack in internal SRAM */
377 /*----------------------------------------------------------------*/
378 lis r1,CFG_INIT_RAM_ADDR@h
379 ori r1,r1,CFG_INIT_SP_OFFSET@l
383 stwu r0,-4(r1) /* Terminate call chain */
385 stwu r1,-8(r1) /* Save back chain and move SP */
386 lis r0,RESET_VECTOR@h /* Address of reset vector */
387 ori r0,r0, RESET_VECTOR@l
388 stwu r1,-8(r1) /* Save back chain and move SP */
389 stw r0,+12(r1) /* Save return addr (underflow vect) */
394 #endif /* CONFIG_440 */
396 /*****************************************************************************/
398 /*----------------------------------------------------------------------- */
399 /* Set up some machine state registers. */
400 /*----------------------------------------------------------------------- */
401 addi r0,r0,0x0000 /* initialize r0 to zero */
402 mtspr esr,r0 /* clear Exception Syndrome Reg */
403 mttcr r0 /* timer control register */
404 mtexier r0 /* disable all interrupts */
405 addi r4,r0,0x1000 /* set ME bit (Machine Exceptions) */
406 oris r4,r4,0x2 /* set CE bit (Critical Exceptions) */
407 mtmsr r4 /* change MSR */
408 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
409 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
410 mtdbsr r4 /* clear/reset the dbsr */
411 mtexisr r4 /* clear all pending interrupts */
413 mtexier r4 /* enable critical exceptions */
414 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
415 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
416 mtiocr r4 /* since bit not used) & DRC to latch */
417 /* data bus on rising edge of CAS */
418 /*----------------------------------------------------------------------- */
420 /*----------------------------------------------------------------------- */
422 /*----------------------------------------------------------------------- */
423 /* Invalidate i-cache and d-cache TAG arrays. */
424 /*----------------------------------------------------------------------- */
425 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
426 addi r4,0,1024 /* 1/4 of I-cache */
431 addic. r3,r3,-16 /* move back one cache line */
432 bne ..cloop /* loop back to do rest until r3 = 0 */
435 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
436 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
439 /* first copy IOP480 register base address into r3 */
440 addis r3,0,0x5000 /* IOP480 register base address hi */
441 /* ori r3,r3,0x0000 / IOP480 register base address lo */
444 /* use r4 as the working variable */
445 /* turn on CS3 (LOCCTL.7) */
446 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
447 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
448 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
451 #ifdef CONFIG_DASA_SIM
452 /* use r4 as the working variable */
453 /* turn on MA17 (LOCCTL.7) */
454 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
455 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
456 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
459 /* turn on MA16..13 (LCS0BRD.12 = 0) */
460 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
461 andi. r4,r4,0xefff /* make bit 12 = 0 */
462 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
464 /* make sure above stores all comlete before going on */
467 /* last thing, set local init status done bit (DEVINIT.31) */
468 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
469 oris r4,r4,0x8000 /* make bit 31 = 1 */
470 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
472 /* clear all pending interrupts and disable all interrupts */
473 li r4,-1 /* set p1 to 0xffffffff */
474 stw r4,0x1b0(r3) /* clear all pending interrupts */
475 stw r4,0x1b8(r3) /* clear all pending interrupts */
476 li r4,0 /* set r4 to 0 */
477 stw r4,0x1b4(r3) /* disable all interrupts */
478 stw r4,0x1bc(r3) /* disable all interrupts */
480 /* make sure above stores all comlete before going on */
483 /*----------------------------------------------------------------------- */
484 /* Enable two 128MB cachable regions. */
485 /*----------------------------------------------------------------------- */
488 mticcr r1 /* instruction cache */
492 mtdccr r1 /* data cache */
494 addis r1,r0,CFG_INIT_RAM_ADDR@h
495 ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */
496 li r0, 0 /* Make room for stack frame header and */
497 stwu r0, -4(r1) /* clear final stack frame so that */
498 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
500 GET_GOT /* initialize GOT access */
502 bl board_init_f /* run first part of init code (from Flash) */
504 #endif /* CONFIG_IOP480 */
506 /*****************************************************************************/
507 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_405EP)
508 /*----------------------------------------------------------------------- */
509 /* Clear and set up some registers. */
510 /*----------------------------------------------------------------------- */
514 mtesr r4 /* clear Exception Syndrome Reg */
515 mttcr r4 /* clear Timer Control Reg */
516 mtxer r4 /* clear Fixed-Point Exception Reg */
517 mtevpr r4 /* clear Exception Vector Prefix Reg */
518 addi r4,r0,0x1000 /* set ME bit (Machine Exceptions) */
519 oris r4,r4,0x0002 /* set CE bit (Critical Exceptions) */
520 mtmsr r4 /* change MSR */
521 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
522 /* dbsr is cleared by setting bits to 1) */
523 mtdbsr r4 /* clear/reset the dbsr */
525 /*----------------------------------------------------------------------- */
526 /* Invalidate I and D caches. Enable I cache for defined memory regions */
527 /* to speed things up. Leave the D cache disabled for now. It will be */
528 /* enabled/left disabled later based on user selected menu options. */
529 /* Be aware that the I cache may be disabled later based on the menu */
530 /* options as well. See miscLib/main.c. */
531 /*----------------------------------------------------------------------- */
535 /*----------------------------------------------------------------------- */
536 /* Enable two 128MB cachable regions. */
537 /*----------------------------------------------------------------------- */
540 mticcr r4 /* instruction cache */
545 mtdccr r4 /* data cache */
547 #if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
548 /*----------------------------------------------------------------------- */
549 /* Tune the speed and size for flash CS0 */
550 /*----------------------------------------------------------------------- */
551 bl ext_bus_cntlr_init
554 #if defined(CONFIG_405EP)
555 /*----------------------------------------------------------------------- */
556 /* DMA Status, clear to come up clean */
557 /*----------------------------------------------------------------------- */
558 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
562 bl ppc405ep_init /* do ppc405ep specific init */
563 #endif /* CONFIG_405EP */
565 #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
566 /********************************************************************
567 * Setup OCM - On Chip Memory
568 *******************************************************************/
572 mfdcr r3, ocmiscntl /* get instr-side IRAM config */
573 mfdcr r4, ocmdscntl /* get data-side IRAM config */
574 and r3, r3, r0 /* disable data-side IRAM */
575 and r4, r4, r0 /* disable data-side IRAM */
576 mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
577 mtdcr ocmdscntl, r4 /* set data-side IRAM config */
580 addis r3, 0, CFG_OCM_DATA_ADDR@h /* OCM location */
582 addis r4, 0, 0xC000 /* OCM data area enabled */
587 /*----------------------------------------------------------------------- */
588 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
589 /*----------------------------------------------------------------------- */
590 #ifdef CFG_INIT_DCACHE_CS
591 /*----------------------------------------------------------------------- */
592 /* Memory Bank x (nothingness) initialization 1GB+64MEG */
593 /* used as temporary stack pointer for stage0 */
594 /*----------------------------------------------------------------------- */
607 /* turn on data chache for this region */
611 /* set stack pointer and clear stack to known value */
613 lis r1,CFG_INIT_RAM_ADDR@h
614 ori r1,r1,CFG_INIT_SP_OFFSET@l
616 li r4,2048 /* we store 2048 words to stack */
619 lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */
620 ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */
622 lis r4,0xdead /* we store 0xdeaddead in the stack */
629 li r0, 0 /* Make room for stack frame header and */
630 stwu r0, -4(r1) /* clear final stack frame so that */
631 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
633 * Set up a dummy frame to store reset vector as return address.
634 * this causes stack underflow to reset board.
636 stwu r1, -8(r1) /* Save back chain and move SP */
637 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
638 ori r0, r0, RESET_VECTOR@l
639 stwu r1, -8(r1) /* Save back chain and move SP */
640 stw r0, +12(r1) /* Save return addr (underflow vect) */
642 #elif defined(CFG_TEMP_STACK_OCM) && \
643 (defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE))
648 /* Set up Stack at top of OCM */
649 lis r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h
650 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l
652 /* Set up a zeroized stack frame so that backtrace works right */
658 * Set up a dummy frame to store reset vector as return address.
659 * this causes stack underflow to reset board.
661 stwu r1, -8(r1) /* Save back chain and move SP */
662 lis r0, RESET_VECTOR@h /* Address of reset vector */
663 ori r0, r0, RESET_VECTOR@l
664 stwu r1, -8(r1) /* Save back chain and move SP */
665 stw r0, +12(r1) /* Save return addr (underflow vect) */
666 #endif /* CFG_INIT_DCACHE_CS */
668 /*----------------------------------------------------------------------- */
669 /* Initialize SDRAM Controller */
670 /*----------------------------------------------------------------------- */
674 * Setup temporary stack pointer only for boards
675 * that do not use SDRAM SPD I2C stuff since it
676 * is already initialized to use DCACHE or OCM
679 #if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
680 lis r1, CFG_INIT_RAM_ADDR@h
681 ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
683 li r0, 0 /* Make room for stack frame header and */
684 stwu r0, -4(r1) /* clear final stack frame so that */
685 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
687 * Set up a dummy frame to store reset vector as return address.
688 * this causes stack underflow to reset board.
690 stwu r1, -8(r1) /* Save back chain and move SP */
691 lis r0, RESET_VECTOR@h /* Address of reset vector */
692 ori r0, r0, RESET_VECTOR@l
693 stwu r1, -8(r1) /* Save back chain and move SP */
694 stw r0, +12(r1) /* Save return addr (underflow vect) */
695 #endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
697 GET_GOT /* initialize GOT access */
699 bl cpu_init_f /* run low-level CPU init code (from Flash) */
702 bl board_init_f /* run first part of init code (from Flash) */
704 #endif /* CONFIG_405GP || CONFIG_405CR */
707 /*****************************************************************************/
708 .globl _start_of_vectors
712 /*TODO Fixup _start above so we can do this*/
713 /* Critical input. */
714 CRIT_EXCEPTION(0x100, CritcalInput, CritcalInputException)
718 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
720 /* Data Storage exception. */
721 STD_EXCEPTION(0x300, DataStorage, UnknownException)
723 /* Instruction Storage exception. */
724 STD_EXCEPTION(0x400, InstStorage, UnknownException)
726 /* External Interrupt exception. */
727 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
729 /* Alignment exception. */
737 addi r3,r1,STACK_FRAME_OVERHEAD
739 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
740 lwz r6,GOT(transfer_to_handler)
744 .long AlignmentException - _start + EXC_OFF_SYS_RESET
745 .long int_return - _start + EXC_OFF_SYS_RESET
747 /* Program check exception */
751 addi r3,r1,STACK_FRAME_OVERHEAD
753 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
754 lwz r6,GOT(transfer_to_handler)
758 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
759 .long int_return - _start + EXC_OFF_SYS_RESET
761 /* No FPU on MPC8xx. This exception is not supposed to happen.
763 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
765 /* I guess we could implement decrementer, and may have
766 * to someday for timekeeping.
768 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
769 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
770 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
774 * r0 - SYSCALL number
778 addis r11,r0,0 /* get functions table addr */
779 ori r11,r11,0 /* Note: this code is patched in trap_init */
780 addis r12,r0,0 /* get number of functions */
786 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
790 li r20,0xd00-4 /* Get stack pointer */
792 subi r12,r12,12 /* Adjust stack pointer */
793 li r0,0xc00+_end_back-SystemCall
794 cmplw 0, r0, r12 /* Check stack overflow */
805 li r12,0xc00+_back-SystemCall
814 mfmsr r11 /* Disable interrupts */
818 SYNC /* Some chip revs need this... */
822 li r12,0xd00-4 /* restore regs */
832 addi r12,r12,12 /* Adjust stack pointer */
840 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
842 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
843 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
845 /* On the MPC8xx, this is a software emulation interrupt. It occurs
846 * for all unimplemented and illegal instructions.
848 STD_EXCEPTION(0x1000, PIT, PITException)
850 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
851 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
852 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
853 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
855 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
856 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
857 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
858 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
859 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
860 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
861 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
863 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
864 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
865 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
866 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
868 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
870 .globl _end_of_vectors
877 * This code finishes saving the registers to the exception frame
878 * and jumps to the appropriate handler for the exception.
879 * Register r21 is pointer into trap frame, r1 has new stack pointer.
881 .globl transfer_to_handler
893 mfspr r23,SPRG3 /* if from user, fix up tss.regs */
895 addi r24,r1,STACK_FRAME_OVERHEAD
897 2: addi r2,r23,-TSS /* set r2 to current */
901 andi. r24,r23,0x3f00 /* get vector offset */
905 mtspr SPRG2,r22 /* r1 is now kernel sp */
907 addi r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */
911 bgt stack_ovf /* if r2 < r1 < r2+TASK_STRUCT_SIZE */
913 lwz r24,0(r23) /* virtual address of handler */
914 lwz r23,4(r23) /* where to go when done */
919 rfi /* jump to handler, enable MMU */
922 mfmsr r28 /* Disable interrupts */
926 SYNC /* Some chip revs need this... */
941 lwz r2,_NIP(r1) /* Restore environment */
952 mfmsr r28 /* Disable interrupts */
956 SYNC /* Some chip revs need this... */
971 lwz r2,_NIP(r1) /* Restore environment */
973 mtspr 990,r2 /* SRR2 */
974 mtspr 991,r0 /* SRR3 */
984 iccci r0,r0 /* for 405, iccci invalidates the */
985 blr /* entire I cache */
988 addi r6,0,0x0000 /* clear GPR 6 */
989 /* Do loop for # of dcache congruence classes. */
990 addi r7,r0, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
991 /* NOTE: dccci invalidates both */
992 mtctr r7 /* ways in the D cache */
994 dccci 0,r6 /* invalidate line */
995 addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */
1000 addis r9,r0,0x0002 /* set mask for EE and CE msr bits */
1002 mfmsr r12 /* save msr */
1004 mtmsr r9 /* disable EE and CE */
1005 addi r10,r0,0x0001 /* enable data cache for unused memory */
1006 mfdccr r9 /* region 0xF8000000-0xFFFFFFFF via */
1007 or r10,r10,r9 /* bit 31 in dccr */
1010 /* do loop for # of congruence classes. */
1011 addi r10,r0,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
1012 addi r11,r0,(CFG_DCACHE_SIZE / 2) /* D cache set size - 2 way sets */
1014 addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
1015 add r11,r10,r11 /* add to get to other side of cache line */
1016 ..flush_dcache_loop:
1017 lwz r3,0(r10) /* least recently used side */
1018 lwz r3,0(r11) /* the other side */
1019 dccci r0,r11 /* invalidate both sides */
1020 addi r10,r10,CFG_CACHELINE_SIZE /* bump to next line */
1021 addi r11,r11,CFG_CACHELINE_SIZE /* bump to next line */
1022 bdnz ..flush_dcache_loop
1023 sync /* allow memory access to complete */
1024 mtdccr r9 /* restore dccr */
1025 mtmsr r12 /* restore msr */
1028 .globl icache_enable
1031 bl invalidate_icache
1034 addis r3,r0, 0x8000 /* set bit 0 */
1038 .globl icache_disable
1040 addis r3,r0, 0x0000 /* clear bit 0 */
1045 .globl icache_status
1048 srwi r3, r3, 31 /* >>31 => select bit 0 */
1051 .globl dcache_enable
1054 bl invalidate_dcache
1057 addis r3,r0, 0x8000 /* set bit 0 */
1061 .globl dcache_disable
1066 addis r3,r0, 0x0000 /* clear bit 0 */
1070 .globl dcache_status
1073 srwi r3, r3, 31 /* >>31 => select bit 0 */
1081 #if !defined(CONFIG_440)
1093 /*------------------------------------------------------------------------------- */
1095 /* Description: Input 8 bits */
1096 /*------------------------------------------------------------------------------- */
1102 /*------------------------------------------------------------------------------- */
1103 /* Function: out8 */
1104 /* Description: Output 8 bits */
1105 /*------------------------------------------------------------------------------- */
1111 /*------------------------------------------------------------------------------- */
1112 /* Function: out16 */
1113 /* Description: Output 16 bits */
1114 /*------------------------------------------------------------------------------- */
1120 /*------------------------------------------------------------------------------- */
1121 /* Function: out16r */
1122 /* Description: Byte reverse and output 16 bits */
1123 /*------------------------------------------------------------------------------- */
1129 /*------------------------------------------------------------------------------- */
1130 /* Function: out32 */
1131 /* Description: Output 32 bits */
1132 /*------------------------------------------------------------------------------- */
1138 /*------------------------------------------------------------------------------- */
1139 /* Function: out32r */
1140 /* Description: Byte reverse and output 32 bits */
1141 /*------------------------------------------------------------------------------- */
1147 /*------------------------------------------------------------------------------- */
1148 /* Function: in16 */
1149 /* Description: Input 16 bits */
1150 /*------------------------------------------------------------------------------- */
1156 /*------------------------------------------------------------------------------- */
1157 /* Function: in16r */
1158 /* Description: Input 16 bits and byte reverse */
1159 /*------------------------------------------------------------------------------- */
1165 /*------------------------------------------------------------------------------- */
1166 /* Function: in32 */
1167 /* Description: Input 32 bits */
1168 /*------------------------------------------------------------------------------- */
1174 /*------------------------------------------------------------------------------- */
1175 /* Function: in32r */
1176 /* Description: Input 32 bits and byte reverse */
1177 /*------------------------------------------------------------------------------- */
1183 /*------------------------------------------------------------------------------- */
1184 /* Function: ppcDcbf */
1185 /* Description: Data Cache block flush */
1186 /* Input: r3 = effective address */
1188 /*------------------------------------------------------------------------------- */
1194 /*------------------------------------------------------------------------------- */
1195 /* Function: ppcDcbi */
1196 /* Description: Data Cache block Invalidate */
1197 /* Input: r3 = effective address */
1199 /*------------------------------------------------------------------------------- */
1205 /*------------------------------------------------------------------------------- */
1206 /* Function: ppcSync */
1207 /* Description: Processor Synchronize */
1210 /*------------------------------------------------------------------------------- */
1216 /*------------------------------------------------------------------------------*/
1219 * void relocate_code (addr_sp, gd, addr_moni)
1221 * This "function" does not return, instead it continues in RAM
1222 * after relocating the monitor code.
1226 * r5 = length in bytes
1227 * r6 = cachelinesize
1229 .globl relocate_code
1231 mr r1, r3 /* Set new stack pointer */
1232 mr r9, r4 /* Save copy of Init Data pointer */
1233 mr r10, r5 /* Save copy of Destination Address */
1235 mr r3, r5 /* Destination Address */
1236 lis r4, CFG_MONITOR_BASE@h /* Source Address */
1237 ori r4, r4, CFG_MONITOR_BASE@l
1238 lis r5, CFG_MONITOR_LEN@h /* Length in Bytes */
1239 ori r5, r5, CFG_MONITOR_LEN@l
1240 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
1245 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
1251 /* First our own GOT */
1253 /* the the one used by the C code */
1263 beq cr1,4f /* In place copy is not necessary */
1264 beq 7f /* Protect against 0 count */
1283 * Now flush the cache: note that we must start from a cache aligned
1284 * address. Otherwise we might miss one cache line.
1288 beq 7f /* Always flush prefetch queue in any case */
1296 sync /* Wait for all dcbst to complete on bus */
1302 7: sync /* Wait for all icbi to complete on bus */
1306 * We are done. Do not return, instead branch to second part of board
1307 * initialization, now running from RAM.
1310 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
1312 blr /* NEVER RETURNS! */
1317 * Relocation Function, r14 point to got2+0x8000
1319 * Adjust got2 pointers, no need to check for 0, this code
1320 * already puts a few entries in the table.
1322 li r0,__got2_entries@sectoff@l
1323 la r3,GOT(_GOT2_TABLE_)
1324 lwz r11,GOT(_GOT2_TABLE_)
1334 * Now adjust the fixups and the pointers to the fixups
1335 * in case we need to move ourselves again.
1337 2: li r0,__fixup_entries@sectoff@l
1338 lwz r3,GOT(_FIXUP_TABLE_)
1352 * Now clear BSS segment
1354 lwz r3,GOT(__bss_start)
1368 mr r3, r9 /* Init Data pointer */
1369 mr r4, r10 /* Destination Address */
1372 /* Problems accessing "end" in C, so do it here */
1379 * Copy exception vector code to low memory
1382 * r7: source address, r8: end address, r9: target address
1387 lwz r8, GOT(_end_of_vectors)
1389 rlwinm r9, r7, 0, 18, 31 /* _start & 0x3FFF */
1392 bgelr /* return if r7>=r8 - just in case */
1394 mflr r4 /* save link register */
1404 * relocate `hdlr' and `int_return' entries
1406 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1407 li r8, Alignment - _start + EXC_OFF_SYS_RESET
1410 addi r7, r7, 0x100 /* next exception vector */
1414 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1417 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1420 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1421 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
1424 addi r7, r7, 0x100 /* next exception vector */
1428 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1429 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1432 addi r7, r7, 0x100 /* next exception vector */
1436 mtlr r4 /* restore link register */
1440 * Function: relocate entries for one exception vector
1443 lwz r0, 0(r7) /* hdlr ... */
1444 add r0, r0, r3 /* ... += dest_addr */
1447 lwz r0, 4(r7) /* int_return ... */
1448 add r0, r0, r3 /* ... += dest_addr */
1454 /**************************************************************************/
1455 /* PPC405EP specific stuff */
1456 /**************************************************************************/
1460 !-----------------------------------------------------------------------
1461 ! Check FPGA for PCI internal/external arbitration
1462 ! If board is set to internal arbitration, update cpc0_pci
1463 !-----------------------------------------------------------------------
1465 addi r3,0,CPC0_PCI_HOST_CFG_EN
1466 #ifdef CONFIG_BUBINGA405EP
1467 addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */
1468 ori r5,r5,FPGA_REG1@l
1469 lbz r5,0x0(r5) /* read to get PCI arb selection */
1470 andi. r6,r5,FPGA_REG1_PCI_INT_ARB /* using internal arbiter ?*/
1471 beq ..pci_cfg_set /* if not set, then bypass reg write*/
1473 ori r3,r3,CPC0_PCI_ARBIT_EN
1475 mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/
1478 !-----------------------------------------------------------------------
1479 ! Check to see if chip is in bypass mode.
1480 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1481 ! CPU reset Otherwise, skip this step and keep going.
1482 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1483 ! will not be fast enough for the SDRAM (min 66MHz)
1484 !-----------------------------------------------------------------------
1486 mfdcr r5, CPC0_PLLMR1
1487 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1490 beq pll_done /* if SSCS =b'1' then PLL has */
1491 /* already been set */
1492 /* and CPU has been reset */
1493 /* so skip to next section */
1495 #ifdef CONFIG_BUBINGA405EP
1497 !-----------------------------------------------------------------------
1498 ! Read NVRAM to get value to write in PLLMR.
1499 ! If value has not been correctly saved, write default value
1500 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1501 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1503 ! WARNING: This code assumes the first three words in the nvram_t
1504 ! structure in openbios.h. Changing the beginning of
1505 ! the structure will break this code.
1507 !-----------------------------------------------------------------------
1509 addis r3,0,NVRAM_BASE@h
1510 addi r3,r3,NVRAM_BASE@l
1513 addis r5,0,NVRVFY1@h
1514 addi r5,r5,NVRVFY1@l
1515 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1519 addis r5,0,NVRVFY2@h
1520 addi r5,r5,NVRVFY2@l
1521 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1523 addi r3,r3,8 /* Skip over conf_size */
1524 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1525 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1526 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1527 cmpi cr0,0,r5,1 /* See if PLL is locked */
1530 #endif /* CONFIG_BUBINGA405EP */
1532 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1533 ori r3,r3,PLLMR0_DEFAULT@l /* */
1534 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1535 ori r4,r4,PLLMR1_DEFAULT@l /* */
1537 b pll_write /* Write the CPC0_PLLMR with new value */
1541 !-----------------------------------------------------------------------
1542 ! Clear Soft Reset Register
1543 ! This is needed to enable PCI if not booting from serial EPROM
1544 !-----------------------------------------------------------------------
1554 blr /* return to main code */
1557 !-----------------------------------------------------------------------------
1558 ! Function: pll_write
1559 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1561 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
1563 ! 3. Clock dividers are set while PLL is held in reset and bypassed
1564 ! 4. PLL Reset is cleared
1565 ! 5. Wait 100us for PLL to lock
1566 ! 6. A core reset is performed
1567 ! Input: r3 = Value to write to CPC0_PLLMR0
1568 ! Input: r4 = Value to write to CPC0_PLLMR1
1570 !-----------------------------------------------------------------------------
1575 ori r5,r5,0x0101 /* Stop the UART clocks */
1576 mtdcr CPC0_UCR,r5 /* Before changing PLL */
1578 mfdcr r5, CPC0_PLLMR1
1579 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
1580 mtdcr CPC0_PLLMR1,r5
1581 oris r5,r5,0x4000 /* Set PLL Reset */
1582 mtdcr CPC0_PLLMR1,r5
1584 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
1585 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
1586 oris r5,r5,0x4000 /* Set PLL Reset */
1587 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
1588 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
1589 mtdcr CPC0_PLLMR1,r5
1592 ! Wait min of 100us for PLL to lock.
1593 ! See CMOS 27E databook for more info.
1594 ! At 200MHz, that means waiting 20,000 instructions
1596 addi r3,0,20000 /* 2000 = 0x4e20 */
1601 oris r5,r5,0x8000 /* Enable PLL */
1602 mtdcr CPC0_PLLMR1,r5 /* Engage */
1605 * Reset CPU to guarantee timings are OK
1606 * Not sure if this is needed...
1609 mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
1610 /* execution will continue from the poweron */
1611 /* vector of 0xfffffffc */
1612 #endif /* CONFIG_405EP */