2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright (c) 2008 Nuovation System Designs, LLC
7 * Grant Erickson <gerickson@nuovations.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 /*------------------------------------------------------------------------------+
29 * This source code has been made available to you by IBM on an AS-IS
30 * basis. Anyone receiving this source is licensed under IBM
31 * copyrights to use it in any way he or she deems fit, including
32 * copying it, modifying it, compiling it, and redistributing it either
33 * with or without modifications. No license under IBM patents or
34 * patent applications is to be implied by the copyright license.
36 * Any user of this software should understand that IBM cannot provide
37 * technical support for this software and will not be responsible for
38 * any consequences resulting from the use of this software.
40 * Any person who transfers this source code or any derivative work
41 * must include the IBM copyright notice, this paragraph, and the
42 * preceding two paragraphs in the transferred software.
44 * COPYRIGHT I B M CORPORATION 1995
45 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
46 *-------------------------------------------------------------------------------
49 /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
52 * The processor starts at 0xfffffffc and the code is executed
54 * in memory, but as long we don't jump around before relocating.
55 * board_init lies at a quite high address and when the cpu has
56 * jumped there, everything is ok.
57 * This works because the cpu gives the FLASH (CS0) the whole
58 * address space at startup, and board_init lies as a echo of
59 * the flash somewhere up there in the memorymap.
61 * board_init will change CS0 to be positioned at the correct
62 * address and (s)dram will be positioned at address 0
66 #include <timestamp.h>
69 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
71 #include <ppc_asm.tmpl>
74 #include <asm/cache.h>
76 #include <asm/ppc4xx-isram.h>
78 #ifndef CONFIG_IDENT_STRING
79 #define CONFIG_IDENT_STRING ""
82 #ifdef CONFIG_SYS_INIT_DCACHE_CS
83 # if (CONFIG_SYS_INIT_DCACHE_CS == 0)
86 # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
87 # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
88 # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
91 # if (CONFIG_SYS_INIT_DCACHE_CS == 1)
94 # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
95 # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
96 # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
99 # if (CONFIG_SYS_INIT_DCACHE_CS == 2)
102 # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
103 # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
104 # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
107 # if (CONFIG_SYS_INIT_DCACHE_CS == 3)
110 # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
111 # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
112 # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
115 # if (CONFIG_SYS_INIT_DCACHE_CS == 4)
118 # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
119 # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
120 # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
123 # if (CONFIG_SYS_INIT_DCACHE_CS == 5)
126 # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
127 # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
128 # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
131 # if (CONFIG_SYS_INIT_DCACHE_CS == 6)
134 # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
135 # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
136 # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
139 # if (CONFIG_SYS_INIT_DCACHE_CS == 7)
142 # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
143 # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
144 # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
154 * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
155 * used as temporary stack pointer for the primordial stack
157 # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
158 # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
159 EBC_BXAP_TWT_ENCODE(7) | \
160 EBC_BXAP_BCE_DISABLE | \
161 EBC_BXAP_BCT_2TRANS | \
162 EBC_BXAP_CSN_ENCODE(0) | \
163 EBC_BXAP_OEN_ENCODE(0) | \
164 EBC_BXAP_WBN_ENCODE(0) | \
165 EBC_BXAP_WBF_ENCODE(0) | \
166 EBC_BXAP_TH_ENCODE(2) | \
167 EBC_BXAP_RE_DISABLED | \
168 EBC_BXAP_SOR_NONDELAYED | \
169 EBC_BXAP_BEM_WRITEONLY | \
170 EBC_BXAP_PEN_DISABLED)
171 # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
172 # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
173 # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \
177 # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
178 # ifndef CONFIG_SYS_INIT_RAM_PATTERN
179 # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD
181 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
183 #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10)))
184 #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END!
188 * Unless otherwise overriden, enable two 128MB cachable instruction regions
189 * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
190 * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
192 #if !defined(CONFIG_SYS_FLASH_BASE)
193 /* If not already defined, set it to the "last" 128MByte region */
194 # define CONFIG_SYS_FLASH_BASE 0xf8000000
196 #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
197 # define CONFIG_SYS_ICACHE_SACR_VALUE \
198 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
199 PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
200 PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
201 #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
203 #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
204 # define CONFIG_SYS_DCACHE_SACR_VALUE \
206 #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
208 #define function_prolog(func_name) .text; \
212 #define function_epilog(func_name) .type func_name,@function; \
213 .size func_name,.-func_name
215 /* We don't want the MMU yet.
218 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
221 .extern ext_bus_cntlr_init
222 #ifdef CONFIG_NAND_U_BOOT
223 .extern reconfig_tlb0
227 * Set up GOT: Global Offset Table
229 * Use r14 to access the GOT
231 #if !defined(CONFIG_NAND_SPL)
233 GOT_ENTRY(_GOT2_TABLE_)
234 GOT_ENTRY(_FIXUP_TABLE_)
237 GOT_ENTRY(_start_of_vectors)
238 GOT_ENTRY(_end_of_vectors)
239 GOT_ENTRY(transfer_to_handler)
241 GOT_ENTRY(__init_end)
243 GOT_ENTRY(__bss_start)
245 #endif /* CONFIG_NAND_SPL */
247 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
249 * NAND U-Boot image is started from offset 0
252 #if defined(CONFIG_440)
256 bl cpu_init_f /* run low-level CPU init code (from Flash) */
260 #if defined(CONFIG_SYS_RAMBOOT)
262 * 4xx RAM-booting U-Boot image is started from offset 0
269 * 440 Startup -- on reset only the top 4k of the effective
270 * address space is mapped in by an entry in the instruction
271 * and data shadow TLB. The .bootpg section is located in the
272 * top 4k & does only what's necessary to map in the the rest
273 * of the boot rom. Once the boot rom is mapped in we can
274 * proceed with normal startup.
276 * NOTE: CS0 only covers the top 2MB of the effective address
280 #if defined(CONFIG_440)
281 #if !defined(CONFIG_NAND_SPL)
282 .section .bootpg,"ax"
286 /**************************************************************************/
288 /*--------------------------------------------------------------------+
289 | 440EPX BUP Change - Hardware team request
290 +--------------------------------------------------------------------*/
291 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
296 /*----------------------------------------------------------------+
297 | Core bug fix. Clear the esr
298 +-----------------------------------------------------------------*/
301 /*----------------------------------------------------------------*/
302 /* Clear and set up some registers. */
303 /*----------------------------------------------------------------*/
304 iccci r0,r0 /* NOTE: operands not used for 440 */
305 dccci r0,r0 /* NOTE: operands not used for 440 */
312 /* NOTE: 440GX adds machine check status regs */
313 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
320 /*----------------------------------------------------------------*/
322 /*----------------------------------------------------------------*/
323 /* Disable store gathering & broadcast, guarantee inst/data
324 * cache block touch, force load/store alignment
325 * (see errata 1.12: 440_33)
327 lis r1,0x0030 /* store gathering & broadcast disable */
328 ori r1,r1,0x6000 /* cache touch */
331 /*----------------------------------------------------------------*/
332 /* Initialize debug */
333 /*----------------------------------------------------------------*/
335 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
336 bne skip_debug_init /* if set, don't clear debug register */
349 mtspr dbsr,r1 /* Clear all valid bits */
352 #if defined (CONFIG_440SPE)
353 /*----------------------------------------------------------------+
354 | Initialize Core Configuration Reg1.
355 | a. ICDPEI: Record even parity. Normal operation.
356 | b. ICTPEI: Record even parity. Normal operation.
357 | c. DCTPEI: Record even parity. Normal operation.
358 | d. DCDPEI: Record even parity. Normal operation.
359 | e. DCUPEI: Record even parity. Normal operation.
360 | f. DCMPEI: Record even parity. Normal operation.
361 | g. FCOM: Normal operation
362 | h. MMUPEI: Record even parity. Normal operation.
363 | i. FFF: Flush only as much data as necessary.
364 | j. TCS: Timebase increments from CPU clock.
365 +-----------------------------------------------------------------*/
369 /*----------------------------------------------------------------+
370 | Reset the timebase.
371 | The previous write to CCR1 sets the timebase source.
372 +-----------------------------------------------------------------*/
377 /*----------------------------------------------------------------*/
378 /* Setup interrupt vectors */
379 /*----------------------------------------------------------------*/
380 mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */
382 mtspr ivor0,r1 /* Critical input */
384 mtspr ivor1,r1 /* Machine check */
386 mtspr ivor2,r1 /* Data storage */
388 mtspr ivor3,r1 /* Instruction storage */
390 mtspr ivor4,r1 /* External interrupt */
392 mtspr ivor5,r1 /* Alignment */
394 mtspr ivor6,r1 /* Program check */
396 mtspr ivor7,r1 /* Floating point unavailable */
398 mtspr ivor8,r1 /* System call */
400 mtspr ivor9,r1 /* Auxiliary Processor unavailable */
402 mtspr ivor10,r1 /* Decrementer */
404 mtspr ivor13,r1 /* Data TLB error */
406 mtspr ivor14,r1 /* Instr TLB error */
408 mtspr ivor15,r1 /* Debug */
410 /*----------------------------------------------------------------*/
411 /* Configure cache regions */
412 /*----------------------------------------------------------------*/
430 /*----------------------------------------------------------------*/
431 /* Cache victim limits */
432 /*----------------------------------------------------------------*/
433 /* floors 0, ceiling max to use the entire cache -- nothing locked
440 /*----------------------------------------------------------------+
441 |Initialize MMUCR[STID] = 0.
442 +-----------------------------------------------------------------*/
449 /*----------------------------------------------------------------*/
450 /* Clear all TLB entries -- TID = 0, TS = 0 */
451 /*----------------------------------------------------------------*/
453 li r1,0x003f /* 64 TLB entries */
455 li r4,0 /* Start with TLB #0 */
457 #ifdef CONFIG_SYS_RAMBOOT
458 tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */
459 rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */
460 beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */
462 tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/
465 tlbnxt: addi r4,r4,1 /* Next TLB */
468 /*----------------------------------------------------------------*/
469 /* TLB entry setup -- step thru tlbtab */
470 /*----------------------------------------------------------------*/
471 #if defined(CONFIG_440SPE)
472 /*----------------------------------------------------------------*/
473 /* We have different TLB tables for revA and rev B of 440SPe */
474 /*----------------------------------------------------------------*/
486 bl tlbtab /* Get tlbtab pointer */
489 li r1,0x003f /* 64 TLB entries max */
495 #ifdef CONFIG_SYS_RAMBOOT
496 tlbre r3,r4,0 /* Read contents from TLB word #0 */
497 rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */
498 bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */
502 beq 2f /* 0 marks end */
505 tlbwe r0,r4,0 /* TLB Word 0 */
506 tlbwe r1,r4,1 /* TLB Word 1 */
507 tlbwe r2,r4,2 /* TLB Word 2 */
508 tlbnx2: addi r4,r4,1 /* Next TLB */
511 /*----------------------------------------------------------------*/
512 /* Continue from 'normal' start */
513 /*----------------------------------------------------------------*/
519 mtspr srr1,r0 /* Keep things disabled for now */
523 #endif /* CONFIG_440 */
526 * r3 - 1st arg to board_init(): IMMP pointer
527 * r4 - 2nd arg to board_init(): boot flag
529 #ifndef CONFIG_NAND_SPL
531 .long 0x27051956 /* U-Boot Magic Number */
532 .globl version_string
534 .ascii U_BOOT_VERSION
535 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
536 .ascii CONFIG_IDENT_STRING, "\0"
538 . = EXC_OFF_SYS_RESET
539 .globl _start_of_vectors
542 /* Critical input. */
543 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
547 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
549 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
550 #endif /* CONFIG_440 */
552 /* Data Storage exception. */
553 STD_EXCEPTION(0x300, DataStorage, UnknownException)
555 /* Instruction Storage exception. */
556 STD_EXCEPTION(0x400, InstStorage, UnknownException)
558 /* External Interrupt exception. */
559 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
561 /* Alignment exception. */
564 EXCEPTION_PROLOG(SRR0, SRR1)
569 addi r3,r1,STACK_FRAME_OVERHEAD
571 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
572 lwz r6,GOT(transfer_to_handler)
576 .long AlignmentException - _start + _START_OFFSET
577 .long int_return - _start + _START_OFFSET
579 /* Program check exception */
582 EXCEPTION_PROLOG(SRR0, SRR1)
583 addi r3,r1,STACK_FRAME_OVERHEAD
585 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
586 lwz r6,GOT(transfer_to_handler)
590 .long ProgramCheckException - _start + _START_OFFSET
591 .long int_return - _start + _START_OFFSET
594 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
595 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
596 STD_EXCEPTION(0xa00, APU, UnknownException)
598 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
601 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
602 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
604 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
605 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
606 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
608 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
610 .globl _end_of_vectors
617 /*****************************************************************************/
618 #if defined(CONFIG_440)
620 /*----------------------------------------------------------------*/
621 /* Clear and set up some registers. */
622 /*----------------------------------------------------------------*/
625 mtspr dec,r0 /* prevent dec exceptions */
626 mtspr tbl,r0 /* prevent fit & wdt exceptions */
628 mtspr tsr,r1 /* clear all timer exception status */
629 mtspr tcr,r0 /* disable all */
630 mtspr esr,r0 /* clear exception syndrome register */
631 mtxer r0 /* clear integer exception register */
633 /*----------------------------------------------------------------*/
634 /* Debug setup -- some (not very good) ice's need an event*/
635 /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
636 /* value you need in this case 0x8cff 0000 should do the trick */
637 /*----------------------------------------------------------------*/
638 #if defined(CONFIG_SYS_INIT_DBCR)
641 mtspr dbsr,r1 /* Clear all status bits */
642 lis r0,CONFIG_SYS_INIT_DBCR@h
643 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
648 /*----------------------------------------------------------------*/
649 /* Setup the internal SRAM */
650 /*----------------------------------------------------------------*/
653 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
654 /* Clear Dcache to use as RAM */
655 addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
656 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
657 addis r4,r0,CONFIG_SYS_INIT_RAM_END@h
658 ori r4,r4,CONFIG_SYS_INIT_RAM_END@l
659 rlwinm. r5,r4,0,27,31
671 * Lock the init-ram/stack in d-cache, so that other regions
672 * may use d-cache as well
673 * Note, that this current implementation locks exactly 4k
674 * of d-cache, so please make sure that you don't define a
675 * bigger init-ram area. Take a look at the lwmon5 440EPx
676 * implementation as a reference.
680 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
696 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
698 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
699 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
700 /* not all PPC's have internal SRAM usable as L2-cache */
701 #if defined(CONFIG_440GX) || \
702 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
703 defined(CONFIG_460SX)
704 mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
705 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
707 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
708 mtdcr L2_CACHE_CFG,r1
714 and r1,r1,r2 /* Disable parity check */
717 and r1,r1,r2 /* Disable pwr mgmt */
720 lis r1,0x8000 /* BAS = 8000_0000 */
721 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
722 ori r1,r1,0x0980 /* first 64k */
723 mtdcr ISRAM0_SB0CR,r1
725 ori r1,r1,0x0980 /* second 64k */
726 mtdcr ISRAM0_SB1CR,r1
728 ori r1,r1, 0x0980 /* third 64k */
729 mtdcr ISRAM0_SB2CR,r1
731 ori r1,r1, 0x0980 /* fourth 64k */
732 mtdcr ISRAM0_SB3CR,r1
733 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
734 lis r1,0x0000 /* BAS = X_0000_0000 */
735 ori r1,r1,0x0984 /* first 64k */
736 mtdcr ISRAM0_SB0CR,r1
738 ori r1,r1,0x0984 /* second 64k */
739 mtdcr ISRAM0_SB1CR,r1
741 ori r1,r1, 0x0984 /* third 64k */
742 mtdcr ISRAM0_SB2CR,r1
744 ori r1,r1, 0x0984 /* fourth 64k */
745 mtdcr ISRAM0_SB3CR,r1
746 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
750 and r1,r1,r2 /* Disable parity check */
753 and r1,r1,r2 /* Disable pwr mgmt */
756 lis r1,0x0004 /* BAS = 4_0004_0000 */
757 ori r1,r1,0x0984 /* 64k */
758 mtdcr ISRAM1_SB0CR,r1
760 #elif defined(CONFIG_460SX)
761 lis r1,0x0000 /* BAS = 0000_0000 */
762 ori r1,r1,0x0B84 /* first 128k */
763 mtdcr ISRAM0_SB0CR,r1
765 ori r1,r1,0x0B84 /* second 128k */
766 mtdcr ISRAM0_SB1CR,r1
768 ori r1,r1, 0x0B84 /* third 128k */
769 mtdcr ISRAM0_SB2CR,r1
771 ori r1,r1, 0x0B84 /* fourth 128k */
772 mtdcr ISRAM0_SB3CR,r1
773 #elif defined(CONFIG_440GP)
774 ori r1,r1,0x0380 /* 8k rw */
775 mtdcr ISRAM0_SB0CR,r1
776 mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
778 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
780 /*----------------------------------------------------------------*/
781 /* Setup the stack in internal SRAM */
782 /*----------------------------------------------------------------*/
783 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
784 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
787 stwu r0,-4(r1) /* Terminate call chain */
789 stwu r1,-8(r1) /* Save back chain and move SP */
790 lis r0,RESET_VECTOR@h /* Address of reset vector */
791 ori r0,r0, RESET_VECTOR@l
792 stwu r1,-8(r1) /* Save back chain and move SP */
793 stw r0,+12(r1) /* Save return addr (underflow vect) */
795 #ifdef CONFIG_NAND_SPL
796 bl nand_boot_common /* will not return */
800 bl cpu_init_f /* run low-level CPU init code (from Flash) */
804 #endif /* CONFIG_440 */
806 /*****************************************************************************/
808 /*----------------------------------------------------------------------- */
809 /* Set up some machine state registers. */
810 /*----------------------------------------------------------------------- */
811 addi r0,r0,0x0000 /* initialize r0 to zero */
812 mtspr esr,r0 /* clear Exception Syndrome Reg */
813 mttcr r0 /* timer control register */
814 mtexier r0 /* disable all interrupts */
815 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
816 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
817 mtdbsr r4 /* clear/reset the dbsr */
818 mtexisr r4 /* clear all pending interrupts */
820 mtexier r4 /* enable critical exceptions */
821 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
822 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
823 mtiocr r4 /* since bit not used) & DRC to latch */
824 /* data bus on rising edge of CAS */
825 /*----------------------------------------------------------------------- */
827 /*----------------------------------------------------------------------- */
829 /*----------------------------------------------------------------------- */
830 /* Invalidate i-cache and d-cache TAG arrays. */
831 /*----------------------------------------------------------------------- */
832 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
833 addi r4,0,1024 /* 1/4 of I-cache */
838 addic. r3,r3,-16 /* move back one cache line */
839 bne ..cloop /* loop back to do rest until r3 = 0 */
842 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
843 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
846 /* first copy IOP480 register base address into r3 */
847 addis r3,0,0x5000 /* IOP480 register base address hi */
848 /* ori r3,r3,0x0000 / IOP480 register base address lo */
851 /* use r4 as the working variable */
852 /* turn on CS3 (LOCCTL.7) */
853 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
854 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
855 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
858 #ifdef CONFIG_DASA_SIM
859 /* use r4 as the working variable */
860 /* turn on MA17 (LOCCTL.7) */
861 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
862 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
863 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
866 /* turn on MA16..13 (LCS0BRD.12 = 0) */
867 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
868 andi. r4,r4,0xefff /* make bit 12 = 0 */
869 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
871 /* make sure above stores all comlete before going on */
874 /* last thing, set local init status done bit (DEVINIT.31) */
875 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
876 oris r4,r4,0x8000 /* make bit 31 = 1 */
877 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
879 /* clear all pending interrupts and disable all interrupts */
880 li r4,-1 /* set p1 to 0xffffffff */
881 stw r4,0x1b0(r3) /* clear all pending interrupts */
882 stw r4,0x1b8(r3) /* clear all pending interrupts */
883 li r4,0 /* set r4 to 0 */
884 stw r4,0x1b4(r3) /* disable all interrupts */
885 stw r4,0x1bc(r3) /* disable all interrupts */
887 /* make sure above stores all comlete before going on */
890 /* Set-up icache cacheability. */
891 lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h
892 ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l
896 /* Set-up dcache cacheability. */
897 lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h
898 ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l
901 addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h
902 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */
903 li r0, 0 /* Make room for stack frame header and */
904 stwu r0, -4(r1) /* clear final stack frame so that */
905 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
907 GET_GOT /* initialize GOT access */
909 bl board_init_f /* run first part of init code (from Flash) */
911 #endif /* CONFIG_IOP480 */
913 /*****************************************************************************/
914 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
915 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
916 defined(CONFIG_405EX) || defined(CONFIG_405)
917 /*----------------------------------------------------------------------- */
918 /* Clear and set up some registers. */
919 /*----------------------------------------------------------------------- */
921 #if !defined(CONFIG_405EX)
925 * On 405EX, completely clearing the SGR leads to PPC hangup
926 * upon PCIe configuration access. The PCIe memory regions
927 * need to be guarded!
934 mtesr r4 /* clear Exception Syndrome Reg */
935 mttcr r4 /* clear Timer Control Reg */
936 mtxer r4 /* clear Fixed-Point Exception Reg */
937 mtevpr r4 /* clear Exception Vector Prefix Reg */
938 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
939 /* dbsr is cleared by setting bits to 1) */
940 mtdbsr r4 /* clear/reset the dbsr */
942 /* Invalidate the i- and d-caches. */
946 /* Set-up icache cacheability. */
947 lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
948 ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
952 /* Set-up dcache cacheability. */
953 lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
954 ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
957 #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
958 && !defined (CONFIG_XILINX_405)
959 /*----------------------------------------------------------------------- */
960 /* Tune the speed and size for flash CS0 */
961 /*----------------------------------------------------------------------- */
962 bl ext_bus_cntlr_init
965 #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
967 * For boards that don't have OCM and can't use the data cache
968 * for their primordial stack, setup stack here directly after the
969 * SDRAM is initialized in ext_bus_cntlr_init.
971 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
972 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
974 li r0, 0 /* Make room for stack frame header and */
975 stwu r0, -4(r1) /* clear final stack frame so that */
976 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
978 * Set up a dummy frame to store reset vector as return address.
979 * this causes stack underflow to reset board.
981 stwu r1, -8(r1) /* Save back chain and move SP */
982 lis r0, RESET_VECTOR@h /* Address of reset vector */
983 ori r0, r0, RESET_VECTOR@l
984 stwu r1, -8(r1) /* Save back chain and move SP */
985 stw r0, +12(r1) /* Save return addr (underflow vect) */
986 #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
988 #if defined(CONFIG_405EP)
989 /*----------------------------------------------------------------------- */
990 /* DMA Status, clear to come up clean */
991 /*----------------------------------------------------------------------- */
992 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
996 bl ppc405ep_init /* do ppc405ep specific init */
997 #endif /* CONFIG_405EP */
999 #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
1000 #if defined(CONFIG_405EZ)
1001 /********************************************************************
1002 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
1003 *******************************************************************/
1005 * We can map the OCM on the PLB3, so map it at
1006 * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
1008 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1009 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1010 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
1011 mtdcr ocmplb3cr1,r3 /* Set PLB Access */
1012 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
1013 mtdcr ocmplb3cr2,r3 /* Set PLB Access */
1016 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1017 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1018 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
1019 mtdcr ocmdscr1, r3 /* Set Data Side */
1020 mtdcr ocmiscr1, r3 /* Set Instruction Side */
1021 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
1022 mtdcr ocmdscr2, r3 /* Set Data Side */
1023 mtdcr ocmiscr2, r3 /* Set Instruction Side */
1024 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
1028 #else /* CONFIG_405EZ */
1029 /********************************************************************
1030 * Setup OCM - On Chip Memory
1031 *******************************************************************/
1035 mfdcr r3, ocmiscntl /* get instr-side IRAM config */
1036 mfdcr r4, ocmdscntl /* get data-side IRAM config */
1037 and r3, r3, r0 /* disable data-side IRAM */
1038 and r4, r4, r0 /* disable data-side IRAM */
1039 mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
1040 mtdcr ocmdscntl, r4 /* set data-side IRAM config */
1043 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
1044 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
1046 addis r4, 0, 0xC000 /* OCM data area enabled */
1049 #endif /* CONFIG_405EZ */
1052 /*----------------------------------------------------------------------- */
1053 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
1054 /*----------------------------------------------------------------------- */
1055 #ifdef CONFIG_SYS_INIT_DCACHE_CS
1058 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
1059 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
1064 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
1065 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
1069 * Enable the data cache for the 128MB storage access control region
1070 * at CONFIG_SYS_INIT_RAM_ADDR.
1073 oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1074 ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1078 * Preallocate data cache lines to be used to avoid a subsequent
1079 * cache miss and an ensuing machine check exception when exceptions
1084 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1085 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1087 lis r4, CONFIG_SYS_INIT_RAM_END@h
1088 ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
1091 * Convert the size, in bytes, to the number of cache lines/blocks
1094 clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
1095 srwi r5, r4, L1_CACHE_SHIFT
1101 /* Preallocate the computed number of cache blocks. */
1102 ..alloc_dcache_block:
1104 addi r3, r3, L1_CACHE_BYTES
1105 bdnz ..alloc_dcache_block
1109 * Load the initial stack pointer and data area and convert the size,
1110 * in bytes, to the number of words to initialize to a known value.
1112 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
1113 ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
1115 lis r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h
1116 ori r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l
1119 lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
1120 ori r2, r2, CONFIG_SYS_INIT_RAM_END@l
1122 lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
1123 ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
1130 * Make room for stack frame header and clear final stack frame so
1131 * that stack backtraces terminate cleanly.
1137 * Set up a dummy frame to store reset vector as return address.
1138 * this causes stack underflow to reset board.
1140 stwu r1, -8(r1) /* Save back chain and move SP */
1141 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1142 ori r0, r0, RESET_VECTOR@l
1143 stwu r1, -8(r1) /* Save back chain and move SP */
1144 stw r0, +12(r1) /* Save return addr (underflow vect) */
1146 #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
1147 (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
1152 /* Set up Stack at top of OCM */
1153 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
1154 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
1156 /* Set up a zeroized stack frame so that backtrace works right */
1162 * Set up a dummy frame to store reset vector as return address.
1163 * this causes stack underflow to reset board.
1165 stwu r1, -8(r1) /* Save back chain and move SP */
1166 lis r0, RESET_VECTOR@h /* Address of reset vector */
1167 ori r0, r0, RESET_VECTOR@l
1168 stwu r1, -8(r1) /* Save back chain and move SP */
1169 stw r0, +12(r1) /* Save return addr (underflow vect) */
1170 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
1172 #ifdef CONFIG_NAND_SPL
1173 bl nand_boot_common /* will not return */
1175 GET_GOT /* initialize GOT access */
1177 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1179 /* NEVER RETURNS! */
1180 bl board_init_f /* run first part of init code (from Flash) */
1181 #endif /* CONFIG_NAND_SPL */
1183 #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1184 /*----------------------------------------------------------------------- */
1187 #ifndef CONFIG_NAND_SPL
1189 * This code finishes saving the registers to the exception frame
1190 * and jumps to the appropriate handler for the exception.
1191 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1193 .globl transfer_to_handler
1194 transfer_to_handler:
1204 andi. r24,r23,0x3f00 /* get vector offset */
1208 mtspr SPRG2,r22 /* r1 is now kernel sp */
1209 lwz r24,0(r23) /* virtual address of handler */
1210 lwz r23,4(r23) /* where to go when done */
1215 rfi /* jump to handler, enable MMU */
1218 mfmsr r28 /* Disable interrupts */
1222 SYNC /* Some chip revs need this... */
1237 lwz r2,_NIP(r1) /* Restore environment */
1248 mfmsr r28 /* Disable interrupts */
1252 SYNC /* Some chip revs need this... */
1267 lwz r2,_NIP(r1) /* Restore environment */
1279 mfmsr r28 /* Disable interrupts */
1283 SYNC /* Some chip revs need this... */
1298 lwz r2,_NIP(r1) /* Restore environment */
1307 #endif /* CONFIG_440 */
1315 /*------------------------------------------------------------------------------- */
1316 /* Function: out16 */
1317 /* Description: Output 16 bits */
1318 /*------------------------------------------------------------------------------- */
1324 /*------------------------------------------------------------------------------- */
1325 /* Function: out16r */
1326 /* Description: Byte reverse and output 16 bits */
1327 /*------------------------------------------------------------------------------- */
1333 /*------------------------------------------------------------------------------- */
1334 /* Function: out32r */
1335 /* Description: Byte reverse and output 32 bits */
1336 /*------------------------------------------------------------------------------- */
1342 /*------------------------------------------------------------------------------- */
1343 /* Function: in16 */
1344 /* Description: Input 16 bits */
1345 /*------------------------------------------------------------------------------- */
1351 /*------------------------------------------------------------------------------- */
1352 /* Function: in16r */
1353 /* Description: Input 16 bits and byte reverse */
1354 /*------------------------------------------------------------------------------- */
1360 /*------------------------------------------------------------------------------- */
1361 /* Function: in32r */
1362 /* Description: Input 32 bits and byte reverse */
1363 /*------------------------------------------------------------------------------- */
1370 * void relocate_code (addr_sp, gd, addr_moni)
1372 * This "function" does not return, instead it continues in RAM
1373 * after relocating the monitor code.
1375 * r3 = Relocated stack pointer
1376 * r4 = Relocated global data pointer
1377 * r5 = Relocated text pointer
1379 .globl relocate_code
1381 #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
1383 * We need to flush the initial global data (gd_t) before the dcache
1384 * will be invalidated.
1387 /* Save registers */
1392 /* Flush initial global data range */
1394 addi r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l
1395 bl flush_dcache_range
1397 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
1399 * Undo the earlier data cache set-up for the primordial stack and
1400 * data area. First, invalidate the data cache and then disable data
1401 * cacheability for that area. Finally, restore the EBC values, if
1405 /* Invalidate the primordial stack and data area in cache */
1406 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1407 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1409 lis r4, CONFIG_SYS_INIT_RAM_END@h
1410 ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
1413 bl invalidate_dcache_range
1415 /* Disable cacheability for the region */
1417 lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1418 ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1422 /* Restore the EBC parameters */
1426 ori r3, r3, PBxAP_VAL@l
1432 ori r3, r3, PBxCR_VAL@l
1434 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
1436 /* Restore registers */
1440 #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
1442 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
1444 * Unlock the previously locked d-cache
1448 /* set TFLOOR/NFLOOR to 0 again */
1464 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
1466 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1467 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1468 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
1469 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1470 defined(CONFIG_460SX)
1472 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1473 * to speed up the boot process. Now this cache needs to be disabled.
1475 iccci 0,0 /* Invalidate inst cache */
1476 dccci 0,0 /* Invalidate data cache, now no longer our stack */
1480 /* Clear all potential pending exceptions */
1483 #ifdef CONFIG_SYS_TLB_FOR_BOOT_FLASH
1484 addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1486 addi r1,r0,0x0000 /* Default TLB entry is #0 */
1487 #endif /* CONFIG_SYS_TLB_FOR_BOOT_FLASH */
1488 tlbre r0,r1,0x0002 /* Read contents */
1489 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1490 tlbwe r0,r1,0x0002 /* Save it out */
1493 #endif /* defined(CONFIG_440EP) || ... || defined(CONFIG_460GT) */
1494 mr r1, r3 /* Set new stack pointer */
1495 mr r9, r4 /* Save copy of Init Data pointer */
1496 mr r10, r5 /* Save copy of Destination Address */
1498 mr r3, r5 /* Destination Address */
1499 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1500 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
1501 lwz r5, GOT(__init_end)
1503 li r6, L1_CACHE_BYTES /* Cache Line Size */
1508 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1514 /* First our own GOT */
1516 /* then the one used by the C code */
1526 beq cr1,4f /* In place copy is not necessary */
1527 beq 7f /* Protect against 0 count */
1546 * Now flush the cache: note that we must start from a cache aligned
1547 * address. Otherwise we might miss one cache line.
1551 beq 7f /* Always flush prefetch queue in any case */
1559 sync /* Wait for all dcbst to complete on bus */
1565 7: sync /* Wait for all icbi to complete on bus */
1569 * We are done. Do not return, instead branch to second part of board
1570 * initialization, now running from RAM.
1573 addi r0, r10, in_ram - _start + _START_OFFSET
1575 blr /* NEVER RETURNS! */
1580 * Relocation Function, r14 point to got2+0x8000
1582 * Adjust got2 pointers, no need to check for 0, this code
1583 * already puts a few entries in the table.
1585 li r0,__got2_entries@sectoff@l
1586 la r3,GOT(_GOT2_TABLE_)
1587 lwz r11,GOT(_GOT2_TABLE_)
1597 * Now adjust the fixups and the pointers to the fixups
1598 * in case we need to move ourselves again.
1600 2: li r0,__fixup_entries@sectoff@l
1601 lwz r3,GOT(_FIXUP_TABLE_)
1615 * Now clear BSS segment
1617 lwz r3,GOT(__bss_start)
1640 mr r3, r9 /* Init Data pointer */
1641 mr r4, r10 /* Destination Address */
1645 * Copy exception vector code to low memory
1648 * r7: source address, r8: end address, r9: target address
1652 lwz r7, GOT(_start_of_vectors)
1653 lwz r8, GOT(_end_of_vectors)
1655 li r9, 0x100 /* reset vector always at 0x100 */
1658 bgelr /* return if r7>=r8 - just in case */
1660 mflr r4 /* save link register */
1670 * relocate `hdlr' and `int_return' entries
1672 li r7, .L_MachineCheck - _start + _START_OFFSET
1673 li r8, Alignment - _start + _START_OFFSET
1676 addi r7, r7, 0x100 /* next exception vector */
1680 li r7, .L_Alignment - _start + _START_OFFSET
1683 li r7, .L_ProgramCheck - _start + _START_OFFSET
1687 li r7, .L_FPUnavailable - _start + _START_OFFSET
1690 li r7, .L_Decrementer - _start + _START_OFFSET
1693 li r7, .L_APU - _start + _START_OFFSET
1696 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1699 li r7, .L_DataTLBError - _start + _START_OFFSET
1701 #else /* CONFIG_440 */
1702 li r7, .L_PIT - _start + _START_OFFSET
1705 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1708 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1710 #endif /* CONFIG_440 */
1712 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1715 #if !defined(CONFIG_440)
1716 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1717 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1718 mtmsr r7 /* change MSR */
1721 b __440_msr_continue
1724 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1725 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1733 mtlr r4 /* restore link register */
1737 * Function: relocate entries for one exception vector
1740 lwz r0, 0(r7) /* hdlr ... */
1741 add r0, r0, r3 /* ... += dest_addr */
1744 lwz r0, 4(r7) /* int_return ... */
1745 add r0, r0, r3 /* ... += dest_addr */
1750 #if defined(CONFIG_440)
1751 /*----------------------------------------------------------------------------+
1753 +----------------------------------------------------------------------------*/
1754 function_prolog(dcbz_area)
1755 rlwinm. r5,r4,0,27,31
1756 rlwinm r5,r4,27,5,31
1765 function_epilog(dcbz_area)
1766 #endif /* CONFIG_440 */
1767 #endif /* CONFIG_NAND_SPL */
1769 /*------------------------------------------------------------------------------- */
1771 /* Description: Input 8 bits */
1772 /*------------------------------------------------------------------------------- */
1778 /*------------------------------------------------------------------------------- */
1779 /* Function: out8 */
1780 /* Description: Output 8 bits */
1781 /*------------------------------------------------------------------------------- */
1787 /*------------------------------------------------------------------------------- */
1788 /* Function: out32 */
1789 /* Description: Output 32 bits */
1790 /*------------------------------------------------------------------------------- */
1796 /*------------------------------------------------------------------------------- */
1797 /* Function: in32 */
1798 /* Description: Input 32 bits */
1799 /*------------------------------------------------------------------------------- */
1805 /**************************************************************************/
1806 /* PPC405EP specific stuff */
1807 /**************************************************************************/
1811 #ifdef CONFIG_BUBINGA
1813 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1814 * function) to support FPGA and NVRAM accesses below.
1817 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1818 ori r3,r3,GPIO0_OSRH@l
1819 lis r4,CONFIG_SYS_GPIO0_OSRH@h
1820 ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l
1823 ori r3,r3,GPIO0_OSRL@l
1824 lis r4,CONFIG_SYS_GPIO0_OSRL@h
1825 ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l
1828 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1829 ori r3,r3,GPIO0_ISR1H@l
1830 lis r4,CONFIG_SYS_GPIO0_ISR1H@h
1831 ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
1833 lis r3,GPIO0_ISR1L@h
1834 ori r3,r3,GPIO0_ISR1L@l
1835 lis r4,CONFIG_SYS_GPIO0_ISR1L@h
1836 ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
1839 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1840 ori r3,r3,GPIO0_TSRH@l
1841 lis r4,CONFIG_SYS_GPIO0_TSRH@h
1842 ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l
1845 ori r3,r3,GPIO0_TSRL@l
1846 lis r4,CONFIG_SYS_GPIO0_TSRL@h
1847 ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l
1850 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1851 ori r3,r3,GPIO0_TCR@l
1852 lis r4,CONFIG_SYS_GPIO0_TCR@h
1853 ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
1856 li r3,pb1ap /* program EBC bank 1 for RTC access */
1858 lis r3,CONFIG_SYS_EBC_PB1AP@h
1859 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1863 lis r3,CONFIG_SYS_EBC_PB1CR@h
1864 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1867 li r3,pb1ap /* program EBC bank 1 for RTC access */
1869 lis r3,CONFIG_SYS_EBC_PB1AP@h
1870 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1874 lis r3,CONFIG_SYS_EBC_PB1CR@h
1875 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1878 li r3,pb4ap /* program EBC bank 4 for FPGA access */
1880 lis r3,CONFIG_SYS_EBC_PB4AP@h
1881 ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
1885 lis r3,CONFIG_SYS_EBC_PB4CR@h
1886 ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
1891 !-----------------------------------------------------------------------
1892 ! Check to see if chip is in bypass mode.
1893 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1894 ! CPU reset Otherwise, skip this step and keep going.
1895 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1896 ! will not be fast enough for the SDRAM (min 66MHz)
1897 !-----------------------------------------------------------------------
1899 mfdcr r5, CPC0_PLLMR1
1900 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1903 beq pll_done /* if SSCS =b'1' then PLL has */
1904 /* already been set */
1905 /* and CPU has been reset */
1906 /* so skip to next section */
1908 #ifdef CONFIG_BUBINGA
1910 !-----------------------------------------------------------------------
1911 ! Read NVRAM to get value to write in PLLMR.
1912 ! If value has not been correctly saved, write default value
1913 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1914 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1916 ! WARNING: This code assumes the first three words in the nvram_t
1917 ! structure in openbios.h. Changing the beginning of
1918 ! the structure will break this code.
1920 !-----------------------------------------------------------------------
1922 addis r3,0,NVRAM_BASE@h
1923 addi r3,r3,NVRAM_BASE@l
1926 addis r5,0,NVRVFY1@h
1927 addi r5,r5,NVRVFY1@l
1928 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1932 addis r5,0,NVRVFY2@h
1933 addi r5,r5,NVRVFY2@l
1934 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1936 addi r3,r3,8 /* Skip over conf_size */
1937 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1938 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1939 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1940 cmpi cr0,0,r5,1 /* See if PLL is locked */
1943 #endif /* CONFIG_BUBINGA */
1947 andi. r5, r4, CPC0_BOOT_SEP@l
1948 bne strap_1 /* serial eeprom present */
1949 addis r5,0,CPLD_REG0_ADDR@h
1950 ori r5,r5,CPLD_REG0_ADDR@l
1953 #endif /* CONFIG_TAIHU */
1955 #if defined(CONFIG_ZEUS)
1957 andi. r5, r4, CPC0_BOOT_SEP@l
1958 bne strap_1 /* serial eeprom present */
1965 mfdcr r3, CPC0_PLLMR0
1966 mfdcr r4, CPC0_PLLMR1
1970 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1971 ori r3,r3,PLLMR0_DEFAULT@l /* */
1972 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1973 ori r4,r4,PLLMR1_DEFAULT@l /* */
1978 addis r3,0,PLLMR0_DEFAULT_PCI66@h
1979 ori r3,r3,PLLMR0_DEFAULT_PCI66@l
1980 addis r4,0,PLLMR1_DEFAULT_PCI66@h
1981 ori r4,r4,PLLMR1_DEFAULT_PCI66@l
1984 mfdcr r3, CPC0_PLLMR0
1985 mfdcr r4, CPC0_PLLMR1
1986 #endif /* CONFIG_TAIHU */
1989 b pll_write /* Write the CPC0_PLLMR with new value */
1993 !-----------------------------------------------------------------------
1994 ! Clear Soft Reset Register
1995 ! This is needed to enable PCI if not booting from serial EPROM
1996 !-----------------------------------------------------------------------
2006 blr /* return to main code */
2009 !-----------------------------------------------------------------------------
2010 ! Function: pll_write
2011 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
2013 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
2015 ! 3. Clock dividers are set while PLL is held in reset and bypassed
2016 ! 4. PLL Reset is cleared
2017 ! 5. Wait 100us for PLL to lock
2018 ! 6. A core reset is performed
2019 ! Input: r3 = Value to write to CPC0_PLLMR0
2020 ! Input: r4 = Value to write to CPC0_PLLMR1
2022 !-----------------------------------------------------------------------------
2028 ori r5,r5,0x0101 /* Stop the UART clocks */
2029 mtdcr CPC0_UCR,r5 /* Before changing PLL */
2031 mfdcr r5, CPC0_PLLMR1
2032 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
2033 mtdcr CPC0_PLLMR1,r5
2034 oris r5,r5,0x4000 /* Set PLL Reset */
2035 mtdcr CPC0_PLLMR1,r5
2037 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
2038 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
2039 oris r5,r5,0x4000 /* Set PLL Reset */
2040 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
2041 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
2042 mtdcr CPC0_PLLMR1,r5
2045 ! Wait min of 100us for PLL to lock.
2046 ! See CMOS 27E databook for more info.
2047 ! At 200MHz, that means waiting 20,000 instructions
2049 addi r3,0,20000 /* 2000 = 0x4e20 */
2054 oris r5,r5,0x8000 /* Enable PLL */
2055 mtdcr CPC0_PLLMR1,r5 /* Engage */
2058 * Reset CPU to guarantee timings are OK
2059 * Not sure if this is needed...
2062 mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
2063 /* execution will continue from the poweron */
2064 /* vector of 0xfffffffc */
2065 #endif /* CONFIG_405EP */
2067 #if defined(CONFIG_440)
2068 /*----------------------------------------------------------------------------+
2070 +----------------------------------------------------------------------------*/
2071 function_prolog(mttlb3)
2074 function_epilog(mttlb3)
2076 /*----------------------------------------------------------------------------+
2078 +----------------------------------------------------------------------------*/
2079 function_prolog(mftlb3)
2082 function_epilog(mftlb3)
2084 /*----------------------------------------------------------------------------+
2086 +----------------------------------------------------------------------------*/
2087 function_prolog(mttlb2)
2090 function_epilog(mttlb2)
2092 /*----------------------------------------------------------------------------+
2094 +----------------------------------------------------------------------------*/
2095 function_prolog(mftlb2)
2098 function_epilog(mftlb2)
2100 /*----------------------------------------------------------------------------+
2102 +----------------------------------------------------------------------------*/
2103 function_prolog(mttlb1)
2106 function_epilog(mttlb1)
2108 /*----------------------------------------------------------------------------+
2110 +----------------------------------------------------------------------------*/
2111 function_prolog(mftlb1)
2114 function_epilog(mftlb1)
2115 #endif /* CONFIG_440 */
2117 #if defined(CONFIG_NAND_SPL)
2119 * void nand_boot_relocate(dst, src, bytes)
2121 * r3 = Destination address to copy code to (in SDRAM)
2122 * r4 = Source address to copy code from
2123 * r5 = size to copy in bytes
2131 * Copy SPL from icache into SDRAM
2143 * Calculate "corrected" link register, so that we "continue"
2144 * in execution in destination range
2146 sub r3,r7,r6 /* r3 = src - dst */
2147 sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
2153 * First initialize SDRAM. It has to be available *before* calling
2156 lis r3,CONFIG_SYS_SDRAM_BASE@h
2157 ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
2161 * Now copy the 4k SPL code into SDRAM and continue execution
2164 lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
2165 ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
2166 lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
2167 ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
2168 lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
2169 ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
2170 bl nand_boot_relocate
2173 * We're running from SDRAM now!!!
2175 * It is necessary for 4xx systems to relocate from running at
2176 * the original location (0xfffffxxx) to somewhere else (SDRAM
2177 * preferably). This is because CS0 needs to be reconfigured for
2178 * NAND access. And we can't reconfigure this CS when currently
2179 * "running" from it.
2183 * Finally call nand_boot() to load main NAND U-Boot image from
2184 * NAND and jump to it.
2186 bl nand_boot /* will not return */
2187 #endif /* CONFIG_NAND_SPL */