3 * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
7 * Kenneth Johansson ,Ericsson AB.
8 * kenneth.johansson@etx.ericsson.se
10 * hacked up by bill hunter. fixed so we could run before
11 * serial_init and console_init. previous version avoided this by
12 * running out of cache memory during serial/console init, then running
16 * Jun Gu, Artesyn Technology, jung@artesyncp.com
17 * Support for IBM 440 based on OpenBIOS draminit.c from IBM.
19 * See file CREDITS for list of people who contributed to this
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License as
24 * published by the Free Software Foundation; either version 2 of
25 * the License, or (at your option) any later version.
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
32 * You should have received a copy of the GNU General Public License
33 * along with this program; if not, write to the Free Software
34 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
39 #include <asm/processor.h>
43 #ifdef CONFIG_SPD_EEPROM
49 #define CFG_I2C_SPEED 50000
53 #define CFG_I2C_SLAVE 0xFE
56 #ifndef CONFIG_440 /* for 405 WALNUT board */
58 #define SDRAM0_CFG_DCE 0x80000000
59 #define SDRAM0_CFG_SRE 0x40000000
60 #define SDRAM0_CFG_PME 0x20000000
61 #define SDRAM0_CFG_MEMCHK 0x10000000
62 #define SDRAM0_CFG_REGEN 0x08000000
63 #define SDRAM0_CFG_ECCDD 0x00400000
64 #define SDRAM0_CFG_EMDULR 0x00200000
65 #define SDRAM0_CFG_DRW_SHIFT (31-6)
66 #define SDRAM0_CFG_BRPF_SHIFT (31-8)
68 #define SDRAM0_TR_CASL_SHIFT (31-8)
69 #define SDRAM0_TR_PTA_SHIFT (31-13)
70 #define SDRAM0_TR_CTP_SHIFT (31-15)
71 #define SDRAM0_TR_LDF_SHIFT (31-17)
72 #define SDRAM0_TR_RFTA_SHIFT (31-29)
73 #define SDRAM0_TR_RCD_SHIFT (31-31)
75 #define SDRAM0_RTR_SHIFT (31-15)
76 #define SDRAM0_ECCCFG_SHIFT (31-11)
78 /* SDRAM0_CFG enable macro */
79 #define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )
81 #define SDRAM0_BXCR_SZ_MASK 0x000e0000
82 #define SDRAM0_BXCR_AM_MASK 0x0000e000
84 #define SDRAM0_BXCR_SZ_SHIFT (31-14)
85 #define SDRAM0_BXCR_AM_SHIFT (31-18)
87 #define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
88 #define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
90 #ifdef CONFIG_SPDDRAM_SILENT
91 # define SPD_ERR(x) do { return 0; } while (0)
93 # define SPD_ERR(x) do { printf(x); return(0); } while (0)
96 #define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
98 /* function prototypes */
99 int spd_read(uint addr);
103 * This function is reading data from the DIMM module EEPROM over the SPD bus
104 * and uses that to program the sdram controller.
106 * This works on boards that has the same schematics that the IBM walnut has.
108 * Input: null for default I2C spd functions or a pointer to a custom function
109 * returning spd_data.
112 long int spd_sdram(int(read_spd)(uint addr))
114 int bus_period,tmp,row,col;
115 int total_size,bank_size,bank_code;
120 int sdram0_pmit=0x07c00000;
121 #ifndef CONFIG_405EP /* not on PPC405EP */
124 int sdram0_eccesr=-1;
147 * Make sure I2C controller is initialized
150 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
155 * Calculate the bus period, we do it this
156 * way to minimize stack utilization.
159 tmp = (mfdcr(pllmd) >> (31-6)) & 0xf; /* get FBDV bits */
160 tmp = CONFIG_SYS_CLK_FREQ * tmp; /* get plb freq */
163 unsigned long freqCPU;
164 unsigned long pllmr0;
165 unsigned long pllmr1;
166 unsigned long pllFbkDiv;
167 unsigned long pllPlbDiv;
168 unsigned long pllmr0_ccdv;
171 * Read PLL Mode registers
173 pllmr0 = mfdcr (cpc0_pllmr0);
174 pllmr1 = mfdcr (cpc0_pllmr1);
176 pllFbkDiv = ((pllmr1 & PLLMR1_FBMUL_MASK) >> 20);
177 if (pllFbkDiv == 0) {
180 pllPlbDiv = ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) >> 16) + 1;
183 * Determine CPU clock frequency
185 pllmr0_ccdv = ((pllmr0 & PLLMR0_CPU_DIV_MASK) >> 20) + 1;
186 if (pllmr1 & PLLMR1_SSCS_MASK) {
187 freqCPU = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / pllmr0_ccdv;
189 freqCPU = CONFIG_SYS_CLK_FREQ / pllmr0_ccdv;
193 * Determine PLB clock frequency
195 tmp = freqCPU / pllPlbDiv;
198 bus_period = sdram_HZ_to_ns(tmp); /* get sdram speed */
200 /* Make shure we are using SDRAM */
201 if (read_spd(2) != 0x04){
202 SPD_ERR("SDRAM - non SDRAM memory module found\n");
205 /*------------------------------------------------------------------
206 configure memory timing register
209 27 IN Row Precharge Time ( t RP)
210 29 MIN RAS to CAS Delay ( t RCD)
211 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS
212 -------------------------------------------------------------------*/
215 * first figure out which cas latency mode to use
216 * use the min supported mode
219 tmp = read_spd(127) & 0x6;
220 if(tmp == 0x02){ /* only cas = 2 supported */
222 /* t_ck = read_spd(9); */
223 /* t_ac = read_spd(10); */
225 else if (tmp == 0x04){ /* only cas = 3 supported */
227 /* t_ck = read_spd(9); */
228 /* t_ac = read_spd(10); */
230 else if (tmp == 0x06){ /* 2,3 supported, so use 2 */
232 /* t_ck = read_spd(23); */
233 /* t_ac = read_spd(24); */
236 SPD_ERR("SDRAM - unsupported CAS latency \n");
239 /* get some timing values, t_rp,t_rcd,t_ras,t_rc
242 t_rcd = read_spd(29);
243 t_ras = read_spd(30);
246 /* The following timing calcs subtract 1 before deviding.
247 * this has effect of using ceiling instead of floor rounding,
248 * and also subtracting 1 to convert number to reg value
251 sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT;
253 sdram0_tr |= (((t_rp - 1)/bus_period) & 0x3) << SDRAM0_TR_PTA_SHIFT;
255 tmp = ((t_rc - t_rcd - t_rp -1) / bus_period) & 0x3;
257 sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT;
258 /* set LDF = 2 cycles, reg value = 1 */
259 sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT;
260 /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
261 tmp = ( (t_rc - 1) / bus_period)-3;
264 sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT;
265 /* set RCD = t_rcd/bus_period*/
266 sdram0_tr |= (((t_rcd - 1) / bus_period) &0x3) << SDRAM0_TR_RCD_SHIFT ;
269 /*------------------------------------------------------------------
270 configure RTR register
271 -------------------------------------------------------------------*/
274 tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */
295 SPD_ERR("SDRAM - Bad refresh period \n");
297 /* convert from nsec to bus cycles */
298 tmp = tmp/bus_period;
299 sdram0_rtr = (tmp & 0x3ff8)<< SDRAM0_RTR_SHIFT;
301 /*------------------------------------------------------------------
302 determine the number of banks used
303 -------------------------------------------------------------------*/
304 /* byte 7:6 is module data width */
306 SPD_ERR("SDRAM - unsupported module width\n");
309 SPD_ERR("SDRAM - unsupported module width\n");
311 bank_cnt=1; /* one bank per sdram side */
313 bank_cnt=2; /* need two banks per side */
315 bank_cnt=4; /* need four banks per side */
317 SPD_ERR("SDRAM - unsupported module width\n");
319 /* byte 5 is the module row count (refered to as dimm "sides") */
322 else if(tmp==2) bank_cnt *=2;
323 else if(tmp==4) bank_cnt *=4;
324 else bank_cnt = 8; /* 8 is an error code */
326 if(bank_cnt > 4) /* we only have 4 banks to work with */
327 SPD_ERR("SDRAM - unsupported module rows for this width\n");
329 /* now check for ECC ability of module. We only support ECC
330 * on 32 bit wide devices with 8 bit ECC.
332 if ( (read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8) ){
333 sdram0_ecccfg=0xf<<SDRAM0_ECCCFG_SHIFT;
341 /*------------------------------------------------------------------
343 -------------------------------------------------------------------*/
344 /* calculate total size and do sanity check */
346 total_size=1<<22; /* total_size = 4MB */
347 /* now multiply 4M by the smallest device row density */
348 /* note that we don't support asymetric rows */
349 while (((tmp & 0x0001) == 0) && (tmp != 0)){
350 total_size= total_size<<1;
353 total_size *= read_spd(5); /* mult by module rows (dimm sides) */
355 /*------------------------------------------------------------------
356 map rows * cols * banks to a mode
357 -------------------------------------------------------------------*/
372 SPD_ERR("SDRAM - unsupported mode\n");
386 SPD_ERR("SDRAM - unsupported mode\n");
397 if (read_spd(17) ==2 )
406 SPD_ERR("SDRAM - unsupported mode\n");
410 SPD_ERR("SDRAM - unsupported mode\n");
413 /*------------------------------------------------------------------
414 using the calculated values, compute the bank
415 config register values.
416 -------------------------------------------------------------------*/
421 /* compute the size of each bank */
422 bank_size = total_size / bank_cnt;
423 /* convert bank size to bank size code for ppc4xx
424 by takeing log2(bank_size) - 22 */
425 tmp=bank_size; /* start with tmp = bank_size */
426 bank_code=0; /* and bank_code = 0 */
427 while (tmp>1){ /* this takes log2 of tmp */
428 bank_code++; /* and stores result in bank_code */
430 } /* bank_code is now log2(bank_size) */
431 bank_code-=22; /* subtract 22 to get the code */
433 tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
434 sdram0_b0cr = (bank_size) * 0 | tmp;
435 #ifndef CONFIG_405EP /* not on PPC405EP */
436 if(bank_cnt>1) sdram0_b2cr = (bank_size) * 1 | tmp;
437 if(bank_cnt>2) sdram0_b1cr = (bank_size) * 2 | tmp;
438 if(bank_cnt>3) sdram0_b3cr = (bank_size) * 3 | tmp;
440 /* PPC405EP chip only supports two SDRAM banks */
441 if(bank_cnt>1) sdram0_b1cr = (bank_size) * 1 | tmp;
442 if(bank_cnt>2) total_size -= (bank_size) * (bank_cnt - 2);
447 * enable sdram controller DCE=1
448 * enable burst read prefetch to 32 bytes BRPF=2
449 * leave other functions off
452 /*------------------------------------------------------------------
453 now that we've done our calculations, we are ready to
454 program all the registers.
455 -------------------------------------------------------------------*/
458 #define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
459 /* disable memcontroller so updates work */
461 mtsdram0( mem_mcopt1, sdram0_cfg );
463 #ifndef CONFIG_405EP /* not on PPC405EP */
464 mtsdram0( mem_besra , sdram0_besr0 );
465 mtsdram0( mem_besrb , sdram0_besr1 );
466 mtsdram0( mem_ecccf , sdram0_ecccfg );
467 mtsdram0( mem_eccerr, sdram0_eccesr );
469 mtsdram0( mem_rtr , sdram0_rtr );
470 mtsdram0( mem_pmit , sdram0_pmit );
471 mtsdram0( mem_mb0cf , sdram0_b0cr );
472 mtsdram0( mem_mb1cf , sdram0_b1cr );
473 #ifndef CONFIG_405EP /* not on PPC405EP */
474 mtsdram0( mem_mb2cf , sdram0_b2cr );
475 mtsdram0( mem_mb3cf , sdram0_b3cr );
477 mtsdram0( mem_sdtr1 , sdram0_tr );
479 /* SDRAM have a power on delay, 500 micro should do */
481 sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
482 if(ecc_on) sdram0_cfg |= SDRAM0_CFG_MEMCHK;
483 mtsdram0( mem_mcopt1, sdram0_cfg );
486 /* kernel 2.4.2 from mvista has a bug with memory over 128MB */
487 #ifdef MVISTA_MEM_BUG
488 if (total_size > 128*1024*1024 )
489 total_size=128*1024*1024;
494 int spd_read(uint addr)
498 if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0)
504 #else /* CONFIG_440 */
506 /*-----------------------------------------------------------------------------
507 | Memory Controller Options 0
508 +-----------------------------------------------------------------------------*/
509 #define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */
510 #define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */
511 #define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */
512 #define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */
513 #define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */
514 #define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */
515 #define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */
516 #define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */
517 #define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */
518 #define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */
519 #define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */
520 #define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */
522 /*-----------------------------------------------------------------------------
523 | Memory Controller Options 1
524 +-----------------------------------------------------------------------------*/
525 #define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */
526 #define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */
528 /*-----------------------------------------------------------------------------+
529 | SDRAM DEVPOT Options
530 +-----------------------------------------------------------------------------*/
531 #define SDRAM_DEVOPT_DLL 0x80000000
532 #define SDRAM_DEVOPT_DS 0x40000000
534 /*-----------------------------------------------------------------------------+
535 | SDRAM MCSTS Options
536 +-----------------------------------------------------------------------------*/
537 #define SDRAM_MCSTS_MRSC 0x80000000
538 #define SDRAM_MCSTS_SRMS 0x40000000
539 #define SDRAM_MCSTS_CIS 0x20000000
541 /*-----------------------------------------------------------------------------
542 | SDRAM Refresh Timer Register
543 +-----------------------------------------------------------------------------*/
544 #define SDRAM_RTR_RINT_MASK 0xFFFF0000
545 #define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK)
546 #define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
548 /*-----------------------------------------------------------------------------+
549 | SDRAM UABus Base Address Reg
550 +-----------------------------------------------------------------------------*/
551 #define SDRAM_UABBA_UBBA_MASK 0x0000000F
553 /*-----------------------------------------------------------------------------+
554 | Memory Bank 0-7 configuration
555 +-----------------------------------------------------------------------------*/
556 #define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */
557 #define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */
558 #define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */
559 #define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */
560 #define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */
561 #define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */
562 #define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */
563 #define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */
564 #define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */
565 #define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */
566 #define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */
567 #define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */
568 #define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */
569 #define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */
570 #define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */
572 /*-----------------------------------------------------------------------------+
574 +-----------------------------------------------------------------------------*/
575 #define SDRAM_TR0_SDWR_MASK 0x80000000
576 #define SDRAM_TR0_SDWR_2_CLK 0x00000000
577 #define SDRAM_TR0_SDWR_3_CLK 0x80000000
578 #define SDRAM_TR0_SDWD_MASK 0x40000000
579 #define SDRAM_TR0_SDWD_0_CLK 0x00000000
580 #define SDRAM_TR0_SDWD_1_CLK 0x40000000
581 #define SDRAM_TR0_SDCL_MASK 0x01800000
582 #define SDRAM_TR0_SDCL_2_0_CLK 0x00800000
583 #define SDRAM_TR0_SDCL_2_5_CLK 0x01000000
584 #define SDRAM_TR0_SDCL_3_0_CLK 0x01800000
585 #define SDRAM_TR0_SDPA_MASK 0x000C0000
586 #define SDRAM_TR0_SDPA_2_CLK 0x00040000
587 #define SDRAM_TR0_SDPA_3_CLK 0x00080000
588 #define SDRAM_TR0_SDPA_4_CLK 0x000C0000
589 #define SDRAM_TR0_SDCP_MASK 0x00030000
590 #define SDRAM_TR0_SDCP_2_CLK 0x00000000
591 #define SDRAM_TR0_SDCP_3_CLK 0x00010000
592 #define SDRAM_TR0_SDCP_4_CLK 0x00020000
593 #define SDRAM_TR0_SDCP_5_CLK 0x00030000
594 #define SDRAM_TR0_SDLD_MASK 0x0000C000
595 #define SDRAM_TR0_SDLD_1_CLK 0x00000000
596 #define SDRAM_TR0_SDLD_2_CLK 0x00004000
597 #define SDRAM_TR0_SDRA_MASK 0x0000001C
598 #define SDRAM_TR0_SDRA_6_CLK 0x00000000
599 #define SDRAM_TR0_SDRA_7_CLK 0x00000004
600 #define SDRAM_TR0_SDRA_8_CLK 0x00000008
601 #define SDRAM_TR0_SDRA_9_CLK 0x0000000C
602 #define SDRAM_TR0_SDRA_10_CLK 0x00000010
603 #define SDRAM_TR0_SDRA_11_CLK 0x00000014
604 #define SDRAM_TR0_SDRA_12_CLK 0x00000018
605 #define SDRAM_TR0_SDRA_13_CLK 0x0000001C
606 #define SDRAM_TR0_SDRD_MASK 0x00000003
607 #define SDRAM_TR0_SDRD_2_CLK 0x00000001
608 #define SDRAM_TR0_SDRD_3_CLK 0x00000002
609 #define SDRAM_TR0_SDRD_4_CLK 0x00000003
611 /*-----------------------------------------------------------------------------+
613 +-----------------------------------------------------------------------------*/
614 #define SDRAM_TR1_RDSS_MASK 0xC0000000
615 #define SDRAM_TR1_RDSS_TR0 0x00000000
616 #define SDRAM_TR1_RDSS_TR1 0x40000000
617 #define SDRAM_TR1_RDSS_TR2 0x80000000
618 #define SDRAM_TR1_RDSS_TR3 0xC0000000
619 #define SDRAM_TR1_RDSL_MASK 0x00C00000
620 #define SDRAM_TR1_RDSL_STAGE1 0x00000000
621 #define SDRAM_TR1_RDSL_STAGE2 0x00400000
622 #define SDRAM_TR1_RDSL_STAGE3 0x00800000
623 #define SDRAM_TR1_RDCD_MASK 0x00000800
624 #define SDRAM_TR1_RDCD_RCD_0_0 0x00000000
625 #define SDRAM_TR1_RDCD_RCD_1_2 0x00000800
626 #define SDRAM_TR1_RDCT_MASK 0x000001FF
627 #define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK)
628 #define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
629 #define SDRAM_TR1_RDCT_MIN 0x00000000
630 #define SDRAM_TR1_RDCT_MAX 0x000001FF
632 /*-----------------------------------------------------------------------------+
633 | SDRAM WDDCTR Options
634 +-----------------------------------------------------------------------------*/
635 #define SDRAM_WDDCTR_WRCP_MASK 0xC0000000
636 #define SDRAM_WDDCTR_WRCP_0DEG 0x00000000
637 #define SDRAM_WDDCTR_WRCP_90DEG 0x40000000
638 #define SDRAM_WDDCTR_WRCP_180DEG 0x80000000
639 #define SDRAM_WDDCTR_DCD_MASK 0x000001FF
641 /*-----------------------------------------------------------------------------+
642 | SDRAM CLKTR Options
643 +-----------------------------------------------------------------------------*/
644 #define SDRAM_CLKTR_CLKP_MASK 0xC0000000
645 #define SDRAM_CLKTR_CLKP_0DEG 0x00000000
646 #define SDRAM_CLKTR_CLKP_90DEG 0x40000000
647 #define SDRAM_CLKTR_CLKP_180DEG 0x80000000
648 #define SDRAM_CLKTR_DCDT_MASK 0x000001FF
650 /*-----------------------------------------------------------------------------+
651 | SDRAM DLYCAL Options
652 +-----------------------------------------------------------------------------*/
653 #define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
654 #define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
655 #define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
657 /*-----------------------------------------------------------------------------+
659 +-----------------------------------------------------------------------------*/
660 #define DEFAULT_SPD_ADDR1 0x53
661 #define DEFAULT_SPD_ADDR2 0x52
662 #define ONE_BILLION 1000000000
663 #define MAXBANKS 4 /* at most 4 dimm banks */
664 #define MAX_SPD_BYTES 256
665 #define NUMHALFCYCLES 4
666 #define NUMMEMTESTS 8
667 #define NUMMEMWORDS 8
672 const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
673 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
674 0xFFFFFFFF, 0xFFFFFFFF},
675 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
676 0x00000000, 0x00000000},
677 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
678 0x55555555, 0x55555555},
679 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
680 0xAAAAAAAA, 0xAAAAAAAA},
681 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
682 0x5A5A5A5A, 0x5A5A5A5A},
683 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
684 0xA5A5A5A5, 0xA5A5A5A5},
685 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
686 0x55AA55AA, 0x55AA55AA},
687 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
688 0xAA55AA55, 0xAA55AA55}
692 unsigned char spd_read(uchar chip, uint addr);
694 void get_spd_info(unsigned long* dimm_populated,
695 unsigned char* iic0_dimm_addr,
696 unsigned long num_dimm_banks);
699 (unsigned long* dimm_populated,
700 unsigned char* iic0_dimm_addr,
701 unsigned long num_dimm_banks);
704 (unsigned long* dimm_populated,
705 unsigned char* iic0_dimm_addr,
706 unsigned long num_dimm_banks);
708 void program_cfg0(unsigned long* dimm_populated,
709 unsigned char* iic0_dimm_addr,
710 unsigned long num_dimm_banks);
712 void program_cfg1(unsigned long* dimm_populated,
713 unsigned char* iic0_dimm_addr,
714 unsigned long num_dimm_banks);
716 void program_rtr (unsigned long* dimm_populated,
717 unsigned char* iic0_dimm_addr,
718 unsigned long num_dimm_banks);
720 void program_tr0 (unsigned long* dimm_populated,
721 unsigned char* iic0_dimm_addr,
722 unsigned long num_dimm_banks);
724 void program_tr1 (void);
726 void program_ecc (unsigned long num_bytes);
729 long program_bxcr(unsigned long* dimm_populated,
730 unsigned char* iic0_dimm_addr,
731 unsigned long num_dimm_banks);
734 * This function is reading data from the DIMM module EEPROM over the SPD bus
735 * and uses that to program the sdram controller.
737 * This works on boards that has the same schematics that the IBM walnut has.
739 * BUG: Don't handle ECC memory
740 * BUG: A few values in the TR register is currently hardcoded
743 long int spd_sdram(void) {
744 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
745 unsigned long dimm_populated[sizeof(iic0_dimm_addr)];
746 unsigned long total_size;
749 unsigned long num_dimm_banks; /* on board dimm banks */
751 num_dimm_banks = sizeof(iic0_dimm_addr);
754 * Make sure I2C controller is initialized
757 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
760 * Read the SPD information using I2C interface. Check to see if the
761 * DIMM slots are populated.
763 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
766 * Check the memory type for the dimms plugged.
768 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
771 * Check the voltage type for the dimms plugged.
773 check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
776 * program 440GP SDRAM controller options (SDRAM0_CFG0)
778 program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
781 * program 440GP SDRAM controller options (SDRAM0_CFG1)
783 program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
786 * program SDRAM refresh register (SDRAM0_RTR)
788 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
791 * program SDRAM Timing Register 0 (SDRAM0_TR0)
793 program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
796 * program the BxCR registers to find out total sdram installed
798 total_size = program_bxcr(dimm_populated, iic0_dimm_addr,
802 * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
804 mtsdram(mem_clktr, 0x40000000);
807 * delay to ensure 200 usec has elapsed
812 * enable the memory controller
814 mfsdram(mem_cfg0, cfg0);
815 mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN);
818 * wait for SDRAM_CFG0_DC_EN to complete
821 mfsdram(mem_mcsts, mcsts);
822 if ((mcsts & SDRAM_MCSTS_MRSC) != 0) {
828 * program SDRAM Timing Register 1, adding some delays
833 * if ECC is enabled, initialize parity bits
839 unsigned char spd_read(uchar chip, uint addr) {
840 unsigned char data[2];
842 if (i2c_read(chip, addr, 1, data, 1) == 0)
848 void get_spd_info(unsigned long* dimm_populated,
849 unsigned char* iic0_dimm_addr,
850 unsigned long num_dimm_banks)
852 unsigned long dimm_num;
853 unsigned long dimm_found;
854 unsigned char num_of_bytes;
855 unsigned char total_size;
858 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
862 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
863 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
865 if ((num_of_bytes != 0) && (total_size != 0)) {
866 dimm_populated[dimm_num] = TRUE;
869 printf("DIMM slot %lu: populated\n", dimm_num);
873 dimm_populated[dimm_num] = FALSE;
875 printf("DIMM slot %lu: Not populated\n", dimm_num);
880 if (dimm_found == FALSE) {
881 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
886 void check_mem_type(unsigned long* dimm_populated,
887 unsigned char* iic0_dimm_addr,
888 unsigned long num_dimm_banks)
890 unsigned long dimm_num;
891 unsigned char dimm_type;
893 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
894 if (dimm_populated[dimm_num] == TRUE) {
895 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
899 printf("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
903 printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
905 printf("Only DDR SDRAM DIMMs are supported.\n");
906 printf("Replace the DIMM module with a supported DIMM.\n\n");
915 void check_volt_type(unsigned long* dimm_populated,
916 unsigned char* iic0_dimm_addr,
917 unsigned long num_dimm_banks)
919 unsigned long dimm_num;
920 unsigned long voltage_type;
922 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
923 if (dimm_populated[dimm_num] == TRUE) {
924 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
925 if (voltage_type != 0x04) {
926 printf("ERROR: DIMM %lu with unsupported voltage level.\n",
932 printf("DIMM %lu voltage level supported.\n", dimm_num);
940 void program_cfg0(unsigned long* dimm_populated,
941 unsigned char* iic0_dimm_addr,
942 unsigned long num_dimm_banks)
944 unsigned long dimm_num;
946 unsigned long ecc_enabled;
948 unsigned char attributes;
949 unsigned long data_width;
950 unsigned long dimm_32bit;
951 unsigned long dimm_64bit;
954 * get Memory Controller Options 0 data
956 mfsdram(mem_cfg0, cfg0);
961 cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK |
962 SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
963 SDRAM_CFG0_DMWD_MASK |
964 SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
968 * FIXME: assume the DDR SDRAMs in both banks are the same
971 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
972 if (dimm_populated[dimm_num] == TRUE) {
973 ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
979 * program Registered DIMM Enable
981 attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
982 if ((attributes & 0x02) != 0x00) {
983 cfg0 |= SDRAM_CFG0_RDEN;
987 * program DDR SDRAM Data Width
990 (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
991 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
992 if (data_width == 64 || data_width == 72) {
994 cfg0 |= SDRAM_CFG0_DMWD_64;
996 else if (data_width == 32 || data_width == 40) {
998 cfg0 |= SDRAM_CFG0_DMWD_32;
1001 printf("WARNING: DIMM with datawidth of %lu bits.\n",
1003 printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
1011 * program Memory Data Error Checking
1013 if (ecc_enabled == TRUE) {
1014 cfg0 |= SDRAM_CFG0_MCHK_GEN;
1017 cfg0 |= SDRAM_CFG0_MCHK_NON;
1021 * program Page Management Unit
1023 cfg0 |= SDRAM_CFG0_PMUD;
1026 * program Memory Controller Options 0
1027 * Note: DCEN must be enabled after all DDR SDRAM controller
1028 * configuration registers get initialized.
1030 mtsdram(mem_cfg0, cfg0);
1033 void program_cfg1(unsigned long* dimm_populated,
1034 unsigned char* iic0_dimm_addr,
1035 unsigned long num_dimm_banks)
1038 mfsdram(mem_cfg1, cfg1);
1041 * Self-refresh exit, disable PM
1043 cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN);
1046 * program Memory Controller Options 1
1048 mtsdram(mem_cfg1, cfg1);
1051 void program_rtr (unsigned long* dimm_populated,
1052 unsigned char* iic0_dimm_addr,
1053 unsigned long num_dimm_banks)
1055 unsigned long dimm_num;
1056 unsigned long bus_period_x_10;
1057 unsigned long refresh_rate = 0;
1058 unsigned char refresh_rate_type;
1059 unsigned long refresh_interval;
1060 unsigned long sdram_rtr;
1061 PPC440_SYS_INFO sys_info;
1064 * get the board info
1066 get_sys_info(&sys_info);
1067 bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
1070 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1071 if (dimm_populated[dimm_num] == TRUE) {
1072 refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
1073 switch (refresh_rate_type) {
1075 refresh_rate = 15625;
1078 refresh_rate = 15625/4;
1081 refresh_rate = 15625/2;
1084 refresh_rate = 15626*2;
1087 refresh_rate = 15625*4;
1090 refresh_rate = 15625*8;
1093 printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
1095 printf("Replace the DIMM module with a supported DIMM.\n");
1103 refresh_interval = refresh_rate * 10 / bus_period_x_10;
1104 sdram_rtr = (refresh_interval & 0x3ff8) << 16;
1107 * program Refresh Timer Register (SDRAM0_RTR)
1109 mtsdram(mem_rtr, sdram_rtr);
1112 void program_tr0 (unsigned long* dimm_populated,
1113 unsigned char* iic0_dimm_addr,
1114 unsigned long num_dimm_banks)
1116 unsigned long dimm_num;
1118 unsigned char wcsbc;
1119 unsigned char t_rp_ns;
1120 unsigned char t_rcd_ns;
1121 unsigned char t_ras_ns;
1122 unsigned long t_rp_clk;
1123 unsigned long t_ras_rcd_clk;
1124 unsigned long t_rcd_clk;
1125 unsigned long t_rfc_clk;
1126 unsigned long plb_check;
1127 unsigned char cas_bit;
1128 unsigned long cas_index;
1129 unsigned char cas_2_0_available;
1130 unsigned char cas_2_5_available;
1131 unsigned char cas_3_0_available;
1132 unsigned long cycle_time_ns_x_10[3];
1133 unsigned long tcyc_3_0_ns_x_10;
1134 unsigned long tcyc_2_5_ns_x_10;
1135 unsigned long tcyc_2_0_ns_x_10;
1136 unsigned long tcyc_reg;
1137 unsigned long bus_period_x_10;
1138 PPC440_SYS_INFO sys_info;
1139 unsigned long residue;
1142 * get the board info
1144 get_sys_info(&sys_info);
1145 bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
1148 * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
1150 mfsdram(mem_tr0, tr0);
1151 tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
1152 SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
1153 SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
1154 SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
1163 cas_2_0_available = TRUE;
1164 cas_2_5_available = TRUE;
1165 cas_3_0_available = TRUE;
1166 tcyc_2_0_ns_x_10 = 0;
1167 tcyc_2_5_ns_x_10 = 0;
1168 tcyc_3_0_ns_x_10 = 0;
1170 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1171 if (dimm_populated[dimm_num] == TRUE) {
1172 wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
1173 t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
1174 t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
1175 t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
1176 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1178 for (cas_index = 0; cas_index < 3; cas_index++) {
1179 switch (cas_index) {
1181 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1184 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1187 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1191 if ((tcyc_reg & 0x0F) >= 10) {
1192 printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
1197 cycle_time_ns_x_10[cas_index] =
1198 (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
1203 if ((cas_bit & 0x80) != 0) {
1206 else if ((cas_bit & 0x40) != 0) {
1209 else if ((cas_bit & 0x20) != 0) {
1213 if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
1214 tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
1218 if (cas_index != 0) {
1221 cas_3_0_available = FALSE;
1224 if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
1225 tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
1229 if (cas_index != 0) {
1232 cas_2_5_available = FALSE;
1235 if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
1236 tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
1240 if (cas_index != 0) {
1243 cas_2_0_available = FALSE;
1251 * Program SD_WR and SD_WCSBC fields
1253 tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */
1256 tr0 |= SDRAM_TR0_SDWD_0_CLK;
1259 tr0 |= SDRAM_TR0_SDWD_1_CLK;
1264 * Program SD_CASL field
1266 if ((cas_2_0_available == TRUE) &&
1267 (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
1268 tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
1270 else if((cas_2_5_available == TRUE) &&
1271 (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
1272 tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
1274 else if((cas_3_0_available == TRUE) &&
1275 (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
1276 tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
1279 printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
1280 printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1281 printf("Make sure the PLB speed is within the supported range.\n");
1286 * Calculate Trp in clock cycles and round up if necessary
1287 * Program SD_PTA field
1289 t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION;
1290 plb_check = ONE_BILLION * t_rp_clk / t_rp_ns;
1291 if (sys_info.freqPLB != plb_check) {
1294 switch ((unsigned long)t_rp_clk) {
1298 tr0 |= SDRAM_TR0_SDPA_2_CLK;
1301 tr0 |= SDRAM_TR0_SDPA_3_CLK;
1304 tr0 |= SDRAM_TR0_SDPA_4_CLK;
1309 * Program SD_CTP field
1311 t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION;
1312 plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns);
1313 if (sys_info.freqPLB != plb_check) {
1316 switch (t_ras_rcd_clk) {
1320 tr0 |= SDRAM_TR0_SDCP_2_CLK;
1323 tr0 |= SDRAM_TR0_SDCP_3_CLK;
1326 tr0 |= SDRAM_TR0_SDCP_4_CLK;
1329 tr0 |= SDRAM_TR0_SDCP_5_CLK;
1334 * Program SD_LDF field
1336 tr0 |= SDRAM_TR0_SDLD_2_CLK;
1339 * Program SD_RFTA field
1340 * FIXME tRFC hardcoded as 75 nanoseconds
1342 t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75);
1343 residue = sys_info.freqPLB % (ONE_BILLION / 75);
1344 if (residue >= (ONE_BILLION / 150)) {
1347 switch (t_rfc_clk) {
1355 tr0 |= SDRAM_TR0_SDRA_6_CLK;
1358 tr0 |= SDRAM_TR0_SDRA_7_CLK;
1361 tr0 |= SDRAM_TR0_SDRA_8_CLK;
1364 tr0 |= SDRAM_TR0_SDRA_9_CLK;
1367 tr0 |= SDRAM_TR0_SDRA_10_CLK;
1370 tr0 |= SDRAM_TR0_SDRA_11_CLK;
1373 tr0 |= SDRAM_TR0_SDRA_12_CLK;
1376 tr0 |= SDRAM_TR0_SDRA_13_CLK;
1381 * Program SD_RCD field
1383 t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION;
1384 plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns;
1385 if (sys_info.freqPLB != plb_check) {
1388 switch (t_rcd_clk) {
1392 tr0 |= SDRAM_TR0_SDRD_2_CLK;
1395 tr0 |= SDRAM_TR0_SDRD_3_CLK;
1398 tr0 |= SDRAM_TR0_SDRD_4_CLK;
1403 printf("tr0: %x\n", tr0);
1405 mtsdram(mem_tr0, tr0);
1408 void program_tr1 (void)
1413 unsigned long ecc_temp;
1414 unsigned long dlycal;
1415 unsigned long dly_val;
1416 unsigned long i, j, k;
1417 unsigned long bxcr_num;
1418 unsigned long max_pass_length;
1419 unsigned long current_pass_length;
1420 unsigned long current_fail_length;
1421 unsigned long current_start;
1422 unsigned long rdclt;
1423 unsigned long rdclt_offset;
1427 unsigned char window_found;
1428 unsigned char fail_found;
1429 unsigned char pass_found;
1430 unsigned long * membase;
1431 PPC440_SYS_INFO sys_info;
1434 * get the board info
1436 get_sys_info(&sys_info);
1439 * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
1441 mfsdram(mem_tr1, tr1);
1442 tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
1443 SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
1445 mfsdram(mem_tr0, tr0);
1446 if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
1447 (sys_info.freqPLB > 100000000)) {
1448 tr1 |= SDRAM_TR1_RDSS_TR2;
1449 tr1 |= SDRAM_TR1_RDSL_STAGE3;
1450 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1453 tr1 |= SDRAM_TR1_RDSS_TR1;
1454 tr1 |= SDRAM_TR1_RDSL_STAGE2;
1455 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1459 * save CFG0 ECC setting to a temporary variable and turn ECC off
1461 mfsdram(mem_cfg0, cfg0);
1462 ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
1463 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
1466 * get the delay line calibration register value
1468 mfsdram(mem_dlycal, dlycal);
1469 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
1471 max_pass_length = 0;
1474 current_pass_length = 0;
1475 current_fail_length = 0;
1478 window_found = FALSE;
1482 printf("Starting memory test ");
1484 for (k = 0; k < NUMHALFCYCLES; k++) {
1485 for (rdclt = 0; rdclt < dly_val; rdclt++) {
1487 * Set the timing reg for the test.
1489 mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
1491 for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
1492 mtdcr(memcfga, mem_b0cr + (bxcr_num<<2));
1493 if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
1494 /* Bank is enabled */
1495 membase = (unsigned long*)
1496 (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
1499 * Run the short memory test
1501 for (i = 0; i < NUMMEMTESTS; i++) {
1502 for (j = 0; j < NUMMEMWORDS; j++) {
1503 membase[j] = test[i][j];
1504 ppcDcbf((unsigned long)&(membase[j]));
1507 for (j = 0; j < NUMMEMWORDS; j++) {
1508 if (membase[j] != test[i][j]) {
1509 ppcDcbf((unsigned long)&(membase[j]));
1512 ppcDcbf((unsigned long)&(membase[j]));
1515 if (j < NUMMEMWORDS) {
1521 * see if the rdclt value passed
1523 if (i < NUMMEMTESTS) {
1529 if (bxcr_num == MAXBXCR) {
1530 if (fail_found == TRUE) {
1532 if (current_pass_length == 0) {
1533 current_start = rdclt_offset + rdclt;
1536 current_fail_length = 0;
1537 current_pass_length++;
1539 if (current_pass_length > max_pass_length) {
1540 max_pass_length = current_pass_length;
1541 max_start = current_start;
1542 max_end = rdclt_offset + rdclt;
1547 current_pass_length = 0;
1548 current_fail_length++;
1550 if (current_fail_length >= (dly_val>>2)) {
1551 if (fail_found == FALSE) {
1554 else if (pass_found == TRUE) {
1555 window_found = TRUE;
1564 if (window_found == TRUE) {
1568 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1569 rdclt_offset += dly_val;
1576 * make sure we find the window
1578 if (window_found == FALSE) {
1579 printf("ERROR: Cannot determine a common read delay.\n");
1584 * restore the orignal ECC setting
1586 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
1589 * set the SDRAM TR1 RDCD value
1591 tr1 &= ~SDRAM_TR1_RDCD_MASK;
1592 if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) {
1593 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1596 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1600 * set the SDRAM TR1 RDCLT value
1602 tr1 &= ~SDRAM_TR1_RDCT_MASK;
1603 while (max_end >= (dly_val<<1)) {
1604 max_end -= (dly_val<<1);
1605 max_start -= (dly_val<<1);
1608 rdclt_average = ((max_start + max_end) >> 1);
1609 if (rdclt_average >= 0x60)
1612 if (rdclt_average < 0) {
1616 if (rdclt_average >= dly_val) {
1617 rdclt_average -= dly_val;
1618 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1620 tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
1623 printf("tr1: %x\n", tr1);
1626 * program SDRAM Timing Register 1 TR1
1628 mtsdram(mem_tr1, tr1);
1631 unsigned long program_bxcr(unsigned long* dimm_populated,
1632 unsigned char* iic0_dimm_addr,
1633 unsigned long num_dimm_banks)
1635 unsigned long dimm_num;
1636 unsigned long bxcr_num;
1637 unsigned long bank_base_addr;
1638 unsigned long bank_size_bytes;
1642 unsigned char num_row_addr;
1643 unsigned char num_col_addr;
1644 unsigned char num_banks;
1645 unsigned char bank_size_id;
1649 * Set the BxCR regs. First, wipe out the bank config registers.
1651 for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
1652 mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
1653 mtdcr(memcfgd, 0x00000000);
1657 * reset the bank_base address
1659 bank_base_addr = CFG_SDRAM_BASE;
1661 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1662 if (dimm_populated[dimm_num] == TRUE) {
1663 num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
1664 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
1665 num_banks = spd_read(iic0_dimm_addr[dimm_num], 5);
1666 bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
1669 * Set the SDRAM0_BxCR regs
1672 bank_size_bytes = 4 * 1024 * 1024 * bank_size_id;
1673 switch (bank_size_id) {
1675 cr |= SDRAM_BXCR_SDSZ_8;
1678 cr |= SDRAM_BXCR_SDSZ_16;
1681 cr |= SDRAM_BXCR_SDSZ_32;
1684 cr |= SDRAM_BXCR_SDSZ_64;
1687 cr |= SDRAM_BXCR_SDSZ_128;
1690 cr |= SDRAM_BXCR_SDSZ_256;
1693 cr |= SDRAM_BXCR_SDSZ_512;
1696 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1698 printf("ERROR: Unsupported value for the banksize: %d.\n",
1700 printf("Replace the DIMM module with a supported DIMM.\n\n");
1704 switch (num_col_addr) {
1706 cr |= SDRAM_BXCR_SDAM_1;
1709 cr |= SDRAM_BXCR_SDAM_2;
1712 cr |= SDRAM_BXCR_SDAM_3;
1715 cr |= SDRAM_BXCR_SDAM_4;
1718 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1720 printf("ERROR: Unsupported value for number of "
1721 "column addresses: %d.\n", num_col_addr);
1722 printf("Replace the DIMM module with a supported DIMM.\n\n");
1729 cr |= SDRAM_BXCR_SDBE;
1731 /*------------------------------------------------------------------
1732 | This next section is hardware dependent and must be programmed
1733 | to match the hardware.
1734 +-----------------------------------------------------------------*/
1735 if (dimm_num == 0) {
1736 for (i = 0; i < num_banks; i++) {
1737 mtdcr(memcfga, mem_b0cr + (i << 2));
1738 temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
1739 SDRAM_BXCR_SDSZ_MASK |
1740 SDRAM_BXCR_SDAM_MASK |
1743 cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
1745 bank_base_addr += bank_size_bytes;
1749 for (i = 0; i < num_banks; i++) {
1750 mtdcr(memcfga, mem_b2cr + (i << 2));
1751 temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
1752 SDRAM_BXCR_SDSZ_MASK |
1753 SDRAM_BXCR_SDAM_MASK |
1756 cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
1758 bank_base_addr += bank_size_bytes;
1764 return(bank_base_addr);
1767 void program_ecc (unsigned long num_bytes)
1769 unsigned long bank_base_addr;
1770 unsigned long current_address;
1771 unsigned long end_address;
1772 unsigned long address_increment;
1776 * get Memory Controller Options 0 data
1778 mfsdram(mem_cfg0, cfg0);
1781 * reset the bank_base address
1783 bank_base_addr = CFG_SDRAM_BASE;
1785 if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) {
1786 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
1787 SDRAM_CFG0_MCHK_GEN);
1789 if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) {
1790 address_increment = 4;
1793 address_increment = 8;
1796 current_address = (unsigned long)(bank_base_addr);
1797 end_address = (unsigned long)(bank_base_addr) + num_bytes;
1799 while (current_address < end_address) {
1800 *((unsigned long*)current_address) = 0x00000000;
1801 current_address += address_increment;
1804 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
1805 SDRAM_CFG0_MCHK_CHK);
1809 #endif /* CONFIG_440 */
1811 #endif /* CONFIG_SPD_EEPROM */