3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 /*------------------------------------------------------------------------------+ */
25 * This source code has been made available to you by IBM on an AS-IS
26 * basis. Anyone receiving this source is licensed under IBM
27 * copyrights to use it in any way he or she deems fit, including
28 * copying it, modifying it, compiling it, and redistributing it either
29 * with or without modifications. No license under IBM patents or
30 * patent applications is to be implied by the copyright license.
32 * Any user of this software should understand that IBM cannot provide
33 * technical support for this software and will not be responsible for
34 * any consequences resulting from the use of this software.
36 * Any person who transfers this source code or any derivative work
37 * must include the IBM copyright notice, this paragraph, and the
38 * preceding two paragraphs in the transferred software.
40 * COPYRIGHT I B M CORPORATION 1995
41 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
43 /*------------------------------------------------------------------------------- */
47 #include <asm/processor.h>
51 #if CONFIG_SERIAL_SOFTWARE_FIFO
55 /*****************************************************************************/
58 #define SPU_BASE 0x40000000
60 #define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */
61 #define spu_LineStat_w 0x04 /* Line Status Register (Set) */
62 #define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */
63 #define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */
64 #define spu_BRateDivh 0x10 /* Baud rate divisor high */
65 #define spu_BRateDivl 0x14 /* Baud rate divisor low */
66 #define spu_CtlReg 0x18 /* Control Register */
67 #define spu_RxCmd 0x1c /* Rx Command Register */
68 #define spu_TxCmd 0x20 /* Tx Command Register */
69 #define spu_RxBuff 0x24 /* Rx data buffer */
70 #define spu_TxBuff 0x24 /* Tx data buffer */
72 /*-----------------------------------------------------------------------------+
73 | Line Status Register.
74 +-----------------------------------------------------------------------------*/
75 #define asyncLSRport1 0x40000000
76 #define asyncLSRport1set 0x40000004
77 #define asyncLSRDataReady 0x80
78 #define asyncLSRFramingError 0x40
79 #define asyncLSROverrunError 0x20
80 #define asyncLSRParityError 0x10
81 #define asyncLSRBreakInterrupt 0x08
82 #define asyncLSRTxHoldEmpty 0x04
83 #define asyncLSRTxShiftEmpty 0x02
85 /*-----------------------------------------------------------------------------+
86 | Handshake Status Register.
87 +-----------------------------------------------------------------------------*/
88 #define asyncHSRport1 0x40000008
89 #define asyncHSRport1set 0x4000000c
90 #define asyncHSRDsr 0x80
91 #define asyncLSRCts 0x40
93 /*-----------------------------------------------------------------------------+
95 +-----------------------------------------------------------------------------*/
96 #define asyncCRport1 0x40000018
97 #define asyncCRNormal 0x00
98 #define asyncCRLoopback 0x40
99 #define asyncCRAutoEcho 0x80
100 #define asyncCRDtr 0x20
101 #define asyncCRRts 0x10
102 #define asyncCRWordLength7 0x00
103 #define asyncCRWordLength8 0x08
104 #define asyncCRParityDisable 0x00
105 #define asyncCRParityEnable 0x04
106 #define asyncCREvenParity 0x00
107 #define asyncCROddParity 0x02
108 #define asyncCRStopBitsOne 0x00
109 #define asyncCRStopBitsTwo 0x01
110 #define asyncCRDisableDtrRts 0x00
112 /*-----------------------------------------------------------------------------+
113 | Receiver Command Register.
114 +-----------------------------------------------------------------------------*/
115 #define asyncRCRport1 0x4000001c
116 #define asyncRCRDisable 0x00
117 #define asyncRCREnable 0x80
118 #define asyncRCRIntDisable 0x00
119 #define asyncRCRIntEnabled 0x20
120 #define asyncRCRDMACh2 0x40
121 #define asyncRCRDMACh3 0x60
122 #define asyncRCRErrorInt 0x10
123 #define asyncRCRPauseEnable 0x08
125 /*-----------------------------------------------------------------------------+
126 | Transmitter Command Register.
127 +-----------------------------------------------------------------------------*/
128 #define asyncTCRport1 0x40000020
129 #define asyncTCRDisable 0x00
130 #define asyncTCREnable 0x80
131 #define asyncTCRIntDisable 0x00
132 #define asyncTCRIntEnabled 0x20
133 #define asyncTCRDMACh2 0x40
134 #define asyncTCRDMACh3 0x60
135 #define asyncTCRTxEmpty 0x10
136 #define asyncTCRErrorInt 0x08
137 #define asyncTCRStopPause 0x04
138 #define asyncTCRBreakGen 0x02
140 /*-----------------------------------------------------------------------------+
141 | Miscellanies defines.
142 +-----------------------------------------------------------------------------*/
143 #define asyncTxBufferport1 0x40000024
144 #define asyncRxBufferport1 0x40000024
145 #define asyncDLABLsbport1 0x40000014
146 #define asyncDLABMsbport1 0x40000010
147 #define asyncXOFFchar 0x13
148 #define asyncXONchar 0x11
152 * Minimal serial functions needed to use one of the SMC ports
153 * as serial console interface.
156 int serial_init (void)
158 DECLARE_GLOBAL_DATA_PTR;
161 unsigned short br_reg;
163 br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
168 out8 (SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
169 out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
170 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
171 out8 (SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */
172 out8 (SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */
173 out8 (SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */
174 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
175 val = in8 (SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
181 void serial_setbrg (void)
183 DECLARE_GLOBAL_DATA_PTR;
185 unsigned short br_reg;
187 br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
189 out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
190 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
194 void serial_putc (const char c)
199 /* load status from handshake register */
200 if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
201 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
203 out8 (SPU_BASE + spu_TxBuff, c); /* Put char */
205 while ((in8 (SPU_BASE + spu_LineStat_rc) & 04) != 04) {
206 if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
207 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
212 void serial_puts (const char *s)
222 unsigned char status = 0;
225 status = in8 (asyncLSRport1);
226 if ((status & asyncLSRDataReady) != 0x0) {
229 if ((status & ( asyncLSRFramingError |
230 asyncLSROverrunError |
231 asyncLSRParityError |
232 asyncLSRBreakInterrupt )) != 0) {
233 (void) out8 (asyncLSRport1,
234 asyncLSRFramingError |
235 asyncLSROverrunError |
236 asyncLSRParityError |
237 asyncLSRBreakInterrupt );
240 return (0x000000ff & (int) in8 (asyncRxBufferport1));
246 unsigned char status;
248 status = in8 (asyncLSRport1);
249 if ((status & asyncLSRDataReady) != 0x0) {
252 if ((status & ( asyncLSRFramingError |
253 asyncLSROverrunError |
254 asyncLSRParityError |
255 asyncLSRBreakInterrupt )) != 0) {
256 (void) out8 (asyncLSRport1,
257 asyncLSRFramingError |
258 asyncLSROverrunError |
259 asyncLSRParityError |
260 asyncLSRBreakInterrupt);
265 #endif /* CONFIG_IOP480 */
268 /*****************************************************************************/
269 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440)
271 #if defined(CONFIG_440)
272 #define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
273 #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
274 #define CR0_MASK 0x3fff0000
275 #define CR0_EXTCLK_ENA 0x00600000
276 #define CR0_UDIV_POS 16
278 #define UART_BASE_PTR 0xF800FFFC; /* pointer to uart base */
279 #define UART0_BASE 0xef600300
280 #define UART1_BASE 0xef600400
281 #define CR0_MASK 0x00001fff
282 #define CR0_EXTCLK_ENA 0x00000c00
283 #define CR0_UDIV_POS 1
286 #define UART_RBR 0x00
287 #define UART_THR 0x00
288 #define UART_IER 0x01
289 #define UART_IIR 0x02
290 #define UART_FCR 0x02
291 #define UART_LCR 0x03
292 #define UART_MCR 0x04
293 #define UART_LSR 0x05
294 #define UART_MSR 0x06
295 #define UART_SCR 0x07
296 #define UART_DLL 0x00
297 #define UART_DLM 0x01
299 /*-----------------------------------------------------------------------------+
300 | Line Status Register.
301 +-----------------------------------------------------------------------------*/
302 /*#define asyncLSRport1 UART0_BASE+0x05 */
303 #define asyncLSRDataReady1 0x01
304 #define asyncLSROverrunError1 0x02
305 #define asyncLSRParityError1 0x04
306 #define asyncLSRFramingError1 0x08
307 #define asyncLSRBreakInterrupt1 0x10
308 #define asyncLSRTxHoldEmpty1 0x20
309 #define asyncLSRTxShiftEmpty1 0x40
310 #define asyncLSRRxFifoError1 0x80
312 /*-----------------------------------------------------------------------------+
313 | Miscellanies defines.
314 +-----------------------------------------------------------------------------*/
315 /*#define asyncTxBufferport1 UART0_BASE+0x00 */
316 /*#define asyncRxBufferport1 UART0_BASE+0x00 */
319 #if CONFIG_SERIAL_SOFTWARE_FIFO
320 /*-----------------------------------------------------------------------------+
322 +-----------------------------------------------------------------------------*/
329 volatile static serial_buffer_t buf_info;
333 #if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
334 static void serial_divs (int baudrate, unsigned long *pudiv,
335 unsigned short *pbdiv )
338 unsigned long div; /* total divisor udiv * bdiv */
339 unsigned long umin; /* minimum udiv */
340 unsigned short diff; /* smallest diff */
341 unsigned long udiv; /* best udiv */
343 unsigned short idiff; /* current diff */
344 unsigned short ibdiv; /* current bdiv */
346 unsigned long est; /* current estimate */
348 get_sys_info( &sysinfo );
350 udiv = 32; /* Assume lowest possible serial clk */
351 div = sysinfo.freqPLB/(16*baudrate); /* total divisor */
352 umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */
353 diff = 32; /* highest possible */
355 /* i is the test udiv value -- start with the largest
356 * possible (32) to minimize serial clock and constrain
359 for( i = 32; i > umin; i-- ){
362 idiff = (est > div) ? (est-div) : (div-est);
365 break; /* can't do better */
367 else if( idiff < diff ){
368 udiv = i; /* best so far */
369 diff = idiff; /* update lowest diff*/
377 #endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */
381 * Minimal serial functions needed to use one of the SMC ports
382 * as serial console interface.
385 #if defined(CONFIG_440)
386 int serial_init (void)
388 DECLARE_GLOBAL_DATA_PTR;
394 #ifdef CFG_EXT_SERIAL_CLOCK
398 reg = mfdcr(cntrl0) & ~CR0_MASK;
399 #ifdef CFG_EXT_SERIAL_CLOCK
400 reg |= CR0_EXTCLK_ENA;
402 tmp = gd->baudrate * 16;
403 bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
405 /* For 440, the cpu clock is on divider chain A, UART on divider
406 * chain B ... so cpu clock is irrelevant. Get the "optimized"
407 * values that are subject to the 1/2 opb clock constraint
409 serial_divs (gd->baudrate, &udiv, &bdiv);
412 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
415 out8 (UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
416 out8 (UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
417 out8 (UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
418 out8 (UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
419 out8 (UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
420 out8 (UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
421 val = in8 (UART0_BASE + UART_LSR); /* clear line status */
422 val = in8 (UART0_BASE + UART_RBR); /* read receive buffer */
423 out8 (UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
424 out8 (UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
429 #else /* !defined(CONFIG_440) */
431 int serial_init (void)
433 DECLARE_GLOBAL_DATA_PTR;
442 reg = mfdcr(cntrl0) & ~CR0_MASK;
443 #ifdef CFG_EXT_SERIAL_CLOCK
444 clk = CFG_EXT_SERIAL_CLOCK;
446 reg |= CR0_EXTCLK_ENA;
449 #ifdef CFG_405_UART_ERRATA_59
450 udiv = 31; /* Errata 59: stuck at 31 */
452 tmp = CFG_BASE_BAUD * 16;
453 udiv = (clk + tmp / 2) / tmp;
457 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
460 tmp = gd->baudrate * udiv * 16;
461 bdiv = (clk + tmp / 2) / tmp;
463 out8 (UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
464 out8 (UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
465 out8 (UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
466 out8 (UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
467 out8 (UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
468 out8 (UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
469 val = in8 (UART0_BASE + UART_LSR); /* clear line status */
470 val = in8 (UART0_BASE + UART_RBR); /* read receive buffer */
471 out8 (UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
472 out8 (UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
477 #endif /* if defined(CONFIG_440) */
479 void serial_setbrg (void)
481 DECLARE_GLOBAL_DATA_PTR;
488 #ifdef CFG_EXT_SERIAL_CLOCK
489 clk = CFG_EXT_SERIAL_CLOCK;
493 udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1;
494 tmp = gd->baudrate * udiv * 16;
495 bdiv = (clk + tmp / 2) / tmp;
497 out8 (UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
498 out8 (UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
499 out8 (UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
500 out8 (UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
504 void serial_putc (const char c)
511 /* check THRE bit, wait for transmiter available */
512 for (i = 1; i < 3500; i++) {
513 if ((in8 (UART0_BASE + UART_LSR) & 0x20) == 0x20)
517 out8 (UART0_BASE + UART_THR, c); /* put character out */
521 void serial_puts (const char *s)
531 unsigned char status = 0;
534 #if defined(CONFIG_HW_WATCHDOG)
535 WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
536 #endif /* CONFIG_HW_WATCHDOG */
537 status = in8 (UART0_BASE + UART_LSR);
538 if ((status & asyncLSRDataReady1) != 0x0) {
541 if ((status & ( asyncLSRFramingError1 |
542 asyncLSROverrunError1 |
543 asyncLSRParityError1 |
544 asyncLSRBreakInterrupt1 )) != 0) {
545 out8 (UART0_BASE + UART_LSR,
546 asyncLSRFramingError1 |
547 asyncLSROverrunError1 |
548 asyncLSRParityError1 |
549 asyncLSRBreakInterrupt1);
552 return (0x000000ff & (int) in8 (UART0_BASE));
558 unsigned char status;
560 status = in8 (UART0_BASE + UART_LSR);
561 if ((status & asyncLSRDataReady1) != 0x0) {
564 if ((status & ( asyncLSRFramingError1 |
565 asyncLSROverrunError1 |
566 asyncLSRParityError1 |
567 asyncLSRBreakInterrupt1 )) != 0) {
568 out8 (UART0_BASE + UART_LSR,
569 asyncLSRFramingError1 |
570 asyncLSROverrunError1 |
571 asyncLSRParityError1 |
572 asyncLSRBreakInterrupt1);
578 #if CONFIG_SERIAL_SOFTWARE_FIFO
580 void serial_isr (void *arg)
584 const int rx_get = buf_info.rx_get;
585 int rx_put = buf_info.rx_put;
587 if (rx_get <= rx_put) {
588 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
590 space = rx_get - rx_put;
592 while (serial_tstc ()) {
595 buf_info.rx_buffer[rx_put++] = c;
598 if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO)
600 if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
601 /* Stop flow by setting RTS inactive */
602 out8 (UART0_BASE + UART_MCR,
603 in8 (UART0_BASE + UART_MCR) & (0xFF ^ 0x02));
606 buf_info.rx_put = rx_put;
609 void serial_buffered_init (void)
611 serial_puts ("Switching to interrupt driven serial input mode.\n");
612 buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
616 if (in8 (UART0_BASE + UART_MSR) & 0x10) {
617 serial_puts ("Check CTS signal present on serial port: OK.\n");
619 serial_puts ("WARNING: CTS signal not present on serial port.\n");
622 irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
623 serial_isr /*interrupt_handler_t *handler */ ,
624 (void *) &buf_info /*void *arg */ );
626 /* Enable "RX Data Available" Interrupt on UART */
627 /* out8(UART0_BASE + UART_IER, in8(UART0_BASE + UART_IER) |0x01); */
628 out8 (UART0_BASE + UART_IER, 0x01);
630 out8 (UART0_BASE + UART_MCR, in8 (UART0_BASE + UART_MCR) | 0x01);
631 /* Start flow by setting RTS active */
632 out8 (UART0_BASE + UART_MCR, in8 (UART0_BASE + UART_MCR) | 0x02);
633 /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
634 out8 (UART0_BASE + UART_FCR, (1 << 6) | 1);
637 void serial_buffered_putc (const char c)
640 #if defined(CONFIG_HW_WATCHDOG)
641 while (!(in8 (UART0_BASE + UART_MSR) & 0x10))
644 while (!(in8 (UART0_BASE + UART_MSR) & 0x10));
649 void serial_buffered_puts (const char *s)
654 int serial_buffered_getc (void)
658 int rx_get = buf_info.rx_get;
661 #if defined(CONFIG_HW_WATCHDOG)
662 while (rx_get == buf_info.rx_put)
665 while (rx_get == buf_info.rx_put);
667 c = buf_info.rx_buffer[rx_get++];
668 if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO)
670 buf_info.rx_get = rx_get;
672 rx_put = buf_info.rx_put;
673 if (rx_get <= rx_put) {
674 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
676 space = rx_get - rx_put;
678 if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
679 /* Start flow by setting RTS active */
680 out8 (UART0_BASE + UART_MCR, in8 (UART0_BASE + UART_MCR) | 0x02);
686 int serial_buffered_tstc (void)
688 return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
691 #endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
694 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
696 AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
698 - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
699 configuration has been already done
700 - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
701 configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
703 #if (CONFIG_KGDB_SER_INDEX & 2)
704 void kgdb_serial_init (void)
706 DECLARE_GLOBAL_DATA_PTR;
709 unsigned short br_reg;
712 br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
715 * Init onboard 16550 UART
717 out8 (UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
718 out8 (UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
719 out8 (UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
720 out8 (UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
721 out8 (UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
722 out8 (UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
723 val = in8 (UART1_BASE + UART_LSR); /* clear line status */
724 val = in8 (UART1_BASE + UART_RBR); /* read receive buffer */
725 out8 (UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
726 out8 (UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
730 void putDebugChar (const char c)
735 out8 (UART1_BASE + UART_THR, c); /* put character out */
737 /* check THRE bit, wait for transfer done */
738 while ((in8 (UART1_BASE + UART_LSR) & 0x20) != 0x20);
742 void putDebugStr (const char *s)
750 int getDebugChar (void)
752 unsigned char status = 0;
755 status = in8 (UART1_BASE + UART_LSR);
756 if ((status & asyncLSRDataReady1) != 0x0) {
759 if ((status & ( asyncLSRFramingError1 |
760 asyncLSROverrunError1 |
761 asyncLSRParityError1 |
762 asyncLSRBreakInterrupt1 )) != 0) {
763 out8 (UART1_BASE + UART_LSR,
764 asyncLSRFramingError1 |
765 asyncLSROverrunError1 |
766 asyncLSRParityError1 |
767 asyncLSRBreakInterrupt1);
770 return (0x000000ff & (int) in8 (UART1_BASE));
774 void kgdb_interruptible (int yes)
779 #else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
781 void kgdb_serial_init (void)
783 serial_printf ("[on serial] ");
786 void putDebugChar (int c)
791 void putDebugStr (const char *str)
796 int getDebugChar (void)
798 return serial_getc ();
801 void kgdb_interruptible (int yes)
805 #endif /* (CONFIG_KGDB_SER_INDEX & 2) */
806 #endif /* CFG_CMD_KGDB */
808 #endif /* CONFIG_405GP || CONFIG_405CR */