3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * (C) Copyright 2002-2004
6 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/processor.h>
32 #ifdef CONFIG_SDRAM_BANK0
35 #define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
43 typedef struct sdram_conf_s sdram_conf_t;
45 #ifndef CFG_SDRAM_TABLE
46 sdram_conf_t mb0cf[] = {
47 {(128 << 20), 0x000A4001}, /* (0-128MB) Address Mode 3, 13x10(4) */
48 {(64 << 20), 0x00084001}, /* (0-64MB) Address Mode 3, 13x9(4) */
49 {(32 << 20), 0x00062001}, /* (0-32MB) Address Mode 2, 12x9(4) */
50 {(16 << 20), 0x00046001}, /* (0-16MB) Address Mode 4, 12x8(4) */
51 {(4 << 20), 0x00008001}, /* (0-4MB) Address Mode 5, 11x8(2) */
54 sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
57 #define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
63 * Autodetect onboard SDRAM on 405 platforms
72 * Support for 100MHz and 133MHz SDRAM
74 if (get_bus_freq(0) > 100000000) {
82 * default: 100 MHz SDRAM
88 for (i=0; i<N_MB0CF; i++) {
90 * Disable memory controller.
92 mtsdram0(mem_mcopt1, 0x00000000);
95 * Set MB0CF for bank 0.
97 mtsdram0(mem_mb0cf, mb0cf[i].reg);
98 mtsdram0(mem_sdtr1, sdtr1);
99 mtsdram0(mem_rtr, rtr);
104 * Set memory controller options reg, MCOPT1.
105 * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
108 mtsdram0(mem_mcopt1, 0x80800000);
112 if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
114 * OK, size detected -> all done
121 #else /* CONFIG_440 */
124 * Autodetect onboard DDR SDRAM on 440 platforms
126 * NOTE: Some of the hardcoded values are hardware dependant,
127 * so this should be extended for other future boards
128 * using this routine!
130 long int initdram(int board_type)
134 for (i=0; i<N_MB0CF; i++) {
136 * Disable memory controller.
138 mtsdram(mem_cfg0, 0x00000000);
143 mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
144 mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
145 mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
146 mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
147 mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
150 * Following for CAS Latency = 2.5 @ 133 MHz PLB
152 mtsdram(mem_b0cr, mb0cf[i].reg);
153 mtsdram(mem_tr0, 0x41094012);
154 mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
155 mtsdram(mem_rtr, 0x7e000000); /* Interval 15.20µs @ 133MHz PLB*/
156 mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
157 udelay(400); /* Delay 200 usecs (min) */
160 * Enable the controller, then wait for DCEN to complete
162 mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
165 if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
167 * OK, size detected -> all done
169 return mb0cf[i].size;
173 return 0; /* nothing found ! */
176 #endif /* CONFIG_440 */
178 #endif /* CONFIG_SDRAM_BANK0 */