2 * (C) Copyright 2005-2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
6 * DAVE Srl <www.dave-tech.it>
8 * (C) Copyright 2002-2004
9 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm/processor.h>
36 #ifdef CONFIG_SDRAM_BANK0
40 #ifndef CONFIG_SYS_SDRAM_TABLE
41 sdram_conf_t mb0cf[] = {
42 {(128 << 20), 13, 0x000A4001}, /* (0-128MB) Address Mode 3, 13x10(4) */
43 {(64 << 20), 13, 0x00084001}, /* (0-64MB) Address Mode 3, 13x9(4) */
44 {(32 << 20), 12, 0x00062001}, /* (0-32MB) Address Mode 2, 12x9(4) */
45 {(16 << 20), 12, 0x00046001}, /* (0-16MB) Address Mode 4, 12x8(4) */
46 {(4 << 20), 11, 0x00008001}, /* (0-4MB) Address Mode 5, 11x8(2) */
49 sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
52 #define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
54 #ifdef CONFIG_SYS_SDRAM_CASL
55 static ulong ns2clks(ulong ns)
57 ulong bus_period_x_10 = ONE_BILLION / (get_bus_freq(0) / 10);
59 return ((ns * 10) + bus_period_x_10) / bus_period_x_10;
61 #endif /* CONFIG_SYS_SDRAM_CASL */
63 static ulong compute_sdtr1(ulong speed)
65 #ifdef CONFIG_SYS_SDRAM_CASL
70 if (CONFIG_SYS_SDRAM_CASL < 2)
71 sdtr1 |= (1 << SDRAM0_TR_CASL);
73 if (CONFIG_SYS_SDRAM_CASL > 4)
74 sdtr1 |= (3 << SDRAM0_TR_CASL);
76 sdtr1 |= ((CONFIG_SYS_SDRAM_CASL-1) << SDRAM0_TR_CASL);
79 tmp = ns2clks(CONFIG_SYS_SDRAM_PTA);
80 if ((tmp >= 2) && (tmp <= 4))
81 sdtr1 |= ((tmp-1) << SDRAM0_TR_PTA);
83 sdtr1 |= ((4-1) << SDRAM0_TR_PTA);
86 tmp = ns2clks(CONFIG_SYS_SDRAM_CTP);
87 if ((tmp >= 2) && (tmp <= 4))
88 sdtr1 |= ((tmp-1) << SDRAM0_TR_CTP);
90 sdtr1 |= ((4-1) << SDRAM0_TR_CTP);
93 tmp = ns2clks(CONFIG_SYS_SDRAM_LDF);
94 if ((tmp >= 2) && (tmp <= 4))
95 sdtr1 |= ((tmp-1) << SDRAM0_TR_LDF);
97 sdtr1 |= ((2-1) << SDRAM0_TR_LDF);
100 tmp = ns2clks(CONFIG_SYS_SDRAM_RFTA);
101 if ((tmp >= 4) && (tmp <= 10))
102 sdtr1 |= ((tmp-4) << SDRAM0_TR_RFTA);
104 sdtr1 |= ((10-4) << SDRAM0_TR_RFTA);
107 tmp = ns2clks(CONFIG_SYS_SDRAM_RCD);
108 if ((tmp >= 2) && (tmp <= 4))
109 sdtr1 |= ((tmp-1) << SDRAM0_TR_RCD);
111 sdtr1 |= ((4-1) << SDRAM0_TR_RCD);
114 #else /* CONFIG_SYS_SDRAM_CASL */
116 * If no values are configured in the board config file
117 * use the default values, which seem to be ok for most
121 * For new board ports we strongly recommend to define the
122 * correct values for the used SDRAM chips in your board
123 * config file (see PPChameleonEVB.h)
125 if (speed > 100000000) {
132 * default: 100 MHz SDRAM
136 #endif /* CONFIG_SYS_SDRAM_CASL */
139 /* refresh is expressed in ms */
140 static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
142 #ifdef CONFIG_SYS_SDRAM_CASL
145 tmp = ((refresh*1000*1000) / (1 << rows)) * (speed / 1000);
148 return ((tmp & 0x00003FF8) << 16);
149 #else /* CONFIG_SYS_SDRAM_CASL */
150 if (speed > 100000000) {
157 * default: 100 MHz SDRAM
161 #endif /* CONFIG_SYS_SDRAM_CASL */
165 * Autodetect onboard SDRAM on 405 platforms
167 phys_size_t initdram(int board_type)
174 * Determine SDRAM speed
176 speed = get_bus_freq(0); /* parameter not used on ppc4xx */
179 * sdtr1 (register SDRAM0_TR) must take into account timings listed
180 * in SDRAM chip datasheet. rtr (register SDRAM0_RTR) must take into
181 * account actual SDRAM size. So we can set up sdtr1 according to what
182 * is specified in board configuration file while rtr dependds on SDRAM
183 * size we are assuming before detection.
185 sdtr1 = compute_sdtr1(speed);
187 for (i=0; i<N_MB0CF; i++) {
189 * Disable memory controller.
191 mtsdram(mem_mcopt1, 0x00000000);
194 * Set MB0CF for bank 0.
196 mtsdram(mem_mb0cf, mb0cf[i].reg);
197 mtsdram(mem_sdtr1, sdtr1);
198 mtsdram(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64));
203 * Set memory controller options reg, MCOPT1.
204 * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
207 mtsdram(mem_mcopt1, 0x80800000);
211 if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
212 phys_size_t size = mb0cf[i].size;
215 * OK, size detected. Enable second bank if
216 * defined (assumes same type as bank 0)
218 #ifdef CONFIG_SDRAM_BANK1
219 mtsdram(mem_mcopt1, 0x00000000);
220 mtsdram(mem_mb1cf, mb0cf[i].size | mb0cf[i].reg);
221 mtsdram(mem_mcopt1, 0x80800000);
225 * Check if 2nd bank is really available.
226 * If the size not equal to the size of the first
227 * bank, then disable the 2nd bank completely.
229 if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) !=
231 mtsdram(mem_mb1cf, 0);
232 mtsdram(mem_mcopt1, 0);
235 * We have two identical banks, so the size
236 * is twice the bank size
243 * OK, size detected -> all done
252 #else /* CONFIG_440 */
255 * Define some default values. Those can be overwritten in the
259 #ifndef CONFIG_SYS_SDRAM_TABLE
260 sdram_conf_t mb0cf[] = {
261 {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4) */
262 {(64 << 20), 12, 0x00082001} /* 64MB mode 2, 12x9(4) */
265 sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
268 #ifndef CONFIG_SYS_SDRAM0_TR0
269 #define CONFIG_SYS_SDRAM0_TR0 0x41094012
272 #define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
277 static void sdram_tr1_set(int ram_address, int* tr1_value)
281 volatile unsigned int* ram_pointer = (unsigned int *)ram_address;
282 int first_good = -1, last_bad = 0x1ff;
284 unsigned long test[NUM_TRIES] = {
285 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
286 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
287 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
288 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
289 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
290 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
291 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
292 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
293 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
294 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
295 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
296 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
297 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
298 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
299 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
300 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
302 /* go through all possible SDRAM0_TR1[RDCT] values */
303 for (i=0; i<=0x1ff; i++) {
304 /* set the current value for TR1 */
305 mtsdram(mem_tr1, (0x80800800 | i));
308 for (j=0; j<NUM_TRIES; j++) {
309 ram_pointer[j] = test[j];
311 /* clear any cache at ram location */
312 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
315 /* read values back */
316 for (j=0; j<NUM_TRIES; j++) {
317 for (k=0; k<NUM_READS; k++) {
318 /* clear any cache at ram location */
319 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
321 if (ram_pointer[j] != test[j])
330 /* we have a SDRAM0_TR1[RDCT] that is part of the window */
331 if (j == NUM_TRIES) {
332 if (first_good == -1)
333 first_good = i; /* found beginning of window */
334 } else { /* bad read */
335 /* if we have not had a good read then don't care */
336 if (first_good != -1) {
337 /* first failure after a good read */
344 /* return the current value for TR1 */
345 *tr1_value = (first_good + last_bad) / 2;
349 * Autodetect onboard DDR SDRAM on 440 platforms
351 * NOTE: Some of the hardcoded values are hardware dependant,
352 * so this should be extended for other future boards
353 * using this routine!
355 phys_size_t initdram(int board_type)
360 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
361 defined(CONFIG_440GR) || defined(CONFIG_440SP)
363 * Soft-reset SDRAM controller.
365 mtsdr(sdr_srst, SDR0_SRST_DMC);
366 mtsdr(sdr_srst, 0x00000000);
369 for (i=0; i<N_MB0CF; i++) {
371 * Disable memory controller.
373 mtsdram(mem_cfg0, 0x00000000);
378 mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
379 mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
380 mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
381 mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
382 mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
385 * Following for CAS Latency = 2.5 @ 133 MHz PLB
387 mtsdram(mem_b0cr, mb0cf[i].reg);
388 mtsdram(mem_tr0, CONFIG_SYS_SDRAM0_TR0);
389 mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
390 mtsdram(mem_rtr, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */
391 mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
392 udelay(400); /* Delay 200 usecs (min) */
395 * Enable the controller, then wait for DCEN to complete
397 mtsdram(mem_cfg0, 0x82000000); /* DCEN=1, PMUD=0, 64-bit */
400 if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
402 * Optimize TR1 to current hardware environment
404 sdram_tr1_set(0x00000000, &tr1_bank1);
405 mtsdram(mem_tr1, (tr1_bank1 | 0x80800800));
407 #ifdef CONFIG_SDRAM_ECC
408 ecc_init(0, mb0cf[i].size);
412 * OK, size detected -> all done
414 return mb0cf[i].size;
418 return 0; /* nothing found ! */
421 #endif /* CONFIG_440 */
423 #endif /* CONFIG_SDRAM_BANK0 */