3 * Platform independend driver for NDFC (NanD Flash Controller)
4 * integrated into EP440 cores
6 * (C) Copyright 2006-2007
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * Based on original work by
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY) && \
35 (defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
36 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
37 defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \
38 defined(CONFIG_460EX) || defined(CONFIG_460GT))
41 #include <linux/mtd/ndfc.h>
42 #include <linux/mtd/nand_ecc.h>
43 #include <asm/processor.h>
49 static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
51 struct nand_chip *this = mtd->priv;
53 if (ctrl & NAND_CTRL_CHANGE) {
54 if ( ctrl & NAND_CLE )
58 if ( ctrl & NAND_ALE )
63 if (cmd != NAND_CMD_NONE)
64 writeb(cmd, this->IO_ADDR_W);
67 static u_char ndfc_read_byte(struct mtd_info *mtdinfo)
69 struct nand_chip *this = mtdinfo->priv;
70 ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
72 return (in_8((u8 *)(base + NDFC_DATA)));
75 static int ndfc_dev_ready(struct mtd_info *mtdinfo)
77 struct nand_chip *this = mtdinfo->priv;
78 ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
80 while (!(in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY))
86 static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode)
88 struct nand_chip *this = mtdinfo->priv;
89 ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
92 ccr = in_be32((u32 *)(base + NDFC_CCR));
93 ccr |= NDFC_CCR_RESET_ECC;
94 out_be32((u32 *)(base + NDFC_CCR), ccr);
97 static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
98 const u_char *dat, u_char *ecc_code)
100 struct nand_chip *this = mtdinfo->priv;
101 ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
105 ecc = in_be32((u32 *)(base + NDFC_ECC));
107 /* The NDFC uses Smart Media (SMC) bytes order
117 * Speedups for buffer read/write/verify
119 * NDFC allows 32bit read/write of data. So we can speed up the buffer
120 * functions. No further checking, as nand_base will always read/write
123 static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
125 struct nand_chip *this = mtdinfo->priv;
126 ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
127 uint32_t *p = (uint32_t *) buf;
129 for (;len > 0; len -= 4)
130 *p++ = in_be32((u32 *)(base + NDFC_DATA));
133 #ifndef CONFIG_NAND_SPL
135 * Don't use these speedup functions in NAND boot image, since the image
136 * has to fit into 4kByte.
138 static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
140 struct nand_chip *this = mtdinfo->priv;
141 ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
142 uint32_t *p = (uint32_t *) buf;
144 for (; len > 0; len -= 4)
145 out_be32((u32 *)(base + NDFC_DATA), *p++);
148 static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
150 struct nand_chip *this = mtdinfo->priv;
151 ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
152 uint32_t *p = (uint32_t *) buf;
154 for (; len > 0; len -= 4)
155 if (*p++ != in_be32((u32 *)(base + NDFC_DATA)))
160 #endif /* #ifndef CONFIG_NAND_SPL */
162 void board_nand_select_device(struct nand_chip *nand, int chip)
165 * Don't use "chip" to address the NAND device,
166 * generate the cs from the address where it is encoded.
168 int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
169 ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
171 /* Set NandFlash Core Configuration Register */
173 out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24));
176 int board_nand_init(struct nand_chip *nand)
178 int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
179 ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
181 nand->cmd_ctrl = ndfc_hwcontrol;
182 nand->read_byte = ndfc_read_byte;
183 nand->read_buf = ndfc_read_buf;
184 nand->dev_ready = ndfc_dev_ready;
186 nand->ecc.correct = nand_correct_data;
187 nand->ecc.hwctl = ndfc_enable_hwecc;
188 nand->ecc.calculate = ndfc_calculate_ecc;
189 nand->ecc.mode = NAND_ECC_HW;
190 nand->ecc.size = 256;
193 #ifndef CONFIG_NAND_SPL
194 nand->write_buf = ndfc_write_buf;
195 nand->verify_buf = ndfc_verify_buf;
198 * Setup EBC (CS0 only right now)
200 mtebc(EBC0_CFG, 0xb8400000);
202 mtebc(pb0cr, CFG_EBC_PB0CR);
203 mtebc(pb0ap, CFG_EBC_PB0AP);
207 * Select required NAND chip in NDFC
209 board_nand_select_device(nand, cs);
210 out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), 0x80002222);