3 * Platform independend driver for NDFC (NanD Flash Controller)
4 * integrated into EP440 cores
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * Based on original work by
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
37 #include <linux/mtd/ndfc.h>
38 #include <asm/processor.h>
43 static void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
64 static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte)
66 struct nand_chip *this = mtdinfo->priv;
67 ulong base = (ulong) this->IO_ADDR_W;
70 out8(base + NDFC_CMD, byte);
72 out8(base + NDFC_ALE, byte);
74 out8(base + NDFC_DATA, byte);
77 static u_char ndfc_read_byte(struct mtd_info *mtdinfo)
79 struct nand_chip *this = mtdinfo->priv;
80 ulong base = (ulong) this->IO_ADDR_W;
82 return (in8(base + NDFC_DATA));
85 static int ndfc_dev_ready(struct mtd_info *mtdinfo)
87 struct nand_chip *this = mtdinfo->priv;
88 ulong base = (ulong) this->IO_ADDR_W;
90 while (!(in32(base + NDFC_STAT) & NDFC_STAT_IS_READY))
96 #ifndef CONFIG_NAND_SPL
98 * Don't use these speedup functions in NAND boot image, since the image
99 * has to fit into 4kByte.
103 * Speedups for buffer read/write/verify
105 * NDFC allows 32bit read/write of data. So we can speed up the buffer
106 * functions. No further checking, as nand_base will always read/write
109 static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
111 struct nand_chip *this = mtdinfo->priv;
112 ulong base = (ulong) this->IO_ADDR_W;
113 uint32_t *p = (uint32_t *) buf;
115 for(;len > 0; len -= 4)
116 *p++ = in32(base + NDFC_DATA);
119 static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
121 struct nand_chip *this = mtdinfo->priv;
122 ulong base = (ulong) this->IO_ADDR_W;
123 uint32_t *p = (uint32_t *) buf;
125 for(; len > 0; len -= 4)
126 out32(base + NDFC_DATA, *p++);
129 static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
131 struct nand_chip *this = mtdinfo->priv;
132 ulong base = (ulong) this->IO_ADDR_W;
133 uint32_t *p = (uint32_t *) buf;
135 for(; len > 0; len -= 4)
136 if (*p++ != in32(base + NDFC_DATA))
141 #endif /* #ifndef CONFIG_NAND_SPL */
143 void board_nand_init(struct nand_chip *nand)
145 nand->eccmode = NAND_ECC_SOFT;
147 nand->hwcontrol = ndfc_hwcontrol;
148 nand->read_byte = ndfc_read_byte;
149 nand->write_byte = ndfc_write_byte;
150 nand->dev_ready = ndfc_dev_ready;
152 #ifndef CONFIG_NAND_SPL
153 nand->write_buf = ndfc_write_buf;
154 nand->read_buf = ndfc_read_buf;
155 nand->verify_buf = ndfc_verify_buf;
158 * Setup EBC (CS0 only right now)
160 mtdcr(ebccfga, xbcfg);
161 mtdcr(ebccfgd, 0xb8400000);
163 mtebc(pb0cr, CFG_EBC_PB0CR);
164 mtebc(pb0ap, CFG_EBC_PB0AP);
167 /* Set NandFlash Core Configuration Register */
168 /* Chip select 3, 1col x 2 rows */
169 out32(CFG_NAND_BASE + NDFC_CCR, 0x00000000 | (CFG_NAND_CS << 24));
170 out32(CFG_NAND_BASE + NDFC_BCFG0 + (CFG_NAND_CS << 2), 0x80002222);