3 * Platform independend driver for NDFC (NanD Flash Controller)
4 * integrated into EP440 cores
6 * (C) Copyright 2006-2007
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * Based on original work by
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY) && \
35 (defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
36 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
37 defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \
38 defined(CONFIG_460EX) || defined(CONFIG_460GT))
41 #include <linux/mtd/ndfc.h>
42 #include <linux/mtd/nand_ecc.h>
43 #include <asm/processor.h>
49 static void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
70 static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte)
72 struct nand_chip *this = mtdinfo->priv;
73 ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
76 out_8((u8 *)(base + NDFC_CMD), byte);
78 out_8((u8 *)(base + NDFC_ALE), byte);
80 out_8((u8 *)(base + NDFC_DATA), byte);
83 static u_char ndfc_read_byte(struct mtd_info *mtdinfo)
85 struct nand_chip *this = mtdinfo->priv;
86 ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
88 return (in_8((u8 *)(base + NDFC_DATA)));
91 static int ndfc_dev_ready(struct mtd_info *mtdinfo)
93 struct nand_chip *this = mtdinfo->priv;
94 ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
96 while (!(in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY))
102 static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode)
104 struct nand_chip *this = mtdinfo->priv;
105 ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
108 ccr = in_be32((u32 *)(base + NDFC_CCR));
109 ccr |= NDFC_CCR_RESET_ECC;
110 out_be32((u32 *)(base + NDFC_CCR), ccr);
113 static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
114 const u_char *dat, u_char *ecc_code)
116 struct nand_chip *this = mtdinfo->priv;
117 ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
121 ecc = in_be32((u32 *)(base + NDFC_ECC));
123 /* The NDFC uses Smart Media (SMC) bytes order
133 * Speedups for buffer read/write/verify
135 * NDFC allows 32bit read/write of data. So we can speed up the buffer
136 * functions. No further checking, as nand_base will always read/write
139 static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
141 struct nand_chip *this = mtdinfo->priv;
142 ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
143 uint32_t *p = (uint32_t *) buf;
145 for (;len > 0; len -= 4)
146 *p++ = in_be32((u32 *)(base + NDFC_DATA));
149 #ifndef CONFIG_NAND_SPL
151 * Don't use these speedup functions in NAND boot image, since the image
152 * has to fit into 4kByte.
154 static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
156 struct nand_chip *this = mtdinfo->priv;
157 ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
158 uint32_t *p = (uint32_t *) buf;
160 for (; len > 0; len -= 4)
161 out_be32((u32 *)(base + NDFC_DATA), *p++);
164 static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
166 struct nand_chip *this = mtdinfo->priv;
167 ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
168 uint32_t *p = (uint32_t *) buf;
170 for (; len > 0; len -= 4)
171 if (*p++ != in_be32((u32 *)(base + NDFC_DATA)))
176 #endif /* #ifndef CONFIG_NAND_SPL */
178 void board_nand_select_device(struct nand_chip *nand, int chip)
181 * Don't use "chip" to address the NAND device,
182 * generate the cs from the address where it is encoded.
184 int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
185 ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
187 /* Set NandFlash Core Configuration Register */
189 out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24));
192 int board_nand_init(struct nand_chip *nand)
194 int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
195 ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
197 nand->hwcontrol = ndfc_hwcontrol;
198 nand->read_byte = ndfc_read_byte;
199 nand->read_buf = ndfc_read_buf;
200 nand->write_byte = ndfc_write_byte;
201 nand->dev_ready = ndfc_dev_ready;
203 nand->eccmode = NAND_ECC_HW3_256;
204 nand->enable_hwecc = ndfc_enable_hwecc;
205 nand->calculate_ecc = ndfc_calculate_ecc;
206 nand->correct_data = nand_correct_data;
208 #ifndef CONFIG_NAND_SPL
209 nand->write_buf = ndfc_write_buf;
210 nand->verify_buf = ndfc_verify_buf;
213 * Setup EBC (CS0 only right now)
215 mtebc(EBC0_CFG, 0xb8400000);
217 mtebc(pb0cr, CFG_EBC_PB0CR);
218 mtebc(pb0ap, CFG_EBC_PB0AP);
222 * Select required NAND chip in NDFC
224 board_nand_select_device(nand, cs);
225 out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), 0x80002222);