1 /*-----------------------------------------------------------------------------+
3 | This source code has been made available to you by IBM on an AS-IS
4 | basis. Anyone receiving this source is licensed under IBM
5 | copyrights to use it in any way he or she deems fit, including
6 | copying it, modifying it, compiling it, and redistributing it either
7 | with or without modifications. No license under IBM patents or
8 | patent applications is to be implied by the copyright license.
10 | Any user of this software should understand that IBM cannot provide
11 | technical support for this software and will not be responsible for
12 | any consequences resulting from the use of this software.
14 | Any person who transfers this source code or any derivative work
15 | must include the IBM copyright notice, this paragraph, and the
16 | preceding two paragraphs in the transferred software.
18 | COPYRIGHT I B M CORPORATION 1995
19 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 +-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
25 | Function: This module has utilities for accessing the MII PHY through
32 | Date Description of Change BY
33 | --------- --------------------- ---
34 | 05-May-99 Created MKW
35 | 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to
36 | better match OPB speed. Also modified delay times. JWB
37 | 29-Jul-99 Added Full duplex support MKW
38 | 24-Aug-99 Removed printf from dp83843_duplex() JWB
39 | 19-Jul-00 Ported to esd cpci405 sr
40 | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS
41 | <travis.sawyer@sandburst.com>
43 +-----------------------------------------------------------------------------*/
46 #include <asm/processor.h>
47 #include <ppc_asm.tmpl>
49 #include <440gx_enet.h>
53 #if defined(CONFIG_440) && defined(CONFIG_NET_MULTI)
56 /***********************************************************/
57 /* Dump out to the screen PHY regs */
58 /***********************************************************/
60 void miiphy_dump (unsigned char addr)
66 for (i = 0; i < 0x1A; i++) {
67 if (miiphy_read (addr, i, &data)) {
68 printf ("read error for reg %lx\n", i);
71 printf ("Phy reg %lx ==> %4x\n", i, data);
73 /* jump to the next set of regs */
81 /***********************************************************/
82 /* (Re)start autonegotiation */
83 /***********************************************************/
84 int phy_setup_aneg (unsigned char addr)
86 unsigned short ctl, adv;
88 /* Setup standard advertise */
89 miiphy_read (addr, PHY_ANAR, &adv);
90 adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
91 PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
93 miiphy_write (addr, PHY_ANAR, adv);
95 /* Start/Restart aneg */
96 miiphy_read (addr, PHY_BMCR, &ctl);
97 ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
98 miiphy_write (addr, PHY_BMCR, ctl);
104 /***********************************************************/
105 /* read a phy reg and return the value with a rc */
106 /***********************************************************/
107 unsigned int miiphy_getemac_offset (void)
110 unsigned long eoffset;
112 /* Need to find out which mdi port we're using */
113 zmii = in32 (ZMII_FER);
115 if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) {
118 } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) {
121 } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) {
124 } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) {
128 /* None of the mdi ports are enabled! */
130 zmii |= ZMII_FER_MDI << ZMII_FER_V (0);
131 out32 (ZMII_FER, zmii);
133 /* need to soft reset port 0 */
134 zmii = in32 (EMAC_M0);
135 zmii |= EMAC_M0_SRST;
136 out32 (EMAC_M0, zmii);
144 int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
146 unsigned long sta_reg; /* STA scratch area */
148 unsigned long emac_reg;
151 emac_reg = miiphy_getemac_offset ();
152 /* see if it is ready for 1000 nsec */
155 /* see if it is ready for sec */
156 while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) {
160 printf ("read err 1\n");
166 sta_reg = reg; /* reg address */
167 /* set clock (50Mhz) and read flags */
168 #if defined(CONFIG_440GX)
169 sta_reg |= EMAC_STACR_READ;
171 sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
174 #if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
175 sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
177 sta_reg = sta_reg | (addr << 5); /* Phy address */
179 out32 (EMAC_STACR + emac_reg, sta_reg);
180 #if 0 /* test-only */
181 printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
184 sta_reg = in32 (EMAC_STACR + emac_reg);
186 while ((sta_reg & EMAC_STACR_OC) == 0) {
192 sta_reg = in32 (EMAC_STACR + emac_reg);
194 if ((sta_reg & EMAC_STACR_PHYE) != 0) {
198 *value = *(short *) (&sta_reg);
205 /***********************************************************/
206 /* write a phy reg and return the value with a rc */
207 /***********************************************************/
209 int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
211 unsigned long sta_reg; /* STA scratch area */
213 unsigned long emac_reg;
215 emac_reg = miiphy_getemac_offset ();
216 /* see if it is ready for 1000 nsec */
219 while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) {
226 sta_reg = reg; /* reg address */
227 /* set clock (50Mhz) and read flags */
228 #if defined(CONFIG_440GX)
229 sta_reg |= EMAC_STACR_WRITE;
231 sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
234 #if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
235 sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
237 sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */
238 memcpy (&sta_reg, &value, 2); /* put in data */
240 out32 (EMAC_STACR + emac_reg, sta_reg);
242 /* wait for completion */
244 sta_reg = in32 (EMAC_STACR + emac_reg);
245 while ((sta_reg & EMAC_STACR_OC) == 0) {
250 sta_reg = in32 (EMAC_STACR + emac_reg);
253 if ((sta_reg & EMAC_STACR_PHYE) != 0)
259 #endif /* CONFIG_405GP */