1 /*-----------------------------------------------------------------------------+
3 | This source code has been made available to you by IBM on an AS-IS
4 | basis. Anyone receiving this source is licensed under IBM
5 | copyrights to use it in any way he or she deems fit, including
6 | copying it, modifying it, compiling it, and redistributing it either
7 | with or without modifications. No license under IBM patents or
8 | patent applications is to be implied by the copyright license.
10 | Any user of this software should understand that IBM cannot provide
11 | technical support for this software and will not be responsible for
12 | any consequences resulting from the use of this software.
14 | Any person who transfers this source code or any derivative work
15 | must include the IBM copyright notice, this paragraph, and the
16 | preceding two paragraphs in the transferred software.
18 | COPYRIGHT I B M CORPORATION 1995
19 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 +-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
25 | Function: This module has utilities for accessing the MII PHY through
32 | Date Description of Change BY
33 | --------- --------------------- ---
34 | 05-May-99 Created MKW
35 | 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to
36 | better match OPB speed. Also modified delay times. JWB
37 | 29-Jul-99 Added Full duplex support MKW
38 | 24-Aug-99 Removed printf from dp83843_duplex() JWB
39 | 19-Jul-00 Ported to esd cpci405 sr
40 | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS
41 | <travis.sawyer@sandburst.com>
43 +-----------------------------------------------------------------------------*/
46 #include <asm/processor.h>
48 #include <ppc_asm.tmpl>
50 #include <ppc4xx_enet.h>
55 /***********************************************************/
56 /* Dump out to the screen PHY regs */
57 /***********************************************************/
59 void miiphy_dump (char *devname, unsigned char addr)
65 for (i = 0; i < 0x1A; i++) {
66 if (miiphy_read (devname, addr, i, &data)) {
67 printf ("read error for reg %lx\n", i);
70 printf ("Phy reg %lx ==> %4x\n", i, data);
72 /* jump to the next set of regs */
80 /***********************************************************/
81 /* (Re)start autonegotiation */
82 /***********************************************************/
83 int phy_setup_aneg (char *devname, unsigned char addr)
85 unsigned short ctl, adv;
87 /* Setup standard advertise */
88 miiphy_read (devname, addr, PHY_ANAR, &adv);
89 adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
90 PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
92 miiphy_write (devname, addr, PHY_ANAR, adv);
94 miiphy_read (devname, addr, PHY_1000BTCR, &adv);
96 miiphy_write (devname, addr, PHY_1000BTCR, adv);
98 /* Start/Restart aneg */
99 miiphy_read (devname, addr, PHY_BMCR, &ctl);
100 ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
101 miiphy_write (devname, addr, PHY_BMCR, ctl);
107 /***********************************************************/
108 /* read a phy reg and return the value with a rc */
109 /***********************************************************/
110 unsigned int miiphy_getemac_offset (void)
112 #if (defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)) && defined(CONFIG_NET_MULTI)
114 unsigned long eoffset;
116 /* Need to find out which mdi port we're using */
117 zmii = in_be32((void *)ZMII_FER);
119 if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) {
122 } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) {
125 } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) {
128 } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) {
132 /* None of the mdi ports are enabled! */
134 zmii |= ZMII_FER_MDI << ZMII_FER_V (0);
135 out_be32((void *)ZMII_FER, zmii);
137 /* need to soft reset port 0 */
138 zmii = in_be32((void *)EMAC_M0);
139 zmii |= EMAC_M0_SRST;
140 out_be32((void *)EMAC_M0, zmii);
146 #if defined(CONFIG_NET_MULTI) && defined(CONFIG_405EX)
150 rgmii = in_be32((void *)RGMII_FER);
151 if (rgmii & (1 << (19 - devnum)))
160 int emac4xx_miiphy_read (char *devname, unsigned char addr,
161 unsigned char reg, unsigned short *value)
163 unsigned long sta_reg; /* STA scratch area */
165 unsigned long emac_reg;
168 emac_reg = miiphy_getemac_offset ();
169 /* see if it is ready for 1000 nsec */
172 /* see if it is ready for sec */
173 while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
177 sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
178 printf ("read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
179 printf ("read err 1\n");
185 sta_reg = reg; /* reg address */
186 /* set clock (50Mhz) and read flags */
187 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
188 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
189 defined(CONFIG_405EX)
190 #if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
191 sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ;
193 sta_reg |= EMAC_STACR_READ;
196 sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
199 #if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \
200 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
201 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
202 !defined(CONFIG_405EX)
203 sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
205 sta_reg = sta_reg | (addr << 5); /* Phy address */
206 sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */
207 out_be32((void *)EMAC_STACR + emac_reg, sta_reg);
209 printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
212 sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
214 printf ("a21: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
217 while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
223 sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
225 printf ("a22: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
228 if ((sta_reg & EMAC_STACR_PHYE) != 0) {
232 *value = *(short *) (&sta_reg);
239 /***********************************************************/
240 /* write a phy reg and return the value with a rc */
241 /***********************************************************/
243 int emac4xx_miiphy_write (char *devname, unsigned char addr,
244 unsigned char reg, unsigned short value)
246 unsigned long sta_reg; /* STA scratch area */
248 unsigned long emac_reg;
250 emac_reg = miiphy_getemac_offset ();
251 /* see if it is ready for 1000 nsec */
254 while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
261 sta_reg = reg; /* reg address */
262 /* set clock (50Mhz) and read flags */
263 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
264 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
265 defined(CONFIG_405EX)
266 #if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
267 sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE;
269 sta_reg |= EMAC_STACR_WRITE;
272 sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
275 #if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \
276 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
277 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
278 !defined(CONFIG_405EX)
279 sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
281 sta_reg = sta_reg | ((unsigned long) addr << 5);/* Phy address */
282 sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */
283 memcpy (&sta_reg, &value, 2); /* put in data */
285 out_be32((void *)EMAC_STACR + emac_reg, sta_reg);
287 /* wait for completion */
289 sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
291 printf ("a31: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
293 while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
298 sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
300 printf ("a32: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
304 if ((sta_reg & EMAC_STACR_PHYE) != 0)