1 /*-----------------------------------------------------------------------------+
3 | This source code has been made available to you by IBM on an AS-IS
4 | basis. Anyone receiving this source is licensed under IBM
5 | copyrights to use it in any way he or she deems fit, including
6 | copying it, modifying it, compiling it, and redistributing it either
7 | with or without modifications. No license under IBM patents or
8 | patent applications is to be implied by the copyright license.
10 | Any user of this software should understand that IBM cannot provide
11 | technical support for this software and will not be responsible for
12 | any consequences resulting from the use of this software.
14 | Any person who transfers this source code or any derivative work
15 | must include the IBM copyright notice, this paragraph, and the
16 | preceding two paragraphs in the transferred software.
18 | COPYRIGHT I B M CORPORATION 1995
19 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 +-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
25 | Function: This module has utilities for accessing the MII PHY through
30 +-----------------------------------------------------------------------------*/
32 /* define DEBUG for debugging output (obviously ;-)) */
38 #include <asm/processor.h>
40 #include <ppc_asm.tmpl>
42 #include <ppc4xx_enet.h>
46 #if !defined(CONFIG_PHY_CLK_FREQ)
47 #define CONFIG_PHY_CLK_FREQ 0
50 /***********************************************************/
51 /* Dump out to the screen PHY regs */
52 /***********************************************************/
54 void miiphy_dump (char *devname, unsigned char addr)
59 for (i = 0; i < 0x1A; i++) {
60 if (miiphy_read (devname, addr, i, &data)) {
61 printf ("read error for reg %lx\n", i);
64 printf ("Phy reg %lx ==> %4x\n", i, data);
66 /* jump to the next set of regs */
73 /***********************************************************/
74 /* (Re)start autonegotiation */
75 /***********************************************************/
76 int phy_setup_aneg (char *devname, unsigned char addr)
80 #if defined(CONFIG_PHY_DYNAMIC_ANEG)
82 * Set up advertisement based on capablilities reported by the PHY.
83 * This should work for both copper and fiber.
86 #if defined(CONFIG_PHY_GIGE)
90 miiphy_read (devname, addr, PHY_BMSR, &bmsr);
92 #if defined(CONFIG_PHY_GIGE)
93 if (bmsr & PHY_BMSR_EXT_STAT)
94 miiphy_read (devname, addr, PHY_EXSR, &exsr);
96 if (exsr & (PHY_EXSR_1000XF | PHY_EXSR_1000XH)) {
100 if (exsr & PHY_EXSR_1000XF)
101 anar |= PHY_X_ANLPAR_FD;
103 if (exsr & PHY_EXSR_1000XH)
104 anar |= PHY_X_ANLPAR_HD;
106 miiphy_write (devname, addr, PHY_ANAR, anar);
112 miiphy_read (devname, addr, PHY_ANAR, &anar);
113 anar &= ~(0x5000 | PHY_ANLPAR_T4 | PHY_ANLPAR_TXFD |
114 PHY_ANLPAR_TX | PHY_ANLPAR_10FD | PHY_ANLPAR_10);
116 miiphy_read (devname, addr, PHY_1000BTCR, &btcr);
117 btcr &= ~(0x00FF | PHY_1000BTCR_1000FD | PHY_1000BTCR_1000HD);
119 if (bmsr & PHY_BMSR_100T4)
120 anar |= PHY_ANLPAR_T4;
122 if (bmsr & PHY_BMSR_100TXF)
123 anar |= PHY_ANLPAR_TXFD;
125 if (bmsr & PHY_BMSR_100TXH)
126 anar |= PHY_ANLPAR_TX;
128 if (bmsr & PHY_BMSR_10TF)
129 anar |= PHY_ANLPAR_10FD;
131 if (bmsr & PHY_BMSR_10TH)
132 anar |= PHY_ANLPAR_10;
134 miiphy_write (devname, addr, PHY_ANAR, anar);
136 #if defined(CONFIG_PHY_GIGE)
137 if (exsr & PHY_EXSR_1000TF)
138 btcr |= PHY_1000BTCR_1000FD;
140 if (exsr & PHY_EXSR_1000TH)
141 btcr |= PHY_1000BTCR_1000HD;
143 miiphy_write (devname, addr, PHY_1000BTCR, btcr);
147 #else /* defined(CONFIG_PHY_DYNAMIC_ANEG) */
149 * Set up standard advertisement
153 miiphy_read (devname, addr, PHY_ANAR, &adv);
154 adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_TXFD | PHY_ANLPAR_TX |
155 PHY_ANLPAR_10FD | PHY_ANLPAR_10);
156 miiphy_write (devname, addr, PHY_ANAR, adv);
158 miiphy_read (devname, addr, PHY_1000BTCR, &adv);
160 miiphy_write (devname, addr, PHY_1000BTCR, adv);
162 #endif /* defined(CONFIG_PHY_DYNAMIC_ANEG) */
164 /* Start/Restart aneg */
165 miiphy_read (devname, addr, PHY_BMCR, &bmcr);
166 bmcr |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
167 miiphy_write (devname, addr, PHY_BMCR, bmcr);
172 /***********************************************************/
173 /* read a phy reg and return the value with a rc */
174 /***********************************************************/
176 * Find out of the choice for the emac for MDIO is from the bridges,
177 * i.e. ZMII or RGMII as approporiate. If the bridges are not used
178 * to determine the emac for MDIO, then is the SDR0_ETH_CFG[MDIO_SEL]
179 * used? If so, then this routine below does not apply to the 460EX/GT.
181 * sr: Currently on 460EX only EMAC0 works with MDIO, so we always
182 * return EMAC0 offset here
184 unsigned int miiphy_getemac_offset (void)
186 #if (defined(CONFIG_440) && \
187 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
188 !defined(CONFIG_460EX) && !defined(CONFIG_460GT)) && \
189 defined(CONFIG_NET_MULTI)
191 unsigned long eoffset;
193 /* Need to find out which mdi port we're using */
194 zmii = in_be32((void *)ZMII_FER);
196 if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0)))
200 else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1)))
204 else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2)))
208 else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3)))
213 /* None of the mdi ports are enabled! */
215 zmii |= ZMII_FER_MDI << ZMII_FER_V (0);
216 out_be32((void *)ZMII_FER, zmii);
218 /* need to soft reset port 0 */
219 zmii = in_be32((void *)EMAC_M0);
220 zmii |= EMAC_M0_SRST;
221 out_be32((void *)EMAC_M0, zmii);
227 #if defined(CONFIG_NET_MULTI) && defined(CONFIG_405EX)
231 rgmii = in_be32((void *)RGMII_FER);
232 if (rgmii & (1 << (19 - devnum)))
240 static int emac_miiphy_wait(u32 emac_reg)
245 /* wait for completion */
248 sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
250 debug("%s [%d]: Timeout! EMAC_STACR=0x%0x\n", __func__,
255 } while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK);
260 static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value)
265 emac_reg = miiphy_getemac_offset();
267 /* wait for completion */
268 if (emac_miiphy_wait(emac_reg) != 0)
271 sta_reg = reg; /* reg address */
273 /* set clock (50Mhz) and read flags */
274 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
275 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
276 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
277 defined(CONFIG_405EX)
278 #if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
279 sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | cmd;
284 sta_reg = (sta_reg | cmd) & ~EMAC_STACR_CLK_100MHZ;
287 /* Some boards (mainly 405EP based) define the PHY clock freqency fixed */
288 sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
289 sta_reg = sta_reg | ((u32)addr << 5); /* Phy address */
290 sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */
291 if (cmd == EMAC_STACR_WRITE)
292 memcpy(&sta_reg, &value, 2); /* put in data */
294 out_be32((void *)EMAC_STACR + emac_reg, sta_reg);
295 debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg);
297 /* wait for completion */
298 if (emac_miiphy_wait(emac_reg) != 0)
301 debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg);
302 if ((sta_reg & EMAC_STACR_PHYE) != 0)
308 int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg,
309 unsigned short *value)
311 unsigned long sta_reg;
312 unsigned long emac_reg;
314 emac_reg = miiphy_getemac_offset ();
316 if (emac_miiphy_command(addr, reg, EMAC_STACR_READ, 0) != 0)
319 sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
320 *value = *(u16 *)(&sta_reg);
325 /***********************************************************/
326 /* write a phy reg and return the value with a rc */
327 /***********************************************************/
329 int emac4xx_miiphy_write (char *devname, unsigned char addr, unsigned char reg,
330 unsigned short value)
332 return emac_miiphy_command(addr, reg, EMAC_STACR_WRITE, value);