2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2002 (440 port)
6 * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
8 * (C) Copyright 2003 (440GX port)
9 * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/processor.h>
35 #include <ppc_asm.tmpl>
39 #define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
40 UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI) | \
41 UIC_MASK(VECNUM_UIC3CI) | UIC_MASK(VECNUM_UIC3NCI))
43 #define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
44 UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI))
46 #define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI))
51 DECLARE_GLOBAL_DATA_PTR;
54 * CPM interrupt vector functions.
57 interrupt_handler_t *handler;
62 static struct irq_action irq_vecs[UIC_MAX * 32];
65 void set_dcr(u16, u32);
67 #if defined(CONFIG_440)
69 /* SPRN changed in 440 */
70 static __inline__ void set_evpr(unsigned long val)
72 asm volatile("mtspr 0x03f,%0" : : "r" (val));
75 #else /* !defined(CONFIG_440) */
77 static __inline__ void set_pit(unsigned long val)
79 asm volatile("mtpit %0" : : "r" (val));
83 static __inline__ void set_tcr(unsigned long val)
85 asm volatile("mttcr %0" : : "r" (val));
89 static __inline__ void set_evpr(unsigned long val)
91 asm volatile("mtevpr %0" : : "r" (val));
93 #endif /* defined(CONFIG_440 */
95 int interrupt_init_cpu (unsigned *decrementer_count)
100 /* decrementer is automatically reloaded */
101 *decrementer_count = 0;
104 * Mark all irqs as free
106 for (vec = 0; vec < (UIC_MAX * 32); vec++) {
107 irq_vecs[vec].handler = NULL;
108 irq_vecs[vec].arg = NULL;
109 irq_vecs[vec].count = 0;
116 #if defined(CONFIG_440)
118 val &= (~0x04400000); /* clear DIS & ARE */
120 mtspr( dec, 0 ); /* Prevent exception after TSR clear*/
121 mtspr( decar, 0 ); /* clear reload */
122 mtspr( tsr, 0x08000000 ); /* clear DEC status */
123 val = gd->bd->bi_intfreq/1000; /* 1 msec */
124 mtspr( decar, val ); /* Set auto-reload value */
125 mtspr( dec, val ); /* Set inital val */
127 set_pit(gd->bd->bi_intfreq / 1000);
129 #endif /* CONFIG_4xx */
148 set_evpr(0x00000000);
151 /* Install the UIC1 handlers */
152 irq_install_handler(VECNUM_UIC1NCI, (void *)(void *)external_interrupt, 0);
153 irq_install_handler(VECNUM_UIC1CI, (void *)(void *)external_interrupt, 0);
156 irq_install_handler(VECNUM_UIC2NCI, (void *)(void *)external_interrupt, 0);
157 irq_install_handler(VECNUM_UIC2CI, (void *)(void *)external_interrupt, 0);
160 irq_install_handler(VECNUM_UIC3NCI, (void *)(void *)external_interrupt, 0);
161 irq_install_handler(VECNUM_UIC3CI, (void *)(void *)external_interrupt, 0);
167 /* Handler for UIC interrupt */
168 static void uic_interrupt(u32 uic_base, int vec_base)
175 * Read masked interrupt status register to determine interrupt source
177 uic_msr = get_dcr(uic_base + UIC_MSR);
181 while (msr_shift != 0) {
182 if (msr_shift & 0x80000000) {
184 * Increment irq counter (for debug purpose only)
186 irq_vecs[vec].count++;
188 if (irq_vecs[vec].handler != NULL) {
190 (*irq_vecs[vec].handler)(irq_vecs[vec].arg);
192 set_dcr(uic_base + UIC_ER,
193 get_dcr(uic_base + UIC_ER) & ~UIC_MASK(vec));
194 printf("Masking bogus interrupt vector %d"
195 " (UIC_BASE=0x%x)\n", vec, uic_base);
199 * After servicing the interrupt, we have to remove the
202 set_dcr(uic_base + UIC_SR, UIC_MASK(vec));
206 * Shift msr to next position and increment vector
214 * Handle external interrupts
216 void external_interrupt(struct pt_regs *regs)
221 * Read masked interrupt status register to determine interrupt source
223 uic_msr = mfdcr(uic0msr);
226 if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) ||
227 (UIC_MASK(VECNUM_UIC1NCI) & uic_msr))
228 uic_interrupt(UIC1_DCR_BASE, 32);
232 if ((UIC_MASK(VECNUM_UIC2CI) & uic_msr) ||
233 (UIC_MASK(VECNUM_UIC2NCI) & uic_msr))
234 uic_interrupt(UIC2_DCR_BASE, 64);
238 if ((UIC_MASK(VECNUM_UIC3CI) & uic_msr) ||
239 (UIC_MASK(VECNUM_UIC3NCI) & uic_msr))
240 uic_interrupt(UIC3_DCR_BASE, 96);
243 if (uic_msr & ~(UICB0_ALL))
244 uic_interrupt(UIC0_DCR_BASE, 0);
246 mtdcr(uic0sr, uic_msr);
252 * Install and free a interrupt handler.
254 void irq_install_handler(int vec, interrupt_handler_t * handler, void *arg)
257 * Print warning when replacing with a different irq vector
259 if ((irq_vecs[vec].handler != NULL) && (irq_vecs[vec].handler != handler)) {
260 printf("Interrupt vector %d: handler 0x%x replacing 0x%x\n",
261 vec, (uint) handler, (uint) irq_vecs[vec].handler);
263 irq_vecs[vec].handler = handler;
264 irq_vecs[vec].arg = arg;
266 if ((vec >= 0) && (vec < 32))
267 mtdcr(uicer, mfdcr(uicer) | UIC_MASK(vec));
269 else if ((vec >= 32) && (vec < 64))
270 mtdcr(uic1er, mfdcr(uic1er) | UIC_MASK(vec));
273 else if ((vec >= 64) && (vec < 96))
274 mtdcr(uic2er, mfdcr(uic2er) | UIC_MASK(vec));
278 mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec));
281 debug("Install interrupt for vector %d ==> %p\n", vec, handler);
284 void irq_free_handler (int vec)
286 debug("Free interrupt for vector %d ==> %p\n",
287 vec, irq_vecs[vec].handler);
289 if ((vec >= 0) && (vec < 32))
290 mtdcr(uicer, mfdcr(uicer) & ~UIC_MASK(vec));
292 else if ((vec >= 32) && (vec < 64))
293 mtdcr(uic1er, mfdcr(uic1er) & ~UIC_MASK(vec));
296 else if ((vec >= 64) && (vec < 96))
297 mtdcr(uic2er, mfdcr(uic2er) & ~UIC_MASK(vec));
301 mtdcr(uic3er, mfdcr(uic3er) & ~UIC_MASK(vec));
304 irq_vecs[vec].handler = NULL;
305 irq_vecs[vec].arg = NULL;
308 void timer_interrupt_cpu (struct pt_regs *regs)
310 /* nothing to do here */
314 #if defined(CONFIG_CMD_IRQ)
315 int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
319 printf ("Interrupt-Information:\n");
320 printf ("Nr Routine Arg Count\n");
322 for (vec = 0; vec < (UIC_MAX * 32); vec++) {
323 if (irq_vecs[vec].handler != NULL) {
324 printf ("%02d %08lx %08lx %d\n",
326 (ulong)irq_vecs[vec].handler,
327 (ulong)irq_vecs[vec].arg,
328 irq_vecs[vec].count);