2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2002 (440 port)
6 * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
33 #include <ppc_asm.tmpl>
37 /****************************************************************************/
39 unsigned decrementer_count; /* count value for 1e6/HZ microseconds */
41 /****************************************************************************/
44 * CPM interrupt vector functions.
47 interrupt_handler_t *handler;
52 static struct irq_action irq_vecs[32];
54 #if defined(CONFIG_440)
55 static struct irq_action irq_vecs1[32]; /* For UIC1 */
57 void uic1_interrupt( void * parms); /* UIC1 handler */
60 /****************************************************************************/
62 static __inline__ unsigned long get_msr(void)
66 asm volatile("mfmsr %0" : "=r" (msr) :);
70 static __inline__ void set_msr(unsigned long msr)
72 asm volatile("mtmsr %0" : : "r" (msr));
75 #if defined(CONFIG_440)
77 /* SPRN changed in 440 */
78 static __inline__ void set_evpr(unsigned long val)
80 asm volatile("mtspr 0x03f,%0" : : "r" (val));
83 #else /* !defined(CONFIG_440) */
85 static __inline__ unsigned long get_dec(void)
89 asm volatile("mfdec %0" : "=r" (val) :);
94 static __inline__ void set_dec(unsigned long val)
96 asm volatile("mtdec %0" : : "r" (val));
100 static __inline__ void set_pit(unsigned long val)
102 asm volatile("mtpit %0" : : "r" (val));
106 static __inline__ void set_tcr(unsigned long val)
108 asm volatile("mttcr %0" : : "r" (val));
112 static __inline__ void set_evpr(unsigned long val)
114 asm volatile("mtevpr %0" : : "r" (val));
116 #endif /* defined(CONFIG_440 */
119 void enable_interrupts (void)
121 set_msr (get_msr() | MSR_EE);
124 /* returns flag if MSR_EE was set before */
125 int disable_interrupts (void)
127 ulong msr = get_msr();
128 set_msr (msr & ~MSR_EE);
129 return ((msr & MSR_EE) != 0);
132 /****************************************************************************/
134 int interrupt_init(void)
136 DECLARE_GLOBAL_DATA_PTR;
142 * Mark all irqs as free
144 for (vec=0; vec<32; vec++) {
145 irq_vecs[vec].handler = NULL;
146 irq_vecs[vec].arg = NULL;
147 irq_vecs[vec].count = 0;
148 #if defined(CONFIG_440)
149 irq_vecs1[vec].handler = NULL;
150 irq_vecs1[vec].arg = NULL;
151 irq_vecs1[vec].count = 0;
159 #if defined(CONFIG_440)
161 val &= (~0x04400000); /* clear DIS & ARE */
163 mtspr( dec, 0 ); /* Prevent exception after TSR clear*/
164 mtspr( decar, 0 ); /* clear reload */
165 mtspr( tsr, 0x08000000 ); /* clear DEC status */
166 val = gd->bd->bi_intfreq/100; /* 10 msec */
167 mtspr( decar, val ); /* Set auto-reload value */
168 mtspr( dec, val ); /* Set inital val */
170 set_pit(gd->bd->bi_intfreq / 1000);
172 #endif /* CONFIG_4xx */
191 set_evpr(0x00000000);
193 #if defined(CONFIG_440)
194 /* Install the UIC1 handlers */
195 irq_install_handler(VECNUM_UIC1NC, uic1_interrupt, 0);
196 irq_install_handler(VECNUM_UIC1C, uic1_interrupt, 0);
199 * Enable external interrupts (including PIT)
201 set_msr (get_msr() | MSR_EE);
206 /****************************************************************************/
209 * Handle external interrupts
211 void external_interrupt(struct pt_regs *regs)
218 * Read masked interrupt status register to determine interrupt source
220 uic_msr = mfdcr(uicmsr);
224 while (msr_shift != 0) {
225 if (msr_shift & 0x80000000) {
227 * Increment irq counter (for debug purpose only)
229 irq_vecs[vec].count++;
231 if (irq_vecs[vec].handler != NULL) {
233 (*irq_vecs[vec].handler)(irq_vecs[vec].arg);
235 mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> vec));
236 printf ("Masking bogus interrupt vector 0x%x\n", vec);
240 * After servicing the interrupt, we have to remove the status indicator.
242 mtdcr(uicsr, (0x80000000 >> vec));
246 * Shift msr to next position and increment vector
253 #if defined(CONFIG_440)
254 /* Handler for UIC1 interrupt */
255 void uic1_interrupt( void * parms)
262 * Read masked interrupt status register to determine interrupt source
264 uic1_msr = mfdcr(uic1msr);
265 msr_shift = uic1_msr;
268 while (msr_shift != 0) {
269 if (msr_shift & 0x80000000) {
271 * Increment irq counter (for debug purpose only)
273 irq_vecs1[vec].count++;
275 if (irq_vecs1[vec].handler != NULL) {
277 (*irq_vecs1[vec].handler)(irq_vecs1[vec].arg);
279 mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> vec));
280 printf ("Masking bogus interrupt vector (uic1) 0x%x\n", vec);
284 * After servicing the interrupt, we have to remove the status indicator.
286 mtdcr(uic1sr, (0x80000000 >> vec));
290 * Shift msr to next position and increment vector
296 #endif /* defined(CONFIG_440) */
298 /****************************************************************************/
301 * Install and free a interrupt handler.
305 irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
307 struct irq_action *irqa = irq_vecs;
310 #if defined(CONFIG_440)
317 if (irqa[i].handler != NULL) {
318 printf ("Interrupt vector %d: handler 0x%x replacing 0x%x\n",
319 vec, (uint)handler, (uint)irqa[i].handler);
321 irqa[i].handler = handler;
324 #if defined(CONFIG_440)
326 mtdcr(uic1er, mfdcr(uic1er) | (0x80000000 >> i));
329 mtdcr(uicer, mfdcr(uicer) | (0x80000000 >> i));
331 printf ("Install interrupt for vector %d ==> %p\n", vec, handler);
336 irq_free_handler(int vec)
338 struct irq_action *irqa = irq_vecs;
341 #if defined(CONFIG_440)
349 printf ("Free interrupt for vector %d ==> %p\n",
350 vec, irq_vecs[vec].handler);
353 #if defined(CONFIG_440)
355 mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> i));
358 mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> i));
360 irqa[i].handler = NULL;
364 /****************************************************************************/
367 volatile ulong timestamp = 0;
370 * timer_interrupt - gets called when the decrementer overflows,
371 * with interrupts disabled.
372 * Trivial implementation - no need to be really accurate.
374 void timer_interrupt(struct pt_regs *regs)
377 printf ("*** Timer Interrupt *** ");
381 #if defined(CONFIG_WATCHDOG)
382 if ((timestamp % 1000) == 0)
383 reset_4xx_watchdog();
384 #endif /* CONFIG_WATCHDOG */
387 /****************************************************************************/
389 void reset_timer (void)
394 ulong get_timer (ulong base)
396 return (timestamp - base);
399 void set_timer (ulong t)
404 /****************************************************************************/
407 #if (CONFIG_COMMANDS & CFG_CMD_IRQ)
409 /*******************************************************************************
411 * irqinfo - print information about PCI devices
415 do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
419 printf ("\nInterrupt-Information:\n");
420 #if defined(CONFIG_440)
421 printf ("\nUIC 0\n");
423 printf ("Nr Routine Arg Count\n");
425 for (vec=0; vec<32; vec++) {
426 if (irq_vecs[vec].handler != NULL) {
427 printf ("%02d %08lx %08lx %d\n",
429 (ulong)irq_vecs[vec].handler,
430 (ulong)irq_vecs[vec].arg,
431 irq_vecs[vec].count);
435 #if defined(CONFIG_440)
436 printf ("\nUIC 1\n");
437 printf ("Nr Routine Arg Count\n");
439 for (vec=0; vec<32; vec++)
441 if (irq_vecs1[vec].handler != NULL)
442 printf ("%02d %08lx %08lx %d\n",
443 vec+31, (ulong)irq_vecs1[vec].handler,
444 (ulong)irq_vecs1[vec].arg, irq_vecs1[vec].count);
452 #endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */