1 /*****************************************************************************/
2 /* I2C Bus interface initialisation and I2C Commands */
4 /* Author : AS HARNOIS */
6 /*****************************************************************************/
10 #if defined(CONFIG_440)
13 # include <405gp_i2c.h>
17 #ifdef CONFIG_HARD_I2C
21 #define IIC_NOK_LA 2 /* Lost arbitration */
22 #define IIC_NOK_ICT 3 /* Incomplete transfer */
23 #define IIC_NOK_XFRA 4 /* Transfer aborted */
24 #define IIC_NOK_DATA 5 /* No data in buffer */
25 #define IIC_NOK_TOUT 6 /* Transfer timeout */
27 #define IIC_TIMEOUT 1 /* 1 seconde */
30 static void _i2c_bus_reset (void)
34 /* Reset status register */
35 /* write 1 in SCMP and IRQA to clear these fields */
38 /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
39 out8 (IIC_EXTSTS, 0x8F);
40 __asm__ volatile ("eieio");
43 * Get current state, reset bus
44 * only if no transfers are pending.
49 status = in8 (IIC_STS);
50 udelay (500); /* 500us */
52 } while ((status & IIC_STS_PT) && (i > 0));
53 /* Soft reset controller */
54 status = in8 (IIC_XTCNTLSS);
55 out8 (IIC_XTCNTLSS, (status | IIC_XTCNTLSS_SRST));
56 __asm__ volatile ("eieio");
58 /* make sure where in initial state, data hi, clock hi */
59 out8 (IIC_DIRECTCNTL, 0xC);
60 for (i = 0; i < 10; i++) {
61 if ((in8 (IIC_DIRECTCNTL) & 0x3) != 0x3) {
62 /* clock until we get to known state */
63 out8 (IIC_DIRECTCNTL, 0x8); /* clock lo */
64 udelay (100); /* 100us */
65 out8 (IIC_DIRECTCNTL, 0xC); /* clock hi */
66 udelay (100); /* 100us */
71 /* send start condition */
72 out8 (IIC_DIRECTCNTL, 0x4);
73 udelay (1000); /* 1ms */
74 /* send stop condition */
75 out8 (IIC_DIRECTCNTL, 0xC);
76 udelay (1000); /* 1ms */
77 /* Unreset controller */
78 out8 (IIC_XTCNTLSS, (status & ~IIC_XTCNTLSS_SRST));
79 udelay (1000); /* 1ms */
82 void i2c_init (int speed, int slaveadd)
85 unsigned long freqOPB;
88 #ifdef CFG_I2C_INIT_BOARD
89 /* call board specific i2c bus reset routine before accessing the */
90 /* environment, which might be in a chip on that bus. For details */
91 /* about this problem see doc/I2C_Edge_Conditions. */
95 /* Handle possible failed I2C state */
96 /* FIXME: put this into i2c_init_board()? */
99 /* clear lo master address */
102 /* clear hi master address */
105 /* clear lo slave address */
108 /* clear hi slave address */
111 /* Clock divide Register */
112 /* get OPB frequency */
113 get_sys_info (&sysInfo);
114 freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
115 /* set divisor according to freqOPB */
116 divisor = (freqOPB - 1) / 10000000;
119 out8 (IIC_CLKDIV, divisor);
122 out8 (IIC_INTRMSK, 0);
124 /* clear transfer count */
125 out8 (IIC_XFRCNT, 0);
127 /* clear extended control & stat */
128 /* write 1 in SRC SRS SWC SWS to clear these fields */
129 out8 (IIC_XTCNTLSS, 0xF0);
131 /* Mode Control Register
132 Flush Slave/Master data buffer */
133 out8 (IIC_MDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
134 __asm__ volatile ("eieio");
137 val = in8(IIC_MDCNTL);
138 __asm__ volatile ("eieio");
140 /* Ignore General Call, slave transfers are ignored,
141 disable interrupts, exit unknown bus state, enable hold
143 100kHz normaly or FastMode for 400kHz and above
146 val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
147 if( speed >= 400000 ){
148 val |= IIC_MDCNTL_FSM;
150 out8 (IIC_MDCNTL, val);
152 /* clear control reg */
153 out8 (IIC_CNTL, 0x00);
154 __asm__ volatile ("eieio");
159 This code tries to use the features of the 405GP i2c
160 controller. It will transfer up to 4 bytes in one pass
161 on the loop. It only does out8(lbz) to the buffer when it
162 is possible to do out16(lhz) transfers.
164 cmd_type is 0 for write 1 for read.
166 addr_len can take any value from 0-255, it is only limited
167 by the char, we could make it larger if needed. If it is
168 0 we skip the address write cycle.
170 Typical case is a Write of an addr followd by a Read. The
171 IBM FAQ does not cover this. On the last byte of the write
172 we don't set the creg CHT bit, and on the first bytes of the
173 read we set the RPST bit.
175 It does not support address only transfers, there must be
176 a data part. If you want to write the address yourself, put
177 it in the data pointer.
179 It does not support transfer to/from address 0.
181 It does not check XFRCNT.
184 int i2c_transfer(unsigned char cmd_type,
186 unsigned char addr[],
187 unsigned char addr_len,
188 unsigned char data[],
189 unsigned short data_len )
199 if( data == 0 || data_len == 0 ){
200 /*Don't support data transfer of no length or to address 0*/
201 printf( "i2c_transfer: bad call\n" );
204 if( addr && addr_len ){
214 /*Clear Stop Complete Bit*/
215 out8(IIC_STS,IIC_STS_SCMP);
220 status = in8(IIC_STS);
221 __asm__ volatile("eieio");
223 } while ((status & IIC_STS_PT) && (i>0));
225 if (status & IIC_STS_PT) {
226 result = IIC_NOK_TOUT;
229 /*flush the Master/Slave Databuffers*/
230 out8(IIC_MDCNTL, ((in8(IIC_MDCNTL))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
231 /*need to wait 4 OPB clocks? code below should take that long*/
233 /* 7-bit adressing */
235 out8(IIC_LMADR, chip);
236 __asm__ volatile("eieio");
242 while ( tran != cnt && (result == IIC_OK)) {
245 /* Control register =
246 Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
247 Transfer is a sequence of transfers
251 bc = (cnt - tran) > 4 ? 4 :
254 /* if the real cmd type is write continue trans*/
255 if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) )
256 creg |= IIC_CNTL_CHT;
259 creg |= IIC_CNTL_READ;
261 for(j=0; j<bc; j++) {
263 out8(IIC_MDBUF,ptr[tran+j]);
264 __asm__ volatile("eieio");
267 out8(IIC_CNTL, creg );
268 __asm__ volatile("eieio");
270 /* Transfer is in progress
271 we have to wait for upto 5 bytes of data
272 1 byte chip address+r/w bit then bc bytes
274 udelay(10) is 1 bit time at 100khz
275 Doubled for slop. 20 is too small.
280 status = in8(IIC_STS);
281 __asm__ volatile("eieio");
284 } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
287 if (status & IIC_STS_ERR) {
289 status = in8 (IIC_EXTSTS);
290 /* Lost arbitration? */
291 if (status & IIC_EXTSTS_LA)
293 /* Incomplete transfer? */
294 if (status & IIC_EXTSTS_ICT)
295 result = IIC_NOK_ICT;
296 /* Transfer aborted? */
297 if (status & IIC_EXTSTS_XFRA)
298 result = IIC_NOK_XFRA;
299 } else if ( status & IIC_STS_PT) {
300 result = IIC_NOK_TOUT;
302 /* Command is reading => get buffer */
303 if ((reading) && (result == IIC_OK)) {
304 /* Are there data in buffer */
305 if (status & IIC_STS_MDBS) {
307 even if we have data we have to wait 4OPB clocks
308 for it to hit the front of the FIFO, after that
309 we can just read. We should check XFCNT here and
310 if the FIFO is full there is no need to wait.
314 ptr[tran+j] = in8(IIC_MDBUF);
315 __asm__ volatile("eieio");
318 result = IIC_NOK_DATA;
322 if( ptr == addr && tran == cnt ) {
328 creg = IIC_CNTL_RPST;
334 int i2c_probe (uchar chip)
341 * What is needed is to send the chip address and verify that the
342 * address was <ACK>ed (i.e. there was a chip at that address which
343 * drove the data line low).
345 return(i2c_transfer (1, chip << 1, 0,0, buf, 1) != 0);
349 int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
353 DECLARE_GLOBAL_DATA_PTR;
356 printf ("I2C read: addr len %d not supported\n", alen);
361 xaddr[0] = (addr >> 24) & 0xFF;
362 xaddr[1] = (addr >> 16) & 0xFF;
363 xaddr[2] = (addr >> 8) & 0xFF;
364 xaddr[3] = addr & 0xFF;
368 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
370 * EEPROM chips that implement "address overflow" are ones
371 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
372 * address and the extra bits end up in the "chip address"
373 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
374 * four 256 byte chips.
376 * Note that we consider the length of the address field to
377 * still be one byte because the extra address bits are
378 * hidden in the chip address.
381 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
383 if( (ret = i2c_transfer( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
384 if (gd->have_console)
385 printf( "I2c read: failed %d\n", ret);
391 int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
396 printf ("I2C write: addr len %d not supported\n", alen);
401 xaddr[0] = (addr >> 24) & 0xFF;
402 xaddr[1] = (addr >> 16) & 0xFF;
403 xaddr[2] = (addr >> 8) & 0xFF;
404 xaddr[3] = addr & 0xFF;
407 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
409 * EEPROM chips that implement "address overflow" are ones
410 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
411 * address and the extra bits end up in the "chip address"
412 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
413 * four 256 byte chips.
415 * Note that we consider the length of the address field to
416 * still be one byte because the extra address bits are
417 * hidden in the chip address.
420 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
423 return (i2c_transfer( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
426 /*-----------------------------------------------------------------------
429 uchar i2c_reg_read(uchar i2c_addr, uchar reg)
433 i2c_read(i2c_addr, reg, 1, &buf, 1);
438 /*-----------------------------------------------------------------------
441 void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
443 i2c_write(i2c_addr, reg, 1, &val, 1);
445 #endif /* CONFIG_HARD_I2C */