cpu/ppc4xx/denali_spd_ddr2.c

   1 /*
   2  * cpu/ppc4xx/denali_spd_ddr2.c
   3  * This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core
   4  * DDR2 controller, specifically the 440EPx/GRx.
   5  *
   6  * (C) Copyright 2007-2008
   7  * Larry Johnson, lrj@acm.org.
   8  *
   9  * Based primarily on cpu/ppc4xx/4xx_spd_ddr2.c, which is...
  10  *
  11  * (C) Copyright 2007
  12  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  13  *
  14  * COPYRIGHT   AMCC   CORPORATION 2004
  15  *
  16  * See file CREDITS for list of people who contributed to this
  17  * project.
  18  *
  19  * This program is free software; you can redistribute it and/or
  20  * modify it under the terms of the GNU General Public License as
  21  * published by the Free Software Foundation; either version 2 of
  22  * the License, or (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32  * MA 02111-1307 USA
  33  *
  34  */
  35
  36 /* define DEBUG for debugging output (obviously ;-)) */
  37 #if 0
  38 #define DEBUG
  39 #endif
  40
  41 #include <common.h>
  42 #include <command.h>
  43 #include <ppc4xx.h>
  44 #include <i2c.h>
  45 #include <asm/io.h>
  46 #include <asm/processor.h>
  47 #include <asm/mmu.h>
  48
  49 #if defined(CONFIG_SPD_EEPROM) &&                               \
  50         (defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
  51
  52 /*-----------------------------------------------------------------------------+
  53  * Defines
  54  *-----------------------------------------------------------------------------*/
  55 #ifndef TRUE
  56 #define TRUE            1
  57 #endif
  58 #ifndef FALSE
  59 #define FALSE           0
  60 #endif
  61
  62 #define MAXDIMMS        2
  63 #define MAXRANKS        2
  64
  65 #define ONE_BILLION     1000000000
  66
  67 #define MULDIV64(m1, m2, d)     (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
  68
  69 #define DLL_DQS_DELAY   0x19
  70 #define DLL_DQS_BYPASS  0x0B
  71 #define DQS_OUT_SHIFT   0x7F
  72
  73 /*
  74  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
  75  * region. Right now the cache should still be disabled in U-Boot because of the
  76  * EMAC driver, that need it's buffer descriptor to be located in non cached
  77  * memory.
  78  *
  79  * If at some time this restriction doesn't apply anymore, just define
  80  * CONFIG_4xx_DCACHE in the board config file and this code should setup
  81  * everything correctly.
  82  */
  83 #if defined(CONFIG_4xx_DCACHE)
  84 #define MY_TLB_WORD2_I_ENABLE   0                       /* enable caching on SDRAM */
  85 #else
  86 #define MY_TLB_WORD2_I_ENABLE   TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
  87 #endif
  88
  89 /*-----------------------------------------------------------------------------+
  90  * Prototypes
  91  *-----------------------------------------------------------------------------*/
  92 extern int denali_wait_for_dlllock(void);
  93 extern void denali_core_search_data_eye(void);
  94 extern void dcbz_area(u32 start_address, u32 num_bytes);
  95
  96 /*
  97  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
  98  */
  99 void __spd_ddr_init_hang(void)
 100 {
 101         hang();
 102 }
 103 void spd_ddr_init_hang(void)
 104     __attribute__ ((weak, alias("__spd_ddr_init_hang")));
 105
 106 #if defined(DEBUG)
 107 static void print_mcsr(void)
 108 {
 109         printf("MCSR = 0x%08X\n", mfspr(SPRN_MCSR));
 110 }
 111
 112 static void denali_sdram_register_dump(void)
 113 {
 114         unsigned int sdram_data;
 115
 116         printf("\n  Register Dump:\n");
 117         mfsdram(DDR0_00, sdram_data);
 118         printf("        DDR0_00 = 0x%08X", sdram_data);
 119         mfsdram(DDR0_01, sdram_data);
 120         printf("        DDR0_01 = 0x%08X\n", sdram_data);
 121         mfsdram(DDR0_02, sdram_data);
 122         printf("        DDR0_02 = 0x%08X", sdram_data);
 123         mfsdram(DDR0_03, sdram_data);
 124         printf("        DDR0_03 = 0x%08X\n", sdram_data);
 125         mfsdram(DDR0_04, sdram_data);
 126         printf("        DDR0_04 = 0x%08X", sdram_data);
 127         mfsdram(DDR0_05, sdram_data);
 128         printf("        DDR0_05 = 0x%08X\n", sdram_data);
 129         mfsdram(DDR0_06, sdram_data);
 130         printf("        DDR0_06 = 0x%08X", sdram_data);
 131         mfsdram(DDR0_07, sdram_data);
 132         printf("        DDR0_07 = 0x%08X\n", sdram_data);
 133         mfsdram(DDR0_08, sdram_data);
 134         printf("        DDR0_08 = 0x%08X", sdram_data);
 135         mfsdram(DDR0_09, sdram_data);
 136         printf("        DDR0_09 = 0x%08X\n", sdram_data);
 137         mfsdram(DDR0_10, sdram_data);
 138         printf("        DDR0_10 = 0x%08X", sdram_data);
 139         mfsdram(DDR0_11, sdram_data);
 140         printf("        DDR0_11 = 0x%08X\n", sdram_data);
 141         mfsdram(DDR0_12, sdram_data);
 142         printf("        DDR0_12 = 0x%08X", sdram_data);
 143         mfsdram(DDR0_14, sdram_data);
 144         printf("        DDR0_14 = 0x%08X\n", sdram_data);
 145         mfsdram(DDR0_17, sdram_data);
 146         printf("        DDR0_17 = 0x%08X", sdram_data);
 147         mfsdram(DDR0_18, sdram_data);
 148         printf("        DDR0_18 = 0x%08X\n", sdram_data);
 149         mfsdram(DDR0_19, sdram_data);
 150         printf("        DDR0_19 = 0x%08X", sdram_data);
 151         mfsdram(DDR0_20, sdram_data);
 152         printf("        DDR0_20 = 0x%08X\n", sdram_data);
 153         mfsdram(DDR0_21, sdram_data);
 154         printf("        DDR0_21 = 0x%08X", sdram_data);
 155         mfsdram(DDR0_22, sdram_data);
 156         printf("        DDR0_22 = 0x%08X\n", sdram_data);
 157         mfsdram(DDR0_23, sdram_data);
 158         printf("        DDR0_23 = 0x%08X", sdram_data);
 159         mfsdram(DDR0_24, sdram_data);
 160         printf("        DDR0_24 = 0x%08X\n", sdram_data);
 161         mfsdram(DDR0_25, sdram_data);
 162         printf("        DDR0_25 = 0x%08X", sdram_data);
 163         mfsdram(DDR0_26, sdram_data);
 164         printf("        DDR0_26 = 0x%08X\n", sdram_data);
 165         mfsdram(DDR0_27, sdram_data);
 166         printf("        DDR0_27 = 0x%08X", sdram_data);
 167         mfsdram(DDR0_28, sdram_data);
 168         printf("        DDR0_28 = 0x%08X\n", sdram_data);
 169         mfsdram(DDR0_31, sdram_data);
 170         printf("        DDR0_31 = 0x%08X", sdram_data);
 171         mfsdram(DDR0_32, sdram_data);
 172         printf("        DDR0_32 = 0x%08X\n", sdram_data);
 173         mfsdram(DDR0_33, sdram_data);
 174         printf("        DDR0_33 = 0x%08X", sdram_data);
 175         mfsdram(DDR0_34, sdram_data);
 176         printf("        DDR0_34 = 0x%08X\n", sdram_data);
 177         mfsdram(DDR0_35, sdram_data);
 178         printf("        DDR0_35 = 0x%08X", sdram_data);
 179         mfsdram(DDR0_36, sdram_data);
 180         printf("        DDR0_36 = 0x%08X\n", sdram_data);
 181         mfsdram(DDR0_37, sdram_data);
 182         printf("        DDR0_37 = 0x%08X", sdram_data);
 183         mfsdram(DDR0_38, sdram_data);
 184         printf("        DDR0_38 = 0x%08X\n", sdram_data);
 185         mfsdram(DDR0_39, sdram_data);
 186         printf("        DDR0_39 = 0x%08X", sdram_data);
 187         mfsdram(DDR0_40, sdram_data);
 188         printf("        DDR0_40 = 0x%08X\n", sdram_data);
 189         mfsdram(DDR0_41, sdram_data);
 190         printf("        DDR0_41 = 0x%08X", sdram_data);
 191         mfsdram(DDR0_42, sdram_data);
 192         printf("        DDR0_42 = 0x%08X\n", sdram_data);
 193         mfsdram(DDR0_43, sdram_data);
 194         printf("        DDR0_43 = 0x%08X", sdram_data);
 195         mfsdram(DDR0_44, sdram_data);
 196         printf("        DDR0_44 = 0x%08X\n", sdram_data);
 197 }
 198 #else
 199 static inline void denali_sdram_register_dump(void)
 200 {
 201 }
 202
 203 inline static void print_mcsr(void)
 204 {
 205 }
 206 #endif /* defined(DEBUG) */
 207
 208 static int is_ecc_enabled(void)
 209 {
 210         u32 val;
 211
 212         mfsdram(DDR0_22, val);
 213         return 0x3 == DDR0_22_CTRL_RAW_DECODE(val);
 214 }
 215
 216 static unsigned char spd_read(u8 chip, unsigned int addr)
 217 {
 218         u8 data[2];
 219
 220         if (0 != i2c_probe(chip) || 0 != i2c_read(chip, addr, 1, data, 1)) {
 221                 debug("spd_read(0x%02X, 0x%02X) failed\n", chip, addr);
 222                 return 0;
 223         }
 224         debug("spd_read(0x%02X, 0x%02X) returned 0x%02X\n",
 225               chip, addr, data[0]);
 226         return data[0];
 227 }
 228
 229 static unsigned long get_tcyc(unsigned char reg)
 230 {
 231         /*
 232          * Byte 9, et al: Cycle time for CAS Latency=X, is split into two
 233          * nibbles: the higher order nibble (bits 4-7) designates the cycle time
 234          * to a granularity of 1ns; the value presented by the lower order
 235          * nibble (bits 0-3) has a granularity of .1ns and is added to the value
 236          * designated by the higher nibble. In addition, four lines of the lower
 237          * order nibble are assigned to support +.25, +.33, +.66, and +.75.
 238          */
 239
 240         unsigned char subfield_b = reg & 0x0F;
 241
 242         switch (subfield_b & 0x0F) {
 243         case 0x0:
 244         case 0x1:
 245         case 0x2:
 246         case 0x3:
 247         case 0x4:
 248         case 0x5:
 249         case 0x6:
 250         case 0x7:
 251         case 0x8:
 252         case 0x9:
 253                 return 1000 * (reg >> 4) + 100 * subfield_b;
 254         case 0xA:
 255                 return 1000 * (reg >> 4) + 250;
 256         case 0xB:
 257                 return 1000 * (reg >> 4) + 333;
 258         case 0xC:
 259                 return 1000 * (reg >> 4) + 667;
 260         case 0xD:
 261                 return 1000 * (reg >> 4) + 750;
 262         }
 263         return 0;
 264 }
 265
 266 /*------------------------------------------------------------------
 267  * Find the installed DIMMs, make sure that the are DDR2, and fill
 268  * in the dimm_ranks array.  Then dimm_ranks[dimm_num] > 0 iff the
 269  * DIMM and dimm_num is present.
 270  * Note: Because there are only two chip-select lines, it is assumed
 271  * that a board with a single socket can support two ranks on that
 272  * socket, while a board with two sockets can support only one rank
 273  * on each socket.
 274  *-----------------------------------------------------------------*/
 275 static void get_spd_info(unsigned long dimm_ranks[],
 276                          unsigned long *ranks,
 277                          unsigned char const iic0_dimm_addr[],
 278                          unsigned long num_dimm_banks)
 279 {
 280         unsigned long dimm_num;
 281         unsigned long dimm_found = FALSE;
 282         unsigned long const max_ranks_per_dimm = (1 == num_dimm_banks) ? 2 : 1;
 283         unsigned char num_of_bytes;
 284         unsigned char total_size;
 285
 286         *ranks = 0;
 287         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 288                 num_of_bytes = 0;
 289                 total_size = 0;
 290
 291                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 292                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 293                 if ((num_of_bytes != 0) && (total_size != 0)) {
 294                         unsigned char const dimm_type =
 295                             spd_read(iic0_dimm_addr[dimm_num], 2);
 296
 297                         unsigned long ranks_on_dimm =
 298                             (spd_read(iic0_dimm_addr[dimm_num], 5) & 0x07) + 1;
 299
 300                         if (8 != dimm_type) {
 301                                 switch (dimm_type) {
 302                                 case 1:
 303                                         printf("ERROR: Standard Fast Page Mode "
 304                                                "DRAM DIMM");
 305                                         break;
 306                                 case 2:
 307                                         printf("ERROR: EDO DIMM");
 308                                         break;
 309                                 case 3:
 310                                         printf("ERROR: Pipelined Nibble DIMM");
 311                                         break;
 312                                 case 4:
 313                                         printf("ERROR: SDRAM DIMM");
 314                                         break;
 315                                 case 5:
 316                                         printf("ERROR: Multiplexed ROM DIMM");
 317                                         break;
 318                                 case 6:
 319                                         printf("ERROR: SGRAM DIMM");
 320                                         break;
 321                                 case 7:
 322                                         printf("ERROR: DDR1 DIMM");
 323                                         break;
 324                                 default:
 325                                         printf("ERROR: Unknown DIMM (type %d)",
 326                                                (unsigned int)dimm_type);
 327                                         break;
 328                                 }
 329                                 printf(" detected in slot %lu.\n", dimm_num);
 330                                 printf("Only DDR2 SDRAM DIMMs are supported."
 331                                        "\n");
 332                                 printf("Replace the module with a DDR2 DIMM."
 333                                        "\n\n");
 334                                 spd_ddr_init_hang();
 335                         }
 336                         dimm_found = TRUE;
 337                         debug("DIMM slot %lu: populated with %lu-rank DDR2 DIMM"
 338                               "\n", dimm_num, ranks_on_dimm);
 339                         if (ranks_on_dimm > max_ranks_per_dimm) {
 340                                 printf("WARNING: DRAM DIMM in slot %lu has %lu "
 341                                        "ranks.\n");
 342                                 if (1 == max_ranks_per_dimm) {
 343                                         printf("Only one rank will be used.\n");
 344                                 } else {
 345                                         printf
 346                                             ("Only two ranks will be used.\n");
 347                                 }
 348                                 ranks_on_dimm = max_ranks_per_dimm;
 349                         }
 350                         dimm_ranks[dimm_num] = ranks_on_dimm;
 351                         *ranks += ranks_on_dimm;
 352                 } else {
 353                         dimm_ranks[dimm_num] = 0;
 354                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 355                 }
 356         }
 357         if (dimm_found == FALSE) {
 358                 printf("ERROR: No memory installed.\n");
 359                 printf("Install at least one DDR2 DIMM.\n\n");
 360                 spd_ddr_init_hang();
 361         }
 362         debug("Total number of ranks = %d\n", *ranks);
 363 }
 364
 365 /*------------------------------------------------------------------
 366  * For the memory DIMMs installed, this routine verifies that
 367  * frequency previously calculated is supported.
 368  *-----------------------------------------------------------------*/
 369 static void check_frequency(unsigned long *dimm_ranks,
 370                             unsigned char const iic0_dimm_addr[],
 371                             unsigned long num_dimm_banks,
 372                             unsigned long sdram_freq)
 373 {
 374         unsigned long dimm_num;
 375         unsigned long cycle_time;
 376         unsigned long calc_cycle_time;
 377
 378         /*
 379          * calc_cycle_time is calculated from DDR frequency set by board/chip
 380          * and is expressed in picoseconds to match the way DIMM cycle time is
 381          * calculated below.
 382          */
 383         calc_cycle_time = MULDIV64(ONE_BILLION, 1000, sdram_freq);
 384
 385         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 386                 if (dimm_ranks[dimm_num]) {
 387                         cycle_time =
 388                             get_tcyc(spd_read(iic0_dimm_addr[dimm_num], 9));
 389                         debug("cycle_time=%d ps\n", cycle_time);
 390
 391                         if (cycle_time > (calc_cycle_time + 10)) {
 392                                 /*
 393                                  * the provided sdram cycle_time is too small
 394                                  * for the available DIMM cycle_time. The
 395                                  * additionnal 10ps is here to accept a small
 396                                  * incertainty.
 397                                  */
 398                                 printf
 399                                     ("ERROR: DRAM DIMM detected with cycle_time %d ps in "
 400                                      "slot %d \n while calculated cycle time is %d ps.\n",
 401                                      (unsigned int)cycle_time,
 402                                      (unsigned int)dimm_num,
 403                                      (unsigned int)calc_cycle_time);
 404                                 printf
 405                                     ("Replace the DIMM, or change DDR frequency via "
 406                                      "strapping bits.\n\n");
 407                                 spd_ddr_init_hang();
 408                         }
 409                 }
 410         }
 411 }
 412
 413 /*------------------------------------------------------------------
 414  * This routine gets size information for the installed memory
 415  * DIMMs.
 416  *-----------------------------------------------------------------*/
 417 static void get_dimm_size(unsigned long dimm_ranks[],
 418                           unsigned char const iic0_dimm_addr[],
 419                           unsigned long num_dimm_banks,
 420                           unsigned long *const rows,
 421                           unsigned long *const banks,
 422                           unsigned long *const cols, unsigned long *const width)
 423 {
 424         unsigned long dimm_num;
 425
 426         *rows = 0;
 427         *banks = 0;
 428         *cols = 0;
 429         *width = 0;
 430         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 431                 if (dimm_ranks[dimm_num]) {
 432                         unsigned long t;
 433
 434                         /* Rows */
 435                         t = spd_read(iic0_dimm_addr[dimm_num], 3);
 436                         if (0 == *rows) {
 437                                 *rows = t;
 438                         } else if (t != *rows) {
 439                                 printf("ERROR: DRAM DIMM modules do not all "
 440                                        "have the same number of rows.\n\n");
 441                                 spd_ddr_init_hang();
 442                         }
 443                         /* Banks */
 444                         t = spd_read(iic0_dimm_addr[dimm_num], 17);
 445                         if (0 == *banks) {
 446                                 *banks = t;
 447                         } else if (t != *banks) {
 448                                 printf("ERROR: DRAM DIMM modules do not all "
 449                                        "have the same number of banks.\n\n");
 450                                 spd_ddr_init_hang();
 451                         }
 452                         /* Columns */
 453                         t = spd_read(iic0_dimm_addr[dimm_num], 4);
 454                         if (0 == *cols) {
 455                                 *cols = t;
 456                         } else if (t != *cols) {
 457                                 printf("ERROR: DRAM DIMM modules do not all "
 458                                        "have the same number of columns.\n\n");
 459                                 spd_ddr_init_hang();
 460                         }
 461                         /* Data width */
 462                         t = spd_read(iic0_dimm_addr[dimm_num], 6);
 463                         if (0 == *width) {
 464                                 *width = t;
 465                         } else if (t != *width) {
 466                                 printf("ERROR: DRAM DIMM modules do not all "
 467                                        "have the same data width.\n\n");
 468                                 spd_ddr_init_hang();
 469                         }
 470                 }
 471         }
 472         debug("Number of rows = %d\n", *rows);
 473         debug("Number of columns = %d\n", *cols);
 474         debug("Number of banks = %d\n", *banks);
 475         debug("Data width = %d\n", *width);
 476         if (*rows > 14) {
 477                 printf("ERROR: DRAM DIMM modules have %lu address rows.\n",
 478                        *rows);
 479                 printf("Only modules with 14 or fewer rows are supported.\n\n");
 480                 spd_ddr_init_hang();
 481         }
 482         if (4 != *banks && 8 != *banks) {
 483                 printf("ERROR: DRAM DIMM modules have %lu banks.\n", *banks);
 484                 printf("Only modules with 4 or 8 banks are supported.\n\n");
 485                 spd_ddr_init_hang();
 486         }
 487         if (*cols > 12) {
 488                 printf("ERROR: DRAM DIMM modules have %lu address columns.\n",
 489                        *cols);
 490                 printf("Only modules with 12 or fewer columns are "
 491                        "supported.\n\n");
 492                 spd_ddr_init_hang();
 493         }
 494         if (32 != *width && 40 != *width && 64 != *width && 72 != *width) {
 495                 printf("ERROR: DRAM DIMM modules have a width of %lu bit.\n",
 496                        *width);
 497                 printf("Only modules with widths of 32, 40, 64, and 72 bits "
 498                        "are supported.\n\n");
 499                 spd_ddr_init_hang();
 500         }
 501 }
 502
 503 /*------------------------------------------------------------------
 504  * Only 1.8V modules are supported.  This routine verifies this.
 505  *-----------------------------------------------------------------*/
 506 static void check_voltage_type(unsigned long dimm_ranks[],
 507                                unsigned char const iic0_dimm_addr[],
 508                                unsigned long num_dimm_banks)
 509 {
 510         unsigned long dimm_num;
 511         unsigned long voltage_type;
 512
 513         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 514                 if (dimm_ranks[dimm_num]) {
 515                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 516                         if (0x05 != voltage_type) {     /* 1.8V for DDR2 */
 517                                 printf("ERROR: Slot %lu provides 1.8V for DDR2 "
 518                                        "DIMMs.\n", dimm_num);
 519                                 switch (voltage_type) {
 520                                 case 0x00:
 521                                         printf("This DIMM is 5.0 Volt/TTL.\n");
 522                                         break;
 523                                 case 0x01:
 524                                         printf("This DIMM is LVTTL.\n");
 525                                         break;
 526                                 case 0x02:
 527                                         printf("This DIMM is 1.5 Volt.\n");
 528                                         break;
 529                                 case 0x03:
 530                                         printf("This DIMM is 3.3 Volt/TTL.\n");
 531                                         break;
 532                                 case 0x04:
 533                                         printf("This DIMM is 2.5 Volt.\n");
 534                                         break;
 535                                 default:
 536                                         printf("This DIMM is an unknown "
 537                                                "voltage.\n");
 538                                         break;
 539                                 }
 540                                 printf("Replace it with a 1.8V DDR2 DIMM.\n\n");
 541                                 spd_ddr_init_hang();
 542                         }
 543                 }
 544         }
 545 }
 546
 547 static void program_ddr0_03(unsigned long dimm_ranks[],
 548                             unsigned char const iic0_dimm_addr[],
 549                             unsigned long num_dimm_banks,
 550                             unsigned long sdram_freq,
 551                             unsigned long rows, unsigned long *cas_latency)
 552 {
 553         unsigned long dimm_num;
 554         unsigned long cas_index;
 555         unsigned long cycle_2_0_clk;
 556         unsigned long cycle_3_0_clk;
 557         unsigned long cycle_4_0_clk;
 558         unsigned long cycle_5_0_clk;
 559         unsigned long max_2_0_tcyc_ps = 100;
 560         unsigned long max_3_0_tcyc_ps = 100;
 561         unsigned long max_4_0_tcyc_ps = 100;
 562         unsigned long max_5_0_tcyc_ps = 100;
 563         unsigned char cas_available = 0x3C;     /* value for DDR2 */
 564         u32 ddr0_03 = DDR0_03_BSTLEN_ENCODE(0x2) | DDR0_03_INITAREF_ENCODE(0x2);
 565         unsigned int const tcyc_addr[3] = { 9, 23, 25 };
 566
 567         /*------------------------------------------------------------------
 568          * Get the board configuration info.
 569          *-----------------------------------------------------------------*/
 570         debug("sdram_freq = %d\n", sdram_freq);
 571
 572         /*------------------------------------------------------------------
 573          * Handle the timing.  We need to find the worst case timing of all
 574          * the dimm modules installed.
 575          *-----------------------------------------------------------------*/
 576         /* loop through all the DIMM slots on the board */
 577         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 578                 /* If a dimm is installed in a particular slot ... */
 579                 if (dimm_ranks[dimm_num]) {
 580                         unsigned char const cas_bit =
 581                             spd_read(iic0_dimm_addr[dimm_num], 18);
 582                         unsigned char cas_mask;
 583
 584                         cas_available &= cas_bit;
 585                         for (cas_mask = 0x80; cas_mask; cas_mask >>= 1) {
 586                                 if (cas_bit & cas_mask)
 587                                         break;
 588                         }
 589                         debug("cas_bit (SPD byte 18) = %02X, cas_mask = %02X\n",
 590                               cas_bit, cas_mask);
 591
 592                         for (cas_index = 0; cas_index < 3;
 593                              cas_mask >>= 1, cas_index++) {
 594                                 unsigned long cycle_time_ps;
 595
 596                                 if (!(cas_available & cas_mask)) {
 597                                         continue;
 598                                 }
 599                                 cycle_time_ps =
 600                                     get_tcyc(spd_read(iic0_dimm_addr[dimm_num],
 601                                                       tcyc_addr[cas_index]));
 602
 603                                 debug("cas_index = %d: cycle_time_ps = %d\n",
 604                                       cas_index, cycle_time_ps);
 605                                 /*
 606                                  * DDR2 devices use the following bitmask for CAS latency:
 607                                  *  Bit   7    6    5    4    3    2    1    0
 608                                  *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
 609                                  */
 610                                 switch (cas_mask) {
 611                                 case 0x20:
 612                                         max_5_0_tcyc_ps =
 613                                             max(max_5_0_tcyc_ps, cycle_time_ps);
 614                                         break;
 615                                 case 0x10:
 616                                         max_4_0_tcyc_ps =
 617                                             max(max_4_0_tcyc_ps, cycle_time_ps);
 618                                         break;
 619                                 case 0x08:
 620                                         max_3_0_tcyc_ps =
 621                                             max(max_3_0_tcyc_ps, cycle_time_ps);
 622                                         break;
 623                                 case 0x04:
 624                                         max_2_0_tcyc_ps =
 625                                             max(max_2_0_tcyc_ps, cycle_time_ps);
 626                                         break;
 627                                 }
 628                         }
 629                 }
 630         }
 631         debug("cas_available (bit map) = 0x%02X\n", cas_available);
 632
 633         /*------------------------------------------------------------------
 634          * Set the SDRAM mode, SDRAM_MMODE
 635          *-----------------------------------------------------------------*/
 636
 637         /* add 10 here because of rounding problems */
 638         cycle_2_0_clk = MULDIV64(ONE_BILLION, 1000, max_2_0_tcyc_ps) + 10;
 639         cycle_3_0_clk = MULDIV64(ONE_BILLION, 1000, max_3_0_tcyc_ps) + 10;
 640         cycle_4_0_clk = MULDIV64(ONE_BILLION, 1000, max_4_0_tcyc_ps) + 10;
 641         cycle_5_0_clk = MULDIV64(ONE_BILLION, 1000, max_5_0_tcyc_ps) + 10;
 642         debug("cycle_2_0_clk = %d\n", cycle_2_0_clk);
 643         debug("cycle_3_0_clk = %d\n", cycle_3_0_clk);
 644         debug("cycle_4_0_clk = %d\n", cycle_4_0_clk);
 645         debug("cycle_5_0_clk = %d\n", cycle_5_0_clk);
 646
 647         if ((cas_available & 0x04) && (sdram_freq <= cycle_2_0_clk)) {
 648                 *cas_latency = 2;
 649                 ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x2) |
 650                     DDR0_03_CASLAT_LIN_ENCODE(0x4);
 651         } else if ((cas_available & 0x08) && (sdram_freq <= cycle_3_0_clk)) {
 652                 *cas_latency = 3;
 653                 ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x3) |
 654                     DDR0_03_CASLAT_LIN_ENCODE(0x6);
 655         } else if ((cas_available & 0x10) && (sdram_freq <= cycle_4_0_clk)) {
 656                 *cas_latency = 4;
 657                 ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x4) |
 658                     DDR0_03_CASLAT_LIN_ENCODE(0x8);
 659         } else if ((cas_available & 0x20) && (sdram_freq <= cycle_5_0_clk)) {
 660                 *cas_latency = 5;
 661                 ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x5) |
 662                     DDR0_03_CASLAT_LIN_ENCODE(0xA);
 663         } else {
 664                 printf("ERROR: Cannot find a supported CAS latency with the "
 665                        "installed DIMMs.\n");
 666                 printf("Only DDR2 DIMMs with CAS latencies of 2.0, 3.0, 4.0, "
 667                        "and 5.0 are supported.\n");
 668                 printf("Make sure the PLB speed is within the supported range "
 669                        "of the DIMMs.\n");
 670                 printf("sdram_freq=%d cycle2=%d cycle3=%d cycle4=%d "
 671                        "cycle5=%d\n\n", sdram_freq, cycle_2_0_clk,
 672                        cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
 673                 spd_ddr_init_hang();
 674         }
 675         debug("CAS latency = %d\n", *cas_latency);
 676         mtsdram(DDR0_03, ddr0_03);
 677 }
 678
 679 static void program_ddr0_04(unsigned long dimm_ranks[],
 680                             unsigned char const iic0_dimm_addr[],
 681                             unsigned long num_dimm_banks,
 682                             unsigned long sdram_freq)
 683 {
 684         unsigned long dimm_num;
 685         unsigned long t_rc_ps = 0;
 686         unsigned long t_rrd_ps = 0;
 687         unsigned long t_rtp_ps = 0;
 688         unsigned long t_rc_clk;
 689         unsigned long t_rrd_clk;
 690         unsigned long t_rtp_clk;
 691
 692         /*------------------------------------------------------------------
 693          * Handle the timing.  We need to find the worst case timing of all
 694          * the dimm modules installed.
 695          *-----------------------------------------------------------------*/
 696         /* loop through all the DIMM slots on the board */
 697         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 698                 /* If a dimm is installed in a particular slot ... */
 699                 if (dimm_ranks[dimm_num]) {
 700                         unsigned long ps;
 701
 702                         /* tRC */
 703                         ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 41);
 704                         switch (spd_read(iic0_dimm_addr[dimm_num], 40) >> 4) {
 705                         case 0x1:
 706                                 ps += 250;
 707                                 break;
 708                         case 0x2:
 709                                 ps += 333;
 710                                 break;
 711                         case 0x3:
 712                                 ps += 500;
 713                                 break;
 714                         case 0x4:
 715                                 ps += 667;
 716                                 break;
 717                         case 0x5:
 718                                 ps += 750;
 719                                 break;
 720                         }
 721                         t_rc_ps = max(t_rc_ps, ps);
 722                         /* tRRD */
 723                         ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 28);
 724                         t_rrd_ps = max(t_rrd_ps, ps);
 725                         /* tRTP */
 726                         ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 38);
 727                         t_rtp_ps = max(t_rtp_ps, ps);
 728                 }
 729         }
 730         debug("t_rc_ps  = %d\n", t_rc_ps);
 731         t_rc_clk = (MULDIV64(sdram_freq, t_rc_ps, ONE_BILLION) + 999) / 1000;
 732         debug("t_rrd_ps = %d\n", t_rrd_ps);
 733         t_rrd_clk = (MULDIV64(sdram_freq, t_rrd_ps, ONE_BILLION) + 999) / 1000;
 734         debug("t_rtp_ps = %d\n", t_rtp_ps);
 735         t_rtp_clk = (MULDIV64(sdram_freq, t_rtp_ps, ONE_BILLION) + 999) / 1000;
 736         mtsdram(DDR0_04, DDR0_04_TRC_ENCODE(t_rc_clk) |
 737                 DDR0_04_TRRD_ENCODE(t_rrd_clk) |
 738                 DDR0_04_TRTP_ENCODE(t_rtp_clk));
 739 }
 740
 741 static void program_ddr0_05(unsigned long dimm_ranks[],
 742                             unsigned char const iic0_dimm_addr[],
 743                             unsigned long num_dimm_banks,
 744                             unsigned long sdram_freq)
 745 {
 746         unsigned long dimm_num;
 747         unsigned long t_rp_ps = 0;
 748         unsigned long t_ras_ps = 0;
 749         unsigned long t_rp_clk;
 750         unsigned long t_ras_clk;
 751         u32 ddr0_05 = DDR0_05_TMRD_ENCODE(0x2) | DDR0_05_TEMRS_ENCODE(0x2);
 752
 753         /*------------------------------------------------------------------
 754          * Handle the timing.  We need to find the worst case timing of all
 755          * the dimm modules installed.
 756          *-----------------------------------------------------------------*/
 757         /* loop through all the DIMM slots on the board */
 758         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 759                 /* If a dimm is installed in a particular slot ... */
 760                 if (dimm_ranks[dimm_num]) {
 761                         unsigned long ps;
 762
 763                         /* tRP */
 764                         ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 27);
 765                         t_rp_ps = max(t_rp_ps, ps);
 766                         /* tRAS */
 767                         ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 30);
 768                         t_ras_ps = max(t_ras_ps, ps);
 769                 }
 770         }
 771         debug("t_rp_ps  = %d\n", t_rp_ps);
 772         t_rp_clk = (MULDIV64(sdram_freq, t_rp_ps, ONE_BILLION) + 999) / 1000;
 773         debug("t_ras_ps = %d\n", t_ras_ps);
 774         t_ras_clk = (MULDIV64(sdram_freq, t_ras_ps, ONE_BILLION) + 999) / 1000;
 775         mtsdram(DDR0_05, ddr0_05 | DDR0_05_TRP_ENCODE(t_rp_clk) |
 776                 DDR0_05_TRAS_MIN_ENCODE(t_ras_clk));
 777 }
 778
 779 static void program_ddr0_06(unsigned long dimm_ranks[],
 780                             unsigned char const iic0_dimm_addr[],
 781                             unsigned long num_dimm_banks,
 782                             unsigned long sdram_freq)
 783 {
 784         unsigned long dimm_num;
 785         unsigned char spd_40;
 786         unsigned long t_wtr_ps = 0;
 787         unsigned long t_rfc_ps = 0;
 788         unsigned long t_wtr_clk;
 789         unsigned long t_rfc_clk;
 790         u32 ddr0_06 =
 791             DDR0_06_WRITEINTERP_ENCODE(0x1) | DDR0_06_TDLL_ENCODE(200);
 792
 793         /*------------------------------------------------------------------
 794          * Handle the timing.  We need to find the worst case timing of all
 795          * the dimm modules installed.
 796          *-----------------------------------------------------------------*/
 797         /* loop through all the DIMM slots on the board */
 798         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 799                 /* If a dimm is installed in a particular slot ... */
 800                 if (dimm_ranks[dimm_num]) {
 801                         unsigned long ps;
 802
 803                         /* tWTR */
 804                         ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 37);
 805                         t_wtr_ps = max(t_wtr_ps, ps);
 806                         /* tRFC */
 807                         ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 42);
 808                         spd_40 = spd_read(iic0_dimm_addr[dimm_num], 40);
 809                         ps += 256000 * (spd_40 & 0x01);
 810                         switch ((spd_40 & 0x0E) >> 1) {
 811                         case 0x1:
 812                                 ps += 250;
 813                                 break;
 814                         case 0x2:
 815                                 ps += 333;
 816                                 break;
 817                         case 0x3:
 818                                 ps += 500;
 819                                 break;
 820                         case 0x4:
 821                                 ps += 667;
 822                                 break;
 823                         case 0x5:
 824                                 ps += 750;
 825                                 break;
 826                         }
 827                         t_rfc_ps = max(t_rfc_ps, ps);
 828                 }
 829         }
 830         debug("t_wtr_ps = %d\n", t_wtr_ps);
 831         t_wtr_clk = (MULDIV64(sdram_freq, t_wtr_ps, ONE_BILLION) + 999) / 1000;
 832         debug("t_rfc_ps = %d\n", t_rfc_ps);
 833         t_rfc_clk = (MULDIV64(sdram_freq, t_rfc_ps, ONE_BILLION) + 999) / 1000;
 834         mtsdram(DDR0_06, ddr0_06 | DDR0_06_TWTR_ENCODE(t_wtr_clk) |
 835                 DDR0_06_TRFC_ENCODE(t_rfc_clk));
 836 }
 837
 838 static void program_ddr0_10(unsigned long dimm_ranks[], unsigned long ranks)
 839 {
 840         unsigned long csmap;
 841
 842         if (2 == ranks) {
 843                 /* Both chip selects in use */
 844                 csmap = 0x03;
 845         } else {
 846                 /* One chip select in use */
 847                 csmap = (1 == dimm_ranks[0]) ? 0x1 : 0x2;
 848         }
 849         mtsdram(DDR0_10, DDR0_10_WRITE_MODEREG_ENCODE(0x0) |
 850                 DDR0_10_CS_MAP_ENCODE(csmap) |
 851                 DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(0));
 852 }
 853
 854 static void program_ddr0_11(unsigned long sdram_freq)
 855 {
 856         unsigned long const t_xsnr_ps = 200000; /* 200 ns */
 857         unsigned long t_xsnr_clk;
 858
 859         debug("t_xsnr_ps = %d\n", t_xsnr_ps);
 860         t_xsnr_clk =
 861             (MULDIV64(sdram_freq, t_xsnr_ps, ONE_BILLION) + 999) / 1000;
 862         mtsdram(DDR0_11, DDR0_11_SREFRESH_ENCODE(0) |
 863                 DDR0_11_TXSNR_ENCODE(t_xsnr_clk) | DDR0_11_TXSR_ENCODE(200));
 864 }
 865
 866 static void program_ddr0_22(unsigned long dimm_ranks[],
 867                             unsigned char const iic0_dimm_addr[],
 868                             unsigned long num_dimm_banks, unsigned long width)
 869 {
 870 #if defined(CONFIG_DDR_ECC)
 871         unsigned long dimm_num;
 872         unsigned long ecc_available = width >= 64;
 873         u32 ddr0_22 = DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) |
 874             DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) |
 875             DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS);
 876
 877         /* loop through all the DIMM slots on the board */
 878         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 879                 /* If a dimm is installed in a particular slot ... */
 880                 if (dimm_ranks[dimm_num]) {
 881                         /* Check for ECC */
 882                         if (0 == (spd_read(iic0_dimm_addr[dimm_num], 11) &
 883                                   0x02)) {
 884                                 ecc_available = FALSE;
 885                         }
 886                 }
 887         }
 888         if (ecc_available) {
 889                 debug("ECC found on all DIMMs present\n");
 890                 mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x3));
 891         } else {
 892                 debug("ECC not found on some or all DIMMs present\n");
 893                 mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x0));
 894         }
 895 #else
 896         mtsdram(DDR0_22, DDR0_22_CTRL_RAW_ENCODE(0x0) |
 897                 DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) |
 898                 DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) |
 899                 DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS));
 900 #endif /* defined(CONFIG_DDR_ECC) */
 901 }
 902
 903 static void program_ddr0_24(unsigned long ranks)
 904 {
 905         u32 ddr0_24 = DDR0_24_RTT_PAD_TERMINATION_ENCODE(0x1) | /* 75 ohm */
 906             DDR0_24_ODT_RD_MAP_CS1_ENCODE(0x0);
 907
 908         if (2 == ranks) {
 909                 /* Both chip selects in use */
 910                 ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x1) |
 911                     DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x2);
 912         } else {
 913                 /* One chip select in use */
 914                 /* One of the two fields added to ddr0_24 is a "don't care" */
 915                 ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x2) |
 916                     DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x1);
 917         }
 918         mtsdram(DDR0_24, ddr0_24);
 919 }
 920
 921 static void program_ddr0_26(unsigned long sdram_freq)
 922 {
 923         unsigned long const t_ref_ps = 7800000; /* 7.8 us. refresh */
 924         /* TODO: check definition of tRAS_MAX */
 925         unsigned long const t_ras_max_ps = 9 * t_ref_ps;
 926         unsigned long t_ras_max_clk;
 927         unsigned long t_ref_clk;
 928
 929         /* Round down t_ras_max_clk and t_ref_clk */
 930         debug("t_ras_max_ps = %d\n", t_ras_max_ps);
 931         t_ras_max_clk = MULDIV64(sdram_freq, t_ras_max_ps, ONE_BILLION) / 1000;
 932         debug("t_ref_ps     = %d\n", t_ref_ps);
 933         t_ref_clk = MULDIV64(sdram_freq, t_ref_ps, ONE_BILLION) / 1000;
 934         mtsdram(DDR0_26, DDR0_26_TRAS_MAX_ENCODE(t_ras_max_clk) |
 935                 DDR0_26_TREF_ENCODE(t_ref_clk));
 936 }
 937
 938 static void program_ddr0_27(unsigned long sdram_freq)
 939 {
 940         unsigned long const t_init_ps = 200000000;      /* 200 us. init */
 941         unsigned long t_init_clk;
 942
 943         debug("t_init_ps = %d\n", t_init_ps);
 944         t_init_clk =
 945             (MULDIV64(sdram_freq, t_init_ps, ONE_BILLION) + 999) / 1000;
 946         mtsdram(DDR0_27, DDR0_27_EMRS_DATA_ENCODE(0x0000) |
 947                 DDR0_27_TINIT_ENCODE(t_init_clk));
 948 }
 949
 950 static void program_ddr0_43(unsigned long dimm_ranks[],
 951                             unsigned char const iic0_dimm_addr[],
 952                             unsigned long num_dimm_banks,
 953                             unsigned long sdram_freq,
 954                             unsigned long cols, unsigned long banks)
 955 {
 956         unsigned long dimm_num;
 957         unsigned long t_wr_ps = 0;
 958         unsigned long t_wr_clk;
 959         u32 ddr0_43 = DDR0_43_APREBIT_ENCODE(10) |
 960             DDR0_43_COLUMN_SIZE_ENCODE(12 - cols) |
 961             DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0);
 962
 963         /*------------------------------------------------------------------
 964          * Handle the timing.  We need to find the worst case timing of all
 965          * the dimm modules installed.
 966          *-----------------------------------------------------------------*/
 967         /* loop through all the DIMM slots on the board */
 968         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 969                 /* If a dimm is installed in a particular slot ... */
 970                 if (dimm_ranks[dimm_num]) {
 971                         unsigned long ps;
 972
 973                         ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 36);
 974                         t_wr_ps = max(t_wr_ps, ps);
 975                 }
 976         }
 977         debug("t_wr_ps = %d\n", t_wr_ps);
 978         t_wr_clk = (MULDIV64(sdram_freq, t_wr_ps, ONE_BILLION) + 999) / 1000;
 979         mtsdram(DDR0_43, ddr0_43 | DDR0_43_TWR_ENCODE(t_wr_clk));
 980 }
 981
 982 static void program_ddr0_44(unsigned long dimm_ranks[],
 983                             unsigned char const iic0_dimm_addr[],
 984                             unsigned long num_dimm_banks,
 985                             unsigned long sdram_freq)
 986 {
 987         unsigned long dimm_num;
 988         unsigned long t_rcd_ps = 0;
 989         unsigned long t_rcd_clk;
 990
 991         /*------------------------------------------------------------------
 992          * Handle the timing.  We need to find the worst case timing of all
 993          * the dimm modules installed.
 994          *-----------------------------------------------------------------*/
 995         /* loop through all the DIMM slots on the board */
 996         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 997                 /* If a dimm is installed in a particular slot ... */
 998                 if (dimm_ranks[dimm_num]) {
 999                         unsigned long ps;
1000
1001                         ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 29);
1002                         t_rcd_ps = max(t_rcd_ps, ps);
1003                 }
1004         }
1005         debug("t_rcd_ps = %d\n", t_rcd_ps);
1006         t_rcd_clk = (MULDIV64(sdram_freq, t_rcd_ps, ONE_BILLION) + 999) / 1000;
1007         mtsdram(DDR0_44, DDR0_44_TRCD_ENCODE(t_rcd_clk));
1008 }
1009
1010 /*-----------------------------------------------------------------------------+
1011  * initdram.  Initializes the 440EPx/GPx DDR SDRAM controller.
1012  * Note: This routine runs from flash with a stack set up in the chip's
1013  * sram space.  It is important that the routine does not require .sbss, .bss or
1014  * .data sections.  It also cannot call routines that require these sections.
1015  *-----------------------------------------------------------------------------*/
1016 /*-----------------------------------------------------------------------------
1017  * Function:     initdram
1018  * Description:  Configures SDRAM memory banks for DDR operation.
1019  *               Auto Memory Configuration option reads the DDR SDRAM EEPROMs
1020  *               via the IIC bus and then configures the DDR SDRAM memory
1021  *               banks appropriately. If Auto Memory Configuration is
1022  *               not used, it is assumed that no DIMM is plugged
1023  *-----------------------------------------------------------------------------*/
1024 long int initdram(int board_type)
1025 {
1026         unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
1027         unsigned long dimm_ranks[MAXDIMMS];
1028         unsigned long ranks;
1029         unsigned long rows;
1030         unsigned long banks;
1031         unsigned long cols;
1032         unsigned long width;
1033         unsigned long const sdram_freq = get_bus_freq(0);
1034         unsigned long const num_dimm_banks = sizeof(iic0_dimm_addr);    /* on board dimm banks */
1035         unsigned long cas_latency = 0;  /* to quiet initialization warning */
1036         unsigned long dram_size;
1037
1038         debug("\nEntering initdram()\n");
1039
1040         /*------------------------------------------------------------------
1041          * Stop the DDR-SDRAM controller.
1042          *-----------------------------------------------------------------*/
1043         mtsdram(DDR0_02, DDR0_02_START_ENCODE(0));
1044
1045         /*
1046          * Make sure I2C controller is initialized
1047          * before continuing.
1048          */
1049         /* switch to correct I2C bus */
1050         I2C_SET_BUS(CFG_SPD_BUS_NUM);
1051         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
1052
1053         /*------------------------------------------------------------------
1054          * Clear out the serial presence detect buffers.
1055          * Perform IIC reads from the dimm.  Fill in the spds.
1056          * Check to see if the dimm slots are populated
1057          *-----------------------------------------------------------------*/
1058         get_spd_info(dimm_ranks, &ranks, iic0_dimm_addr, num_dimm_banks);
1059
1060         /*------------------------------------------------------------------
1061          * Check the frequency supported for the dimms plugged.
1062          *-----------------------------------------------------------------*/
1063         check_frequency(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1064
1065         /*------------------------------------------------------------------
1066          * Check and get size information.
1067          *-----------------------------------------------------------------*/
1068         get_dimm_size(dimm_ranks, iic0_dimm_addr, num_dimm_banks, &rows, &banks,
1069                       &cols, &width);
1070
1071         /*------------------------------------------------------------------
1072          * Check the voltage type for the dimms plugged.
1073          *-----------------------------------------------------------------*/
1074         check_voltage_type(dimm_ranks, iic0_dimm_addr, num_dimm_banks);
1075
1076         /*------------------------------------------------------------------
1077          * Program registers for SDRAM controller.
1078          *-----------------------------------------------------------------*/
1079         mtsdram(DDR0_00, DDR0_00_DLL_INCREMENT_ENCODE(0x19) |
1080                 DDR0_00_DLL_START_POINT_DECODE(0x0A));
1081
1082         mtsdram(DDR0_01, DDR0_01_PLB0_DB_CS_LOWER_ENCODE(0x01) |
1083                 DDR0_01_PLB0_DB_CS_UPPER_ENCODE(0x00) |
1084                 DDR0_01_INT_MASK_ENCODE(0xFF));
1085
1086         program_ddr0_03(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,
1087                         rows, &cas_latency);
1088
1089         program_ddr0_04(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1090
1091         program_ddr0_05(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1092
1093         program_ddr0_06(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1094
1095         /*
1096          * TODO: tFAW not found in SPD.  Value of 13 taken from Sequoia
1097          * board SDRAM, but may be overly conservative.
1098          */
1099         mtsdram(DDR0_07, DDR0_07_NO_CMD_INIT_ENCODE(0) |
1100                 DDR0_07_TFAW_ENCODE(13) |
1101                 DDR0_07_AUTO_REFRESH_MODE_ENCODE(1) |
1102                 DDR0_07_AREFRESH_ENCODE(0));
1103
1104         mtsdram(DDR0_08, DDR0_08_WRLAT_ENCODE(cas_latency - 1) |
1105                 DDR0_08_TCPD_ENCODE(200) | DDR0_08_DQS_N_EN_ENCODE(0) |
1106                 DDR0_08_DDRII_ENCODE(1));
1107
1108         mtsdram(DDR0_09, DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(0x00) |
1109                 DDR0_09_RTT_0_ENCODE(0x1) |
1110                 DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(0x1D) |
1111                 DDR0_09_WR_DQS_SHIFT_ENCODE(DQS_OUT_SHIFT - 0x20));
1112
1113         program_ddr0_10(dimm_ranks, ranks);
1114
1115         program_ddr0_11(sdram_freq);
1116
1117         mtsdram(DDR0_12, DDR0_12_TCKE_ENCODE(3));
1118
1119         mtsdram(DDR0_14, DDR0_14_DLL_BYPASS_MODE_ENCODE(0) |
1120                 DDR0_14_REDUC_ENCODE(width <= 40 ? 1 : 0) |
1121                 DDR0_14_REG_DIMM_ENABLE_ENCODE(0));
1122
1123         mtsdram(DDR0_17, DDR0_17_DLL_DQS_DELAY_0_ENCODE(DLL_DQS_DELAY));
1124
1125         mtsdram(DDR0_18, DDR0_18_DLL_DQS_DELAY_4_ENCODE(DLL_DQS_DELAY) |
1126                 DDR0_18_DLL_DQS_DELAY_3_ENCODE(DLL_DQS_DELAY) |
1127                 DDR0_18_DLL_DQS_DELAY_2_ENCODE(DLL_DQS_DELAY) |
1128                 DDR0_18_DLL_DQS_DELAY_1_ENCODE(DLL_DQS_DELAY));
1129
1130         mtsdram(DDR0_19, DDR0_19_DLL_DQS_DELAY_8_ENCODE(DLL_DQS_DELAY) |
1131                 DDR0_19_DLL_DQS_DELAY_7_ENCODE(DLL_DQS_DELAY) |
1132                 DDR0_19_DLL_DQS_DELAY_6_ENCODE(DLL_DQS_DELAY) |
1133                 DDR0_19_DLL_DQS_DELAY_5_ENCODE(DLL_DQS_DELAY));
1134
1135         mtsdram(DDR0_20, DDR0_20_DLL_DQS_BYPASS_3_ENCODE(DLL_DQS_BYPASS) |
1136                 DDR0_20_DLL_DQS_BYPASS_2_ENCODE(DLL_DQS_BYPASS) |
1137                 DDR0_20_DLL_DQS_BYPASS_1_ENCODE(DLL_DQS_BYPASS) |
1138                 DDR0_20_DLL_DQS_BYPASS_0_ENCODE(DLL_DQS_BYPASS));
1139
1140         mtsdram(DDR0_21, DDR0_21_DLL_DQS_BYPASS_7_ENCODE(DLL_DQS_BYPASS) |
1141                 DDR0_21_DLL_DQS_BYPASS_6_ENCODE(DLL_DQS_BYPASS) |
1142                 DDR0_21_DLL_DQS_BYPASS_5_ENCODE(DLL_DQS_BYPASS) |
1143                 DDR0_21_DLL_DQS_BYPASS_4_ENCODE(DLL_DQS_BYPASS));
1144
1145         program_ddr0_22(dimm_ranks, iic0_dimm_addr, num_dimm_banks, width);
1146
1147         mtsdram(DDR0_23, DDR0_23_ODT_RD_MAP_CS0_ENCODE(0x0) |
1148                 DDR0_23_FWC_ENCODE(0));
1149
1150         program_ddr0_24(ranks);
1151
1152         program_ddr0_26(sdram_freq);
1153
1154         program_ddr0_27(sdram_freq);
1155
1156         mtsdram(DDR0_28, DDR0_28_EMRS3_DATA_ENCODE(0x0000) |
1157                 DDR0_28_EMRS2_DATA_ENCODE(0x0000));
1158
1159         mtsdram(DDR0_31, DDR0_31_XOR_CHECK_BITS_ENCODE(0x0000));
1160
1161         mtsdram(DDR0_42, DDR0_42_ADDR_PINS_DECODE(14 - rows) |
1162                 DDR0_42_CASLAT_LIN_GATE_ENCODE(2 * cas_latency));
1163
1164         program_ddr0_43(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,
1165                         cols, banks);
1166
1167         program_ddr0_44(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1168
1169         denali_sdram_register_dump();
1170
1171         dram_size = (width >= 64) ? 8 : 4;
1172         dram_size *= 1 << cols;
1173         dram_size *= banks;
1174         dram_size *= 1 << rows;
1175         dram_size *= ranks;
1176         debug("dram_size = %lu\n", dram_size);
1177
1178         /* Start the SDRAM controler */
1179         mtsdram(DDR0_02, DDR0_02_START_ENCODE(1));
1180         denali_wait_for_dlllock();
1181
1182 #if defined(CONFIG_DDR_DATA_EYE)
1183         /*
1184          * Map the first 1 MiB of memory in the TLB, and perform the data eye
1185          * search.
1186          */
1187         program_tlb(0, CFG_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE);
1188         denali_core_search_data_eye();
1189         denali_sdram_register_dump();
1190         remove_tlb(CFG_SDRAM_BASE, TLB_1MB_SIZE);
1191 #endif
1192
1193 #if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC)
1194         program_tlb(0, CFG_SDRAM_BASE, dram_size, 0);
1195         sync();
1196         /* Zero the memory */
1197         debug("Zeroing SDRAM...");
1198 #if defined(CFG_MEM_TOP_HIDE)
1199         dcbz_area(CFG_SDRAM_BASE, dram_size - CFG_MEM_TOP_HIDE);
1200 #else
1201 #error Please define CFG_MEM_TOP_HIDE (see README) in your board config file
1202 #endif
1203         /* Write modified dcache lines back to memory */
1204         clean_dcache_range(CFG_SDRAM_BASE, CFG_SDRAM_BASE + dram_size - CFG_MEM_TOP_HIDE);
1205         debug("Completed\n");
1206         sync();
1207         remove_tlb(CFG_SDRAM_BASE, dram_size);
1208
1209 #if defined(CONFIG_DDR_ECC)
1210         /*
1211          * If ECC is enabled, clear and enable interrupts
1212          */
1213         if (is_ecc_enabled()) {
1214                 u32 val;
1215
1216                 sync();
1217                 /* Clear error status */
1218                 mfsdram(DDR0_00, val);
1219                 mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
1220                 /* Set 'int_mask' parameter to functionnal value */
1221                 mfsdram(DDR0_01, val);
1222                 mtsdram(DDR0_01, (val & ~DDR0_01_INT_MASK_MASK) |
1223                         DDR0_01_INT_MASK_ALL_OFF);
1224 #if defined(CONFIG_DDR_DATA_EYE)
1225                 /*
1226                  * Running denali_core_search_data_eye() when ECC is enabled
1227                  * causes non-ECC machine checks.  This clears them.
1228                  */
1229                 print_mcsr();
1230                 mtspr(SPRN_MCSR, mfspr(SPRN_MCSR));
1231                 print_mcsr();
1232 #endif
1233                 sync();
1234         }
1235 #endif /* defined(CONFIG_DDR_ECC) */
1236 #endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */
1237
1238         program_tlb(0, CFG_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
1239         return dram_size;
1240 }
1241
1242 void board_add_ram_info(int use_default)
1243 {
1244         u32 val;
1245
1246         printf(" (ECC");
1247         if (!is_ecc_enabled()) {
1248                 printf(" not");
1249         }
1250         printf(" enabled, %d MHz", (2 * get_bus_freq(0)) / 1000000);
1251
1252         mfsdram(DDR0_03, val);
1253         printf(", CL%d)", DDR0_03_CASLAT_LIN_DECODE(val) >> 1);
1254 }
1255 #endif /* CONFIG_SPD_EEPROM */