2 * (C) Copyright 2000-2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <ppc4xx_enet.h>
27 #include <asm/processor.h>
31 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
32 DECLARE_GLOBAL_DATA_PTR;
35 #ifdef CFG_INIT_DCACHE_CS
36 # if (CFG_INIT_DCACHE_CS == 0)
39 # if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
40 # define PBxAP_VAL CFG_EBC_PB0AP
41 # define PBxCR_VAL CFG_EBC_PB0CR
44 # if (CFG_INIT_DCACHE_CS == 1)
47 # if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
48 # define PBxAP_VAL CFG_EBC_PB1AP
49 # define PBxCR_VAL CFG_EBC_PB1CR
52 # if (CFG_INIT_DCACHE_CS == 2)
55 # if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
56 # define PBxAP_VAL CFG_EBC_PB2AP
57 # define PBxCR_VAL CFG_EBC_PB2CR
60 # if (CFG_INIT_DCACHE_CS == 3)
63 # if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
64 # define PBxAP_VAL CFG_EBC_PB3AP
65 # define PBxCR_VAL CFG_EBC_PB3CR
68 # if (CFG_INIT_DCACHE_CS == 4)
71 # if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
72 # define PBxAP_VAL CFG_EBC_PB4AP
73 # define PBxCR_VAL CFG_EBC_PB4CR
76 # if (CFG_INIT_DCACHE_CS == 5)
79 # if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
80 # define PBxAP_VAL CFG_EBC_PB5AP
81 # define PBxCR_VAL CFG_EBC_PB5CR
84 # if (CFG_INIT_DCACHE_CS == 6)
87 # if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
88 # define PBxAP_VAL CFG_EBC_PB6AP
89 # define PBxCR_VAL CFG_EBC_PB6CR
92 # if (CFG_INIT_DCACHE_CS == 7)
95 # if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
96 # define PBxAP_VAL CFG_EBC_PB7AP
97 # define PBxCR_VAL CFG_EBC_PB7CR
100 #endif /* CFG_INIT_DCACHE_CS */
103 * Breath some life into the CPU...
105 * Set up the memory map,
106 * initialize a bunch of registers
111 #if defined(CONFIG_WATCHDOG)
115 #if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE)
117 * GPIO0 setup (select GPIO or alternate function)
119 #if defined(CFG_GPIO0_OR)
120 out32(GPIO0_OR, CFG_GPIO0_OR); /* set initial state of output pins */
122 #if defined(CFG_GPIO0_ODR)
123 out32(GPIO0_ODR, CFG_GPIO0_ODR); /* open-drain select */
125 out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
126 out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
127 out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
128 out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
129 out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
130 out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
131 #if defined(CFG_GPIO0_ISR2H)
132 out32(GPIO0_ISR2H, CFG_GPIO0_ISR2H);
133 out32(GPIO0_ISR2L, CFG_GPIO0_ISR2L);
135 #if defined (CFG_GPIO0_TCR)
136 out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
139 #if defined (CONFIG_450EP)
141 * Set EMAC noise filter bits
143 mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
144 #endif /* CONFIG_405EP */
145 #endif /* CONFIG_405EP */
147 #if defined(CFG_4xx_GPIO_TABLE)
148 gpio_set_chip_configuration();
149 #endif /* CFG_4xx_GPIO_TABLE */
152 * External Bus Controller (EBC) Setup
154 #if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
155 #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
156 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
157 defined(CONFIG_405EX) || defined(CONFIG_405))
159 * Move the next instructions into icache, since these modify the flash
160 * we are running from!
162 asm volatile(" bl 0f" ::: "lr");
163 asm volatile("0: mflr 3" ::: "r3");
164 asm volatile(" addi 4, 0, 14" ::: "r4");
165 asm volatile(" mtctr 4" ::: "ctr");
166 asm volatile("1: icbt 0, 3");
167 asm volatile(" addi 3, 3, 32" ::: "r3");
168 asm volatile(" bdnz 1b" ::: "ctr", "cr0");
169 asm volatile(" addis 3, 0, 0x0" ::: "r3");
170 asm volatile(" ori 3, 3, 0xA000" ::: "r3");
171 asm volatile(" mtctr 3" ::: "ctr");
172 asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
175 mtebc(pb0ap, CFG_EBC_PB0AP);
176 mtebc(pb0cr, CFG_EBC_PB0CR);
179 #if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR) && !(CFG_INIT_DCACHE_CS == 1))
180 mtebc(pb1ap, CFG_EBC_PB1AP);
181 mtebc(pb1cr, CFG_EBC_PB1CR);
184 #if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR) && !(CFG_INIT_DCACHE_CS == 2))
185 mtebc(pb2ap, CFG_EBC_PB2AP);
186 mtebc(pb2cr, CFG_EBC_PB2CR);
189 #if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR) && !(CFG_INIT_DCACHE_CS == 3))
190 mtebc(pb3ap, CFG_EBC_PB3AP);
191 mtebc(pb3cr, CFG_EBC_PB3CR);
194 #if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
195 mtebc(pb4ap, CFG_EBC_PB4AP);
196 mtebc(pb4cr, CFG_EBC_PB4CR);
199 #if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR) && !(CFG_INIT_DCACHE_CS == 5))
200 mtebc(pb5ap, CFG_EBC_PB5AP);
201 mtebc(pb5cr, CFG_EBC_PB5CR);
204 #if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR) && !(CFG_INIT_DCACHE_CS == 6))
205 mtebc(pb6ap, CFG_EBC_PB6AP);
206 mtebc(pb6cr, CFG_EBC_PB6CR);
209 #if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR) && !(CFG_INIT_DCACHE_CS == 7))
210 mtebc(pb7ap, CFG_EBC_PB7AP);
211 mtebc(pb7cr, CFG_EBC_PB7CR);
214 #if defined (CFG_EBC_CFG)
215 mtebc(EBC0_CFG, CFG_EBC_CFG);
218 #if defined(CONFIG_WATCHDOG)
220 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
221 val |= 0xb8000000; /* generate system reset after 1.34 seconds */
222 #elif defined(CONFIG_440EPX)
223 val |= 0xb0000000; /* generate system reset after 1.34 seconds */
225 val |= 0xf0000000; /* generate system reset after 2.684 seconds */
227 #if defined(CFG_4xx_RESET_TYPE)
228 val &= ~0x30000000; /* clear WRC bits */
229 val |= CFG_4xx_RESET_TYPE << 28; /* set board specific WRC type */
234 val |= 0x80000000; /* enable watchdog timer */
237 reset_4xx_watchdog();
238 #endif /* CONFIG_WATCHDOG */
242 * initialize higher level parts of CPU like time base and timers
244 int cpu_init_r (void)
246 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
249 #if defined(CONFIG_405GP)
250 uint pvr = get_pvr();
253 #ifdef CFG_INIT_DCACHE_CS
255 * Flush and invalidate dcache, then disable CS for temporary stack.
256 * Afterwards, this CS can be used for other purposes
258 dcache_disable(); /* flush and invalidate dcache */
260 mtebc(PBxCR, 0); /* disable CS for temporary stack */
262 #if (defined(PBxAP_VAL) && defined(PBxCR_VAL))
264 * Write new value into CS register
266 mtebc(PBxAP, PBxAP_VAL);
267 mtebc(PBxCR, PBxCR_VAL);
269 #endif /* CFG_INIT_DCACHE_CS */
272 * Write Ethernetaddress into on-chip register
275 reg |= bd->bi_enetaddr[0]; /* set high address */
277 reg |= bd->bi_enetaddr[1];
278 out32 (EMAC_IAH, reg);
281 reg |= bd->bi_enetaddr[2]; /* set low address */
283 reg |= bd->bi_enetaddr[3];
285 reg |= bd->bi_enetaddr[4];
287 reg |= bd->bi_enetaddr[5];
288 out32 (EMAC_IAL, reg);
290 #if defined(CONFIG_405GP)
292 * Set edge conditioning circuitry on PPC405GPr
293 * for compatibility to existing PPC405GP designs.
295 if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
296 mtdcr(ecr, 0x60606000);
298 #endif /* defined(CONFIG_405GP) */
299 #endif /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */