2 * (C) Copyright 2000-2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <ppc4xx_enet.h>
27 #include <asm/processor.h>
31 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
32 DECLARE_GLOBAL_DATA_PTR;
35 #ifdef CFG_INIT_DCACHE_CS
36 # if (CFG_INIT_DCACHE_CS == 0)
39 # if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
40 # define PBxAP_VAL CFG_EBC_PB0AP
41 # define PBxCR_VAL CFG_EBC_PB0CR
44 # if (CFG_INIT_DCACHE_CS == 1)
47 # if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
48 # define PBxAP_VAL CFG_EBC_PB1AP
49 # define PBxCR_VAL CFG_EBC_PB1CR
52 # if (CFG_INIT_DCACHE_CS == 2)
55 # if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
56 # define PBxAP_VAL CFG_EBC_PB2AP
57 # define PBxCR_VAL CFG_EBC_PB2CR
60 # if (CFG_INIT_DCACHE_CS == 3)
63 # if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
64 # define PBxAP_VAL CFG_EBC_PB3AP
65 # define PBxCR_VAL CFG_EBC_PB3CR
68 # if (CFG_INIT_DCACHE_CS == 4)
71 # if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
72 # define PBxAP_VAL CFG_EBC_PB4AP
73 # define PBxCR_VAL CFG_EBC_PB4CR
76 # if (CFG_INIT_DCACHE_CS == 5)
79 # if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
80 # define PBxAP_VAL CFG_EBC_PB5AP
81 # define PBxCR_VAL CFG_EBC_PB5CR
84 # if (CFG_INIT_DCACHE_CS == 6)
87 # if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
88 # define PBxAP_VAL CFG_EBC_PB6AP
89 # define PBxCR_VAL CFG_EBC_PB6CR
92 # if (CFG_INIT_DCACHE_CS == 7)
95 # if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
96 # define PBxAP_VAL CFG_EBC_PB7AP
97 # define PBxCR_VAL CFG_EBC_PB7CR
100 #endif /* CFG_INIT_DCACHE_CS */
102 #ifndef CFG_PLL_RECONFIG
103 #define CFG_PLL_RECONFIG 0
106 void reconfigure_pll(u32 new_cpu_freq)
108 #if defined(CONFIG_440EPX)
109 int reset_needed = 0;
111 u32 prbdv0, target_prbdv0, /* CLK_PRIMBD */
112 fwdva, target_fwdva, fwdvb, target_fwdvb, /* CLK_PLLD */
113 fbdv, target_fbdv, lfbdv, target_lfbdv,
114 perdv0, target_perdv0, /* CLK_PERD */
115 spcid0, target_spcid0; /* CLK_SPCID */
117 /* Reconfigure clocks if necessary.
118 * See PPC440EPx User's Manual, sections 8.2 and 14 */
119 if (new_cpu_freq == 667) {
128 mfcpr(clk_primbd, reg);
129 temp = (reg & PRBDV_MASK) >> 24;
130 prbdv0 = temp ? temp : 8;
131 if (prbdv0 != target_prbdv0) {
133 reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24);
134 mtcpr(clk_primbd, reg);
138 mfcpr(clk_plld, reg);
140 temp = (reg & PLLD_FWDVA_MASK) >> 16;
141 fwdva = temp ? temp : 16;
143 temp = (reg & PLLD_FWDVB_MASK) >> 8;
144 fwdvb = temp ? temp : 8;
146 temp = (reg & PLLD_FBDV_MASK) >> 24;
147 fbdv = temp ? temp : 32;
149 temp = (reg & PLLD_LFBDV_MASK);
150 lfbdv = temp ? temp : 64;
152 if (fwdva != target_fwdva || fbdv != target_fbdv || lfbdv != target_lfbdv) {
153 reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
154 PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
155 reg |= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) |
156 ((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) |
157 ((target_fbdv == 32 ? 0 : target_fbdv) << 24) |
158 (target_lfbdv == 64 ? 0 : target_lfbdv);
159 mtcpr(clk_plld, reg);
163 mfcpr(clk_perd, reg);
164 perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24;
165 if (perdv0 != target_perdv0) {
166 reg &= ~CPR0_PERD_PERDV0_MASK;
167 reg |= (target_perdv0 << 24);
168 mtcpr(clk_perd, reg);
172 mfcpr(clk_spcid, reg);
173 temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24;
174 spcid0 = temp ? temp : 4;
175 if (spcid0 != target_spcid0) {
176 reg &= ~CPR0_SPCID_SPCIDV0_MASK;
177 reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24);
178 mtcpr(clk_spcid, reg);
182 /* Set reload inhibit so configuration will persist across
183 * processor resets */
184 mfcpr(clk_icfg, reg);
185 reg &= ~CPR0_ICFG_RLI_MASK;
187 mtcpr(clk_icfg, reg);
190 /* Reset processor if configuration changed */
192 __asm__ __volatile__ ("sync; isync");
193 mtspr(dbcr0, 0x20000000);
199 * Breath some life into the CPU...
201 * Reconfigure PLL if necessary,
202 * set up the memory map,
203 * initialize a bunch of registers
208 #if defined(CONFIG_WATCHDOG)
211 reconfigure_pll(CFG_PLL_RECONFIG);
213 #if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE)
215 * GPIO0 setup (select GPIO or alternate function)
217 #if defined(CFG_GPIO0_OR)
218 out32(GPIO0_OR, CFG_GPIO0_OR); /* set initial state of output pins */
220 #if defined(CFG_GPIO0_ODR)
221 out32(GPIO0_ODR, CFG_GPIO0_ODR); /* open-drain select */
223 out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
224 out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
225 out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
226 out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
227 out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
228 out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
229 #if defined(CFG_GPIO0_ISR2H)
230 out32(GPIO0_ISR2H, CFG_GPIO0_ISR2H);
231 out32(GPIO0_ISR2L, CFG_GPIO0_ISR2L);
233 #if defined (CFG_GPIO0_TCR)
234 out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
236 #endif /* CONFIG_405EP ... && !CFG_4xx_GPIO_TABLE */
238 #if defined (CONFIG_405EP)
240 * Set EMAC noise filter bits
242 mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
245 * Enable the internal PCI arbiter
247 mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
248 #endif /* CONFIG_405EP */
250 #if defined(CFG_4xx_GPIO_TABLE)
251 gpio_set_chip_configuration();
252 #endif /* CFG_4xx_GPIO_TABLE */
255 * External Bus Controller (EBC) Setup
257 #if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
258 #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
259 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
260 defined(CONFIG_405EX) || defined(CONFIG_405))
262 * Move the next instructions into icache, since these modify the flash
263 * we are running from!
265 asm volatile(" bl 0f" ::: "lr");
266 asm volatile("0: mflr 3" ::: "r3");
267 asm volatile(" addi 4, 0, 14" ::: "r4");
268 asm volatile(" mtctr 4" ::: "ctr");
269 asm volatile("1: icbt 0, 3");
270 asm volatile(" addi 3, 3, 32" ::: "r3");
271 asm volatile(" bdnz 1b" ::: "ctr", "cr0");
272 asm volatile(" addis 3, 0, 0x0" ::: "r3");
273 asm volatile(" ori 3, 3, 0xA000" ::: "r3");
274 asm volatile(" mtctr 3" ::: "ctr");
275 asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
278 mtebc(pb0ap, CFG_EBC_PB0AP);
279 mtebc(pb0cr, CFG_EBC_PB0CR);
282 #if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR) && !(CFG_INIT_DCACHE_CS == 1))
283 mtebc(pb1ap, CFG_EBC_PB1AP);
284 mtebc(pb1cr, CFG_EBC_PB1CR);
287 #if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR) && !(CFG_INIT_DCACHE_CS == 2))
288 mtebc(pb2ap, CFG_EBC_PB2AP);
289 mtebc(pb2cr, CFG_EBC_PB2CR);
292 #if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR) && !(CFG_INIT_DCACHE_CS == 3))
293 mtebc(pb3ap, CFG_EBC_PB3AP);
294 mtebc(pb3cr, CFG_EBC_PB3CR);
297 #if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
298 mtebc(pb4ap, CFG_EBC_PB4AP);
299 mtebc(pb4cr, CFG_EBC_PB4CR);
302 #if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR) && !(CFG_INIT_DCACHE_CS == 5))
303 mtebc(pb5ap, CFG_EBC_PB5AP);
304 mtebc(pb5cr, CFG_EBC_PB5CR);
307 #if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR) && !(CFG_INIT_DCACHE_CS == 6))
308 mtebc(pb6ap, CFG_EBC_PB6AP);
309 mtebc(pb6cr, CFG_EBC_PB6CR);
312 #if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR) && !(CFG_INIT_DCACHE_CS == 7))
313 mtebc(pb7ap, CFG_EBC_PB7AP);
314 mtebc(pb7cr, CFG_EBC_PB7CR);
317 #if defined (CFG_EBC_CFG)
318 mtebc(EBC0_CFG, CFG_EBC_CFG);
321 #if defined(CONFIG_WATCHDOG)
323 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
324 val |= 0xb8000000; /* generate system reset after 1.34 seconds */
325 #elif defined(CONFIG_440EPX)
326 val |= 0xb0000000; /* generate system reset after 1.34 seconds */
328 val |= 0xf0000000; /* generate system reset after 2.684 seconds */
330 #if defined(CFG_4xx_RESET_TYPE)
331 val &= ~0x30000000; /* clear WRC bits */
332 val |= CFG_4xx_RESET_TYPE << 28; /* set board specific WRC type */
337 val |= 0x80000000; /* enable watchdog timer */
340 reset_4xx_watchdog();
341 #endif /* CONFIG_WATCHDOG */
345 * initialize higher level parts of CPU like time base and timers
347 int cpu_init_r (void)
349 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
352 #if defined(CONFIG_405GP)
353 uint pvr = get_pvr();
356 #ifdef CFG_INIT_DCACHE_CS
358 * Flush and invalidate dcache, then disable CS for temporary stack.
359 * Afterwards, this CS can be used for other purposes
361 dcache_disable(); /* flush and invalidate dcache */
363 mtebc(PBxCR, 0); /* disable CS for temporary stack */
365 #if (defined(PBxAP_VAL) && defined(PBxCR_VAL))
367 * Write new value into CS register
369 mtebc(PBxAP, PBxAP_VAL);
370 mtebc(PBxCR, PBxCR_VAL);
372 #endif /* CFG_INIT_DCACHE_CS */
375 * Write Ethernetaddress into on-chip register
378 reg |= bd->bi_enetaddr[0]; /* set high address */
380 reg |= bd->bi_enetaddr[1];
381 out32 (EMAC_IAH, reg);
384 reg |= bd->bi_enetaddr[2]; /* set low address */
386 reg |= bd->bi_enetaddr[3];
388 reg |= bd->bi_enetaddr[4];
390 reg |= bd->bi_enetaddr[5];
391 out32 (EMAC_IAL, reg);
393 #if defined(CONFIG_405GP)
395 * Set edge conditioning circuitry on PPC405GPr
396 * for compatibility to existing PPC405GP designs.
398 if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
399 mtdcr(ecr, 0x60606000);
401 #endif /* defined(CONFIG_405GP) */
402 #endif /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */