2 * (C) Copyright 2000-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <ppc4xx_enet.h>
27 #include <asm/processor.h>
30 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
31 DECLARE_GLOBAL_DATA_PTR;
34 #ifdef CFG_INIT_DCACHE_CS
35 # if (CFG_INIT_DCACHE_CS == 0)
38 # if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
39 # define PBxAP_VAL CFG_EBC_PB0AP
40 # define PBxCR_VAL CFG_EBC_PB0CR
43 # if (CFG_INIT_DCACHE_CS == 1)
46 # if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
47 # define PBxAP_VAL CFG_EBC_PB1AP
48 # define PBxCR_VAL CFG_EBC_PB1CR
51 # if (CFG_INIT_DCACHE_CS == 2)
54 # if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
55 # define PBxAP_VAL CFG_EBC_PB2AP
56 # define PBxCR_VAL CFG_EBC_PB2CR
59 # if (CFG_INIT_DCACHE_CS == 3)
62 # if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
63 # define PBxAP_VAL CFG_EBC_PB3AP
64 # define PBxCR_VAL CFG_EBC_PB3CR
67 # if (CFG_INIT_DCACHE_CS == 4)
70 # if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
71 # define PBxAP_VAL CFG_EBC_PB4AP
72 # define PBxCR_VAL CFG_EBC_PB4CR
75 # if (CFG_INIT_DCACHE_CS == 5)
78 # if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
79 # define PBxAP_VAL CFG_EBC_PB5AP
80 # define PBxCR_VAL CFG_EBC_PB5CR
83 # if (CFG_INIT_DCACHE_CS == 6)
86 # if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
87 # define PBxAP_VAL CFG_EBC_PB6AP
88 # define PBxCR_VAL CFG_EBC_PB6CR
91 # if (CFG_INIT_DCACHE_CS == 7)
94 # if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
95 # define PBxAP_VAL CFG_EBC_PB7AP
96 # define PBxCR_VAL CFG_EBC_PB7CR
99 #endif /* CFG_INIT_DCACHE_CS */
101 #if defined(CFG_440_GPIO_TABLE)
102 gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE;
104 void set_chip_gpio_configuration(gpio_param_s (*gpio_tab)[GPIO_GROUP_MAX][GPIO_MAX])
106 unsigned char i=0, j=0, reg_offset = 0, gpio_core;
107 unsigned long gpio_reg, gpio_core_add;
109 for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
112 /* GPIO config of the GPIOs 0 to 31 */
113 for (i=0; i<GPIO_MAX; i++, j++) {
114 if (i == GPIO_MAX/2) {
119 gpio_core_add = (*gpio_tab)[gpio_core][i].add;
121 if (((*gpio_tab)[gpio_core][i].in_out == GPIO_IN) ||
122 ((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) {
124 switch ((*gpio_tab)[gpio_core][i].alt_nb) {
129 gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset))
130 & ~(GPIO_MASK >> (j*2));
131 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
132 out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
136 gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset))
137 & ~(GPIO_MASK >> (j*2));
138 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
139 out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
143 gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset))
144 & ~(GPIO_MASK >> (j*2));
145 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
146 out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
151 if (((*gpio_tab)[gpio_core][i].in_out == GPIO_OUT) ||
152 ((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) {
154 switch ((*gpio_tab)[gpio_core][i].alt_nb) {
156 if (gpio_core == GPIO0) {
157 gpio_reg = in32(GPIO0_TCR) | (0x80000000 >> (j));
158 out32(GPIO0_TCR, gpio_reg);
161 if (gpio_core == GPIO1) {
162 gpio_reg = in32(GPIO1_TCR) | (0x80000000 >> (j));
163 out32(GPIO1_TCR, gpio_reg);
166 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
167 & ~(GPIO_MASK >> (j*2));
168 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
169 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
170 & ~(GPIO_MASK >> (j*2));
171 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
175 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
176 & ~(GPIO_MASK >> (j*2));
177 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
178 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
179 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
180 & ~(GPIO_MASK >> (j*2));
181 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
182 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
186 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
187 & ~(GPIO_MASK >> (j*2));
188 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
189 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
190 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
191 & ~(GPIO_MASK >> (j*2));
192 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
193 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
197 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
198 & ~(GPIO_MASK >> (j*2));
199 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
200 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
201 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
202 & ~(GPIO_MASK >> (j*2));
203 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
204 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
211 #endif /* CFG_440_GPIO_TABLE */
214 * Breath some life into the CPU...
216 * Set up the memory map,
217 * initialize a bunch of registers
222 #if defined(CONFIG_WATCHDOG)
226 #if defined(CONFIG_405EP)
228 * GPIO0 setup (select GPIO or alternate function)
230 #if defined(CFG_GPIO0_OR)
231 out32(GPIO0_OR, CFG_GPIO0_OR); /* set initial state of output pins */
233 #if defined(CFG_GPIO0_ODR)
234 out32(GPIO0_ODR, CFG_GPIO0_ODR); /* open-drain select */
236 out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
237 out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
238 out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
239 out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
240 out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
241 out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
242 out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
245 * Set EMAC noise filter bits
247 mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
248 #endif /* CONFIG_405EP */
250 #if defined(CFG_440_GPIO_TABLE)
251 set_chip_gpio_configuration(&gpio_tab);
252 #endif /* CFG_440_GPIO_TABLE */
255 * External Bus Controller (EBC) Setup
257 #if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
258 #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
259 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
262 * Move the next instructions into icache, since these modify the flash
263 * we are running from!
265 asm volatile(" bl 0f" ::: "lr");
266 asm volatile("0: mflr 3" ::: "r3");
267 asm volatile(" addi 4, 0, 14" ::: "r4");
268 asm volatile(" mtctr 4" ::: "ctr");
269 asm volatile("1: icbt 0, 3");
270 asm volatile(" addi 3, 3, 32" ::: "r3");
271 asm volatile(" bdnz 1b" ::: "ctr", "cr0");
272 asm volatile(" addis 3, 0, 0x0" ::: "r3");
273 asm volatile(" ori 3, 3, 0xA000" ::: "r3");
274 asm volatile(" mtctr 3" ::: "ctr");
275 asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
278 mtebc(pb0ap, CFG_EBC_PB0AP);
279 mtebc(pb0cr, CFG_EBC_PB0CR);
282 #if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR) && !(CFG_INIT_DCACHE_CS == 1))
283 mtebc(pb1ap, CFG_EBC_PB1AP);
284 mtebc(pb1cr, CFG_EBC_PB1CR);
287 #if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR) && !(CFG_INIT_DCACHE_CS == 2))
288 mtebc(pb2ap, CFG_EBC_PB2AP);
289 mtebc(pb2cr, CFG_EBC_PB2CR);
292 #if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR) && !(CFG_INIT_DCACHE_CS == 3))
293 mtebc(pb3ap, CFG_EBC_PB3AP);
294 mtebc(pb3cr, CFG_EBC_PB3CR);
297 #if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
298 mtebc(pb4ap, CFG_EBC_PB4AP);
299 mtebc(pb4cr, CFG_EBC_PB4CR);
302 #if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR) && !(CFG_INIT_DCACHE_CS == 5))
303 mtebc(pb5ap, CFG_EBC_PB5AP);
304 mtebc(pb5cr, CFG_EBC_PB5CR);
307 #if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR) && !(CFG_INIT_DCACHE_CS == 6))
308 mtebc(pb6ap, CFG_EBC_PB6AP);
309 mtebc(pb6cr, CFG_EBC_PB6CR);
312 #if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR) && !(CFG_INIT_DCACHE_CS == 7))
313 mtebc(pb7ap, CFG_EBC_PB7AP);
314 mtebc(pb7cr, CFG_EBC_PB7CR);
317 #if defined (CFG_EBC_CFG)
318 mtebc(EBC0_CFG, CFG_EBC_CFG);
321 #if defined(CONFIG_WATCHDOG)
323 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
324 val |= 0xb8000000; /* generate system reset after 1.34 seconds */
326 val |= 0xf0000000; /* generate system reset after 2.684 seconds */
328 #if defined(CFG_4xx_RESET_TYPE)
329 val &= ~0x30000000; /* clear WRC bits */
330 val |= CFG_4xx_RESET_TYPE << 28; /* set board specific WRC type */
335 val |= 0x80000000; /* enable watchdog timer */
338 reset_4xx_watchdog();
339 #endif /* CONFIG_WATCHDOG */
343 * initialize higher level parts of CPU like time base and timers
345 int cpu_init_r (void)
347 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
350 #if defined(CONFIG_405GP)
351 uint pvr = get_pvr();
354 #ifdef CFG_INIT_DCACHE_CS
356 * Flush and invalidate dcache, then disable CS for temporary stack.
357 * Afterwards, this CS can be used for other purposes
359 dcache_disable(); /* flush and invalidate dcache */
361 mtebc(PBxCR, 0); /* disable CS for temporary stack */
363 #if (defined(PBxAP_VAL) && defined(PBxCR_VAL))
365 * Write new value into CS register
367 mtebc(PBxAP, PBxAP_VAL);
368 mtebc(PBxCR, PBxCR_VAL);
370 #endif /* CFG_INIT_DCACHE_CS */
373 * Write Ethernetaddress into on-chip register
376 reg |= bd->bi_enetaddr[0]; /* set high address */
378 reg |= bd->bi_enetaddr[1];
379 out32 (EMAC_IAH, reg);
382 reg |= bd->bi_enetaddr[2]; /* set low address */
384 reg |= bd->bi_enetaddr[3];
386 reg |= bd->bi_enetaddr[4];
388 reg |= bd->bi_enetaddr[5];
389 out32 (EMAC_IAL, reg);
391 #if defined(CONFIG_405GP)
393 * Set edge conditioning circuitry on PPC405GPr
394 * for compatibility to existing PPC405GP designs.
396 if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
397 mtdcr(ecr, 0x60606000);
399 #endif /* defined(CONFIG_405GP) */
400 #endif /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */