2 * (C) Copyright 2000-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
30 * minor modifications by
31 * Wolfgang Denk <wd@denx.de>
37 #include <asm/cache.h>
40 #if !defined(CONFIG_405)
41 DECLARE_GLOBAL_DATA_PTR;
45 #if defined(CONFIG_440)
46 #define FREQ_EBC (sys_info.freqEPB)
48 #define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv)
51 #if defined(CONFIG_405GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
55 int pci_async_enabled(void)
57 #if defined(CONFIG_405GP)
58 return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
61 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
64 mfsdr(sdr_sdstp1, val);
65 return (val & SDR0_SDSTP1_PAME_MASK);
70 #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405)
71 int pci_arbiter_enabled(void)
73 #if defined(CONFIG_405GP)
74 return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
77 #if defined(CONFIG_405EP)
78 return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
81 #if defined(CONFIG_440GP)
82 return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
85 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
86 defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
87 defined(CONFIG_440SPE)
90 mfsdr(sdr_sdstp1, val);
91 return (val & SDR0_SDSTP1_PAE_MASK);
96 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
97 defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
101 int i2c_bootrom_enabled(void)
103 #if defined(CONFIG_405EP)
104 return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
107 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
108 defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
109 defined(CONFIG_440SPE)
112 mfsdr(sdr_sdcs, val);
113 return (val & SDR0_SDCS_SDD);
119 #if defined(CONFIG_440)
120 static int do_chip_reset(unsigned long sys0, unsigned long sys1);
126 #if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
127 uint pvr = get_pvr();
128 ulong clock = gd->cpu_clk;
131 #if !defined(CONFIG_IOP480)
136 get_sys_info(&sys_info);
138 puts("AMCC PowerPC 4");
140 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
143 #if defined(CONFIG_440)
161 case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
175 case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
188 #if defined(CONFIG_440)
191 /* See errata 1.12: CHIP_4 */
192 if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
193 (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
194 puts ( "\n\t CPC0_SYSx DCRs corrupted. "
195 "Resetting chip ...\n");
196 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
197 do_chip_reset ( mfdcr(cpc0_strp0),
227 case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
231 case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
234 #endif /* CONFIG_440EP */
237 case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
241 case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
244 #endif /* CONFIG_440GR */
245 #endif /* CONFIG_440 */
262 printf (" UNKNOWN (PVR=%08x)", pvr);
266 printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
267 sys_info.freqPLB / 1000000,
268 sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
271 #if defined(I2C_BOOTROM)
272 printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
275 #if defined(CONFIG_PCI)
276 printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
279 #if defined(PCI_ASYNC)
280 if (pci_async_enabled()) {
281 printf (", PCI async ext clock used");
283 printf (", PCI sync clock at %lu MHz",
284 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
288 #if defined(CONFIG_PCI)
292 #if defined(CONFIG_405EP)
293 printf (" 16 kB I-Cache 16 kB D-Cache");
294 #elif defined(CONFIG_440)
295 printf (" 32 kB I-Cache 32 kB D-Cache");
297 printf (" 16 kB I-Cache %d kB D-Cache",
298 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
300 #endif /* !defined(CONFIG_IOP480) */
302 #if defined(CONFIG_IOP480)
303 printf ("PLX IOP480 (PVR=%08x)", pvr);
304 printf (" at %s MHz:", strmhz(buf, clock));
305 printf (" %u kB I-Cache", 4);
306 printf (" %u kB D-Cache", 2);
309 #endif /* !defined(CONFIG_405) */
317 /* ------------------------------------------------------------------------- */
319 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
321 #if defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)
322 /*give reset to BCSR*/
323 *(unsigned char*)(CFG_BCSR_BASE | 0x06) = 0x09;
328 * Initiate system reset in debug control register DBCR
330 __asm__ __volatile__("lis 3, 0x3000" ::: "r3");
331 #if defined(CONFIG_440)
332 __asm__ __volatile__("mtspr 0x134, 3");
334 __asm__ __volatile__("mtspr 0x3f2, 3");
337 #endif/* defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)*/
341 #if defined(CONFIG_440)
342 static int do_chip_reset (unsigned long sys0, unsigned long sys1)
344 /* Changes to cpc0_sys0 and cpc0_sys1 require chip
347 mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
348 mtdcr (cpc0_sys0, sys0);
349 mtdcr (cpc0_sys1, sys1);
350 mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
351 mtspr (dbcr0, 0x20000000); /* Reset the chip */
359 * Get timebase clock frequency
361 unsigned long get_tbclk (void)
363 #if !defined(CONFIG_IOP480)
366 get_sys_info(&sys_info);
367 return (sys_info.freqProcessor);
375 #if defined(CONFIG_WATCHDOG)
379 int re_enable = disable_interrupts();
380 reset_4xx_watchdog();
381 if (re_enable) enable_interrupts();
385 reset_4xx_watchdog(void)
390 mtspr(tsr, 0x40000000);
392 #endif /* CONFIG_WATCHDOG */