2 * (C) Copyright 2000-2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
30 * minor modifications by
31 * Wolfgang Denk <wd@denx.de>
37 #include <asm/cache.h>
40 DECLARE_GLOBAL_DATA_PTR;
42 void board_reset(void);
44 #if defined(CONFIG_405GP) || \
45 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
46 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
50 static int pci_async_enabled(void)
52 #if defined(CONFIG_405GP)
53 return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
56 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
57 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
58 defined(CONFIG_460EX) || defined(CONFIG_460GT)
61 mfsdr(sdr_sdstp1, val);
62 return (val & SDR0_SDSTP1_PAME_MASK);
67 #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
68 !defined(CONFIG_405) && !defined(CONFIG_405EX)
69 static int pci_arbiter_enabled(void)
71 #if defined(CONFIG_405GP)
72 return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
75 #if defined(CONFIG_405EP)
76 return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
79 #if defined(CONFIG_440GP)
80 return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
83 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
87 return (val & 0x80000000);
89 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
90 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
91 defined(CONFIG_460EX) || defined(CONFIG_460GT)
95 return (val & 0x80000000);
100 #if defined(CONFIG_405EP)
103 static int i2c_bootrom_enabled(void)
105 #if defined(CONFIG_405EP)
106 return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
110 mfsdr(sdr_sdcs, val);
111 return (val & SDR0_SDCS_SDD);
116 #if defined(CONFIG_440GX)
117 #define SDR0_PINSTP_SHIFT 29
118 static char *bootstrap_str[] = {
128 static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
131 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
132 #define SDR0_PINSTP_SHIFT 30
133 static char *bootstrap_str[] = {
139 static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
142 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
143 #define SDR0_PINSTP_SHIFT 29
144 static char *bootstrap_str[] = {
154 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
157 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
158 #define SDR0_PINSTP_SHIFT 29
159 static char *bootstrap_str[] = {
169 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
172 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
173 #define SDR0_PINSTP_SHIFT 29
174 static char *bootstrap_str[] = {
181 "I2C (Addr 0x54)", /* A8 */
182 "I2C (Addr 0x52)", /* A4 */
184 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
187 #if defined(CONFIG_405EZ)
188 #define SDR0_PINSTP_SHIFT 28
189 static char *bootstrap_str[] = {
192 "NAND (512 page, 4 addr cycle)",
196 "NAND (2K page, 5 addr cycle)",
200 "NAND (2K page, 4 addr cycle)",
202 "NAND (512 page, 3 addr cycle)",
207 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
208 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
211 #if defined(CONFIG_405EX)
212 #define SDR0_PINSTP_SHIFT 29
213 static char *bootstrap_str[] = {
223 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
226 #if defined(SDR0_PINSTP_SHIFT)
227 static int bootstrap_option(void)
231 mfsdr(SDR_PINSTP, val);
232 return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
234 #endif /* SDR0_PINSTP_SHIFT */
237 #if defined(CONFIG_440)
238 static int do_chip_reset (unsigned long sys0, unsigned long sys1)
240 /* Changes to cpc0_sys0 and cpc0_sys1 require chip
243 mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
244 mtdcr (cpc0_sys0, sys0);
245 mtdcr (cpc0_sys1, sys1);
246 mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
247 mtspr (dbcr0, 0x20000000); /* Reset the chip */
256 #if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
257 uint pvr = get_pvr();
258 ulong clock = gd->cpu_clk;
261 #if !defined(CONFIG_IOP480)
262 char addstr[64] = "";
267 get_sys_info(&sys_info);
269 puts("AMCC PowerPC 4");
271 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
272 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
273 defined(CONFIG_405EX)
276 #if defined(CONFIG_440)
277 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
298 case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
312 case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
331 strcpy(addstr, "Security support");
336 strcpy(addstr, "No Security support");
341 strcpy(addstr, "Security support");
346 strcpy(addstr, "No Security support");
349 #if defined(CONFIG_440)
352 /* See errata 1.12: CHIP_4 */
353 if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
354 (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
355 puts ( "\n\t CPC0_SYSx DCRs corrupted. "
356 "Resetting chip ...\n");
357 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
358 do_chip_reset ( mfdcr(cpc0_strp0),
388 case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
392 case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
395 #endif /* CONFIG_440EP */
398 case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
402 case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
405 #endif /* CONFIG_440GR */
406 #endif /* CONFIG_440 */
409 case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
411 strcpy(addstr, "Security/Kasumi support");
414 case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
416 strcpy(addstr, "No Security/Kasumi support");
418 #endif /* CONFIG_440EPX */
421 case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
423 strcpy(addstr, "Security/Kasumi support");
426 case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
428 strcpy(addstr, "No Security/Kasumi support");
430 #endif /* CONFIG_440GRX */
432 case PVR_440SP_6_RAB:
434 strcpy(addstr, "RAID 6 support");
439 strcpy(addstr, "No RAID 6 support");
444 strcpy(addstr, "RAID 6 support");
449 strcpy(addstr, "No RAID 6 support");
452 case PVR_440SPe_6_RA:
454 strcpy(addstr, "RAID 6 support");
459 strcpy(addstr, "No RAID 6 support");
462 case PVR_440SPe_6_RB:
464 strcpy(addstr, "RAID 6 support");
469 strcpy(addstr, "No RAID 6 support");
474 strcpy(addstr, "No Security/Kasumi support");
477 case PVR_460EX_SE_RA:
479 strcpy(addstr, "Security/Kasumi support");
484 strcpy(addstr, "No Security/Kasumi support");
487 case PVR_460GT_SE_RA:
489 strcpy(addstr, "Security/Kasumi support");
493 printf (" UNKNOWN (PVR=%08x)", pvr);
497 printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
498 sys_info.freqPLB / 1000000,
499 get_OPB_freq() / 1000000,
500 sys_info.freqEBC / 1000000);
503 printf(" %s\n", addstr);
505 #if defined(I2C_BOOTROM)
506 printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
507 #endif /* I2C_BOOTROM */
508 #if defined(SDR0_PINSTP_SHIFT)
509 printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
510 printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
511 #endif /* SDR0_PINSTP_SHIFT */
513 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
514 printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
517 #if defined(PCI_ASYNC)
518 if (pci_async_enabled()) {
519 printf (", PCI async ext clock used");
521 printf (", PCI sync clock at %lu MHz",
522 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
526 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
530 #if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
531 printf (" 16 kB I-Cache 16 kB D-Cache");
532 #elif defined(CONFIG_440)
533 printf (" 32 kB I-Cache 32 kB D-Cache");
535 printf (" 16 kB I-Cache %d kB D-Cache",
536 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
538 #endif /* !defined(CONFIG_IOP480) */
540 #if defined(CONFIG_IOP480)
541 printf ("PLX IOP480 (PVR=%08x)", pvr);
542 printf (" at %s MHz:", strmhz(buf, clock));
543 printf (" %u kB I-Cache", 4);
544 printf (" %u kB D-Cache", 2);
547 #endif /* !defined(CONFIG_405) */
554 int ppc440spe_revB() {
558 if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
564 /* ------------------------------------------------------------------------- */
566 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
568 #if defined(CONFIG_BOARD_RESET)
571 #if defined(CFG_4xx_RESET_TYPE)
572 mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28);
575 * Initiate system reset in debug control register DBCR
577 mtspr(dbcr0, 0x30000000);
578 #endif /* defined(CFG_4xx_RESET_TYPE) */
579 #endif /* defined(CONFIG_BOARD_RESET) */
586 * Get timebase clock frequency
588 unsigned long get_tbclk (void)
590 #if !defined(CONFIG_IOP480)
593 get_sys_info(&sys_info);
594 return (sys_info.freqProcessor);
602 #if defined(CONFIG_WATCHDOG)
603 void watchdog_reset(void)
605 int re_enable = disable_interrupts();
606 reset_4xx_watchdog();
607 if (re_enable) enable_interrupts();
610 void reset_4xx_watchdog(void)
615 mtspr(tsr, 0x40000000);
617 #endif /* CONFIG_WATCHDOG */