2 * (C) Copyright 2000-2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
30 * minor modifications by
31 * Wolfgang Denk <wd@denx.de>
37 #include <asm/cache.h>
41 DECLARE_GLOBAL_DATA_PTR;
43 void board_reset(void);
46 * To provide an interface to detect CPU number for boards that support
47 * more then one CPU, we implement the "weak" default functions here.
51 int __get_cpu_num(void)
53 return NA_OR_UNKNOWN_CPU;
55 int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));
57 #if defined(CONFIG_405GP) || \
58 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
59 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
63 static int pci_async_enabled(void)
65 #if defined(CONFIG_405GP)
66 return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
69 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
70 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
71 defined(CONFIG_460EX) || defined(CONFIG_460GT)
74 mfsdr(sdr_sdstp1, val);
75 return (val & SDR0_SDSTP1_PAME_MASK);
80 #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
81 !defined(CONFIG_405) && !defined(CONFIG_405EX)
82 static int pci_arbiter_enabled(void)
84 #if defined(CONFIG_405GP)
85 return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
88 #if defined(CONFIG_405EP)
89 return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
92 #if defined(CONFIG_440GP)
93 return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
96 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
100 return (val & 0x80000000);
102 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
103 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
104 defined(CONFIG_460EX) || defined(CONFIG_460GT)
107 mfsdr(sdr_pci0, val);
108 return (val & 0x80000000);
113 #if defined(CONFIG_405EP)
116 static int i2c_bootrom_enabled(void)
118 #if defined(CONFIG_405EP)
119 return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
123 mfsdr(sdr_sdcs, val);
124 return (val & SDR0_SDCS_SDD);
129 #if defined(CONFIG_440GX)
130 #define SDR0_PINSTP_SHIFT 29
131 static char *bootstrap_str[] = {
141 static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
144 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
145 #define SDR0_PINSTP_SHIFT 30
146 static char *bootstrap_str[] = {
152 static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
155 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
156 #define SDR0_PINSTP_SHIFT 29
157 static char *bootstrap_str[] = {
167 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
170 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
171 #define SDR0_PINSTP_SHIFT 29
172 static char *bootstrap_str[] = {
182 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
185 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
186 #define SDR0_PINSTP_SHIFT 29
187 static char *bootstrap_str[] = {
194 "I2C (Addr 0x54)", /* A8 */
195 "I2C (Addr 0x52)", /* A4 */
197 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
200 #if defined(CONFIG_460SX)
201 #define SDR0_PINSTP_SHIFT 29
202 static char *bootstrap_str[] = {
207 "I2C (Addr 0x54)", /* A8 */
208 "I2C (Addr 0x52)", /* A4 */
210 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
213 #if defined(CONFIG_405EZ)
214 #define SDR0_PINSTP_SHIFT 28
215 static char *bootstrap_str[] = {
218 "NAND (512 page, 4 addr cycle)",
222 "NAND (2K page, 5 addr cycle)",
226 "NAND (2K page, 4 addr cycle)",
228 "NAND (512 page, 3 addr cycle)",
233 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
234 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
237 #if defined(CONFIG_405EX)
238 #define SDR0_PINSTP_SHIFT 29
239 static char *bootstrap_str[] = {
249 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
252 #if defined(SDR0_PINSTP_SHIFT)
253 static int bootstrap_option(void)
257 mfsdr(SDR_PINSTP, val);
258 return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
260 #endif /* SDR0_PINSTP_SHIFT */
263 #if defined(CONFIG_440)
264 static int do_chip_reset (unsigned long sys0, unsigned long sys1)
266 /* Changes to cpc0_sys0 and cpc0_sys1 require chip
269 mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
270 mtdcr (cpc0_sys0, sys0);
271 mtdcr (cpc0_sys1, sys1);
272 mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
273 mtspr (dbcr0, 0x20000000); /* Reset the chip */
282 #if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
283 uint pvr = get_pvr();
284 ulong clock = gd->cpu_clk;
287 #if !defined(CONFIG_IOP480)
288 char addstr[64] = "";
292 cpu_num = get_cpu_num();
294 printf("CPU%d: ", cpu_num);
298 get_sys_info(&sys_info);
300 #if defined(CONFIG_XILINX_440)
301 puts("IBM PowerPC 4");
303 puts("AMCC PowerPC 4");
306 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
307 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
308 defined(CONFIG_405EX)
311 #if defined(CONFIG_440)
312 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
333 case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
347 case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
366 strcpy(addstr, "Security support");
371 strcpy(addstr, "No Security support");
376 strcpy(addstr, "Security support");
381 strcpy(addstr, "No Security support");
386 strcpy(addstr, "Security support");
391 strcpy(addstr, "No Security support");
396 strcpy(addstr, "Security support");
401 strcpy(addstr, "No Security support");
404 #if defined(CONFIG_440)
407 /* See errata 1.12: CHIP_4 */
408 if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
409 (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
410 puts ( "\n\t CPC0_SYSx DCRs corrupted. "
411 "Resetting chip ...\n");
412 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
413 do_chip_reset ( mfdcr(cpc0_strp0),
443 case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
447 case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
450 #endif /* CONFIG_440EP */
453 case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
457 case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
460 #endif /* CONFIG_440GR */
461 #endif /* CONFIG_440 */
464 case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
466 strcpy(addstr, "Security/Kasumi support");
469 case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
471 strcpy(addstr, "No Security/Kasumi support");
473 #endif /* CONFIG_440EPX */
476 case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
478 strcpy(addstr, "Security/Kasumi support");
481 case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
483 strcpy(addstr, "No Security/Kasumi support");
485 #endif /* CONFIG_440GRX */
487 case PVR_440SP_6_RAB:
489 strcpy(addstr, "RAID 6 support");
494 strcpy(addstr, "No RAID 6 support");
499 strcpy(addstr, "RAID 6 support");
504 strcpy(addstr, "No RAID 6 support");
507 case PVR_440SPe_6_RA:
509 strcpy(addstr, "RAID 6 support");
514 strcpy(addstr, "No RAID 6 support");
517 case PVR_440SPe_6_RB:
519 strcpy(addstr, "RAID 6 support");
524 strcpy(addstr, "No RAID 6 support");
529 strcpy(addstr, "No Security/Kasumi support");
532 case PVR_460EX_SE_RA:
534 strcpy(addstr, "Security/Kasumi support");
539 strcpy(addstr, "No Security/Kasumi support");
542 case PVR_460GT_SE_RA:
544 strcpy(addstr, "Security/Kasumi support");
549 strcpy(addstr, "Security support");
552 case PVR_460SX_RA_V1:
554 strcpy(addstr, "No Security support");
559 strcpy(addstr, "Security support");
562 case PVR_460GX_RA_V1:
564 strcpy(addstr, "No Security support");
572 printf (" UNKNOWN (PVR=%08x)", pvr);
576 printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
577 sys_info.freqPLB / 1000000,
578 get_OPB_freq() / 1000000,
579 sys_info.freqEBC / 1000000);
582 printf(" %s\n", addstr);
584 #if defined(I2C_BOOTROM)
585 printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
586 #endif /* I2C_BOOTROM */
587 #if defined(SDR0_PINSTP_SHIFT)
588 printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
589 printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
590 #endif /* SDR0_PINSTP_SHIFT */
592 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
593 printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
596 #if defined(PCI_ASYNC)
597 if (pci_async_enabled()) {
598 printf (", PCI async ext clock used");
600 printf (", PCI sync clock at %lu MHz",
601 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
605 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
609 #if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
610 printf (" 16 kB I-Cache 16 kB D-Cache");
611 #elif defined(CONFIG_440)
612 printf (" 32 kB I-Cache 32 kB D-Cache");
614 printf (" 16 kB I-Cache %d kB D-Cache",
615 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
617 #endif /* !defined(CONFIG_IOP480) */
619 #if defined(CONFIG_IOP480)
620 printf ("PLX IOP480 (PVR=%08x)", pvr);
621 printf (" at %s MHz:", strmhz(buf, clock));
622 printf (" %u kB I-Cache", 4);
623 printf (" %u kB D-Cache", 2);
626 #endif /* !defined(CONFIG_405) */
633 int ppc440spe_revB() {
637 if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
643 /* ------------------------------------------------------------------------- */
645 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
647 #if defined(CONFIG_BOARD_RESET)
650 #if defined(CONFIG_SYS_4xx_RESET_TYPE)
651 mtspr(dbcr0, CONFIG_SYS_4xx_RESET_TYPE << 28);
654 * Initiate system reset in debug control register DBCR
656 mtspr(dbcr0, 0x30000000);
657 #endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
658 #endif /* defined(CONFIG_BOARD_RESET) */
665 * Get timebase clock frequency
667 unsigned long get_tbclk (void)
669 #if !defined(CONFIG_IOP480)
672 get_sys_info(&sys_info);
673 return (sys_info.freqProcessor);
681 #if defined(CONFIG_WATCHDOG)
682 void watchdog_reset(void)
684 int re_enable = disable_interrupts();
685 reset_4xx_watchdog();
686 if (re_enable) enable_interrupts();
689 void reset_4xx_watchdog(void)
694 mtspr(tsr, 0x40000000);
696 #endif /* CONFIG_WATCHDOG */
699 * Initializes on-chip ethernet controllers.
700 * to override, implement board_eth_init()
702 int cpu_eth_init(bd_t *bis)
704 #if defined(CONFIG_PPC4xx_EMAC)
705 ppc_4xx_eth_initialize(bis);