2 * (C) Copyright 2000-2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
30 * minor modifications by
31 * Wolfgang Denk <wd@denx.de>
37 #include <asm/cache.h>
40 DECLARE_GLOBAL_DATA_PTR;
42 void board_reset(void);
45 * To provide an interface to detect CPU number for boards that support
46 * more then one CPU, we implement the "weak" default functions here.
50 int __get_cpu_num(void)
52 return NA_OR_UNKNOWN_CPU;
54 int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));
56 #if defined(CONFIG_405GP) || \
57 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
58 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
62 static int pci_async_enabled(void)
64 #if defined(CONFIG_405GP)
65 return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
68 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
69 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
70 defined(CONFIG_460EX) || defined(CONFIG_460GT)
73 mfsdr(sdr_sdstp1, val);
74 return (val & SDR0_SDSTP1_PAME_MASK);
79 #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
80 !defined(CONFIG_405) && !defined(CONFIG_405EX)
81 static int pci_arbiter_enabled(void)
83 #if defined(CONFIG_405GP)
84 return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
87 #if defined(CONFIG_405EP)
88 return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
91 #if defined(CONFIG_440GP)
92 return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
95 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
99 return (val & 0x80000000);
101 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
102 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
103 defined(CONFIG_460EX) || defined(CONFIG_460GT)
106 mfsdr(sdr_pci0, val);
107 return (val & 0x80000000);
112 #if defined(CONFIG_405EP)
115 static int i2c_bootrom_enabled(void)
117 #if defined(CONFIG_405EP)
118 return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
122 mfsdr(sdr_sdcs, val);
123 return (val & SDR0_SDCS_SDD);
128 #if defined(CONFIG_440GX)
129 #define SDR0_PINSTP_SHIFT 29
130 static char *bootstrap_str[] = {
140 static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
143 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
144 #define SDR0_PINSTP_SHIFT 30
145 static char *bootstrap_str[] = {
151 static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
154 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
155 #define SDR0_PINSTP_SHIFT 29
156 static char *bootstrap_str[] = {
166 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
169 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
170 #define SDR0_PINSTP_SHIFT 29
171 static char *bootstrap_str[] = {
181 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
184 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
185 #define SDR0_PINSTP_SHIFT 29
186 static char *bootstrap_str[] = {
193 "I2C (Addr 0x54)", /* A8 */
194 "I2C (Addr 0x52)", /* A4 */
196 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
199 #if defined(CONFIG_460SX)
200 #define SDR0_PINSTP_SHIFT 29
201 static char *bootstrap_str[] = {
206 "I2C (Addr 0x54)", /* A8 */
207 "I2C (Addr 0x52)", /* A4 */
209 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
212 #if defined(CONFIG_405EZ)
213 #define SDR0_PINSTP_SHIFT 28
214 static char *bootstrap_str[] = {
217 "NAND (512 page, 4 addr cycle)",
221 "NAND (2K page, 5 addr cycle)",
225 "NAND (2K page, 4 addr cycle)",
227 "NAND (512 page, 3 addr cycle)",
232 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
233 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
236 #if defined(CONFIG_405EX)
237 #define SDR0_PINSTP_SHIFT 29
238 static char *bootstrap_str[] = {
248 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
251 #if defined(SDR0_PINSTP_SHIFT)
252 static int bootstrap_option(void)
256 mfsdr(SDR_PINSTP, val);
257 return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
259 #endif /* SDR0_PINSTP_SHIFT */
262 #if defined(CONFIG_440)
263 static int do_chip_reset (unsigned long sys0, unsigned long sys1)
265 /* Changes to cpc0_sys0 and cpc0_sys1 require chip
268 mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
269 mtdcr (cpc0_sys0, sys0);
270 mtdcr (cpc0_sys1, sys1);
271 mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
272 mtspr (dbcr0, 0x20000000); /* Reset the chip */
281 #if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
282 uint pvr = get_pvr();
283 ulong clock = gd->cpu_clk;
286 #if !defined(CONFIG_IOP480)
287 char addstr[64] = "";
291 cpu_num = get_cpu_num();
293 printf("CPU%d: ", cpu_num);
297 get_sys_info(&sys_info);
299 #if defined(CONFIG_XILINX_440)
300 puts("IBM PowerPC 4");
302 puts("AMCC PowerPC 4");
305 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
306 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
307 defined(CONFIG_405EX)
310 #if defined(CONFIG_440)
311 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
332 case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
346 case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
365 strcpy(addstr, "Security support");
370 strcpy(addstr, "No Security support");
375 strcpy(addstr, "Security support");
380 strcpy(addstr, "No Security support");
385 strcpy(addstr, "Security support");
390 strcpy(addstr, "No Security support");
395 strcpy(addstr, "Security support");
400 strcpy(addstr, "No Security support");
403 #if defined(CONFIG_440)
406 /* See errata 1.12: CHIP_4 */
407 if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
408 (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
409 puts ( "\n\t CPC0_SYSx DCRs corrupted. "
410 "Resetting chip ...\n");
411 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
412 do_chip_reset ( mfdcr(cpc0_strp0),
442 case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
446 case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
449 #endif /* CONFIG_440EP */
452 case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
456 case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
459 #endif /* CONFIG_440GR */
460 #endif /* CONFIG_440 */
463 case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
465 strcpy(addstr, "Security/Kasumi support");
468 case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
470 strcpy(addstr, "No Security/Kasumi support");
472 #endif /* CONFIG_440EPX */
475 case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
477 strcpy(addstr, "Security/Kasumi support");
480 case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
482 strcpy(addstr, "No Security/Kasumi support");
484 #endif /* CONFIG_440GRX */
486 case PVR_440SP_6_RAB:
488 strcpy(addstr, "RAID 6 support");
493 strcpy(addstr, "No RAID 6 support");
498 strcpy(addstr, "RAID 6 support");
503 strcpy(addstr, "No RAID 6 support");
506 case PVR_440SPe_6_RA:
508 strcpy(addstr, "RAID 6 support");
513 strcpy(addstr, "No RAID 6 support");
516 case PVR_440SPe_6_RB:
518 strcpy(addstr, "RAID 6 support");
523 strcpy(addstr, "No RAID 6 support");
528 strcpy(addstr, "No Security/Kasumi support");
531 case PVR_460EX_SE_RA:
533 strcpy(addstr, "Security/Kasumi support");
538 strcpy(addstr, "No Security/Kasumi support");
541 case PVR_460GT_SE_RA:
543 strcpy(addstr, "Security/Kasumi support");
548 strcpy(addstr, "Security support");
551 case PVR_460SX_RA_V1:
553 strcpy(addstr, "No Security support");
558 strcpy(addstr, "Security support");
561 case PVR_460GX_RA_V1:
563 strcpy(addstr, "No Security support");
571 printf (" UNKNOWN (PVR=%08x)", pvr);
575 printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
576 sys_info.freqPLB / 1000000,
577 get_OPB_freq() / 1000000,
578 sys_info.freqEBC / 1000000);
581 printf(" %s\n", addstr);
583 #if defined(I2C_BOOTROM)
584 printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
585 #endif /* I2C_BOOTROM */
586 #if defined(SDR0_PINSTP_SHIFT)
587 printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
588 printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
589 #endif /* SDR0_PINSTP_SHIFT */
591 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
592 printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
595 #if defined(PCI_ASYNC)
596 if (pci_async_enabled()) {
597 printf (", PCI async ext clock used");
599 printf (", PCI sync clock at %lu MHz",
600 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
604 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
608 #if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
609 printf (" 16 kB I-Cache 16 kB D-Cache");
610 #elif defined(CONFIG_440)
611 printf (" 32 kB I-Cache 32 kB D-Cache");
613 printf (" 16 kB I-Cache %d kB D-Cache",
614 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
616 #endif /* !defined(CONFIG_IOP480) */
618 #if defined(CONFIG_IOP480)
619 printf ("PLX IOP480 (PVR=%08x)", pvr);
620 printf (" at %s MHz:", strmhz(buf, clock));
621 printf (" %u kB I-Cache", 4);
622 printf (" %u kB D-Cache", 2);
625 #endif /* !defined(CONFIG_405) */
632 int ppc440spe_revB() {
636 if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
642 /* ------------------------------------------------------------------------- */
644 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
646 #if defined(CONFIG_BOARD_RESET)
649 #if defined(CONFIG_SYS_4xx_RESET_TYPE)
650 mtspr(dbcr0, CONFIG_SYS_4xx_RESET_TYPE << 28);
653 * Initiate system reset in debug control register DBCR
655 mtspr(dbcr0, 0x30000000);
656 #endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
657 #endif /* defined(CONFIG_BOARD_RESET) */
664 * Get timebase clock frequency
666 unsigned long get_tbclk (void)
668 #if !defined(CONFIG_IOP480)
671 get_sys_info(&sys_info);
672 return (sys_info.freqProcessor);
680 #if defined(CONFIG_WATCHDOG)
681 void watchdog_reset(void)
683 int re_enable = disable_interrupts();
684 reset_4xx_watchdog();
685 if (re_enable) enable_interrupts();
688 void reset_4xx_watchdog(void)
693 mtspr(tsr, 0x40000000);
695 #endif /* CONFIG_WATCHDOG */