2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
30 * minor modifications by
31 * Wolfgang Denk <wd@denx.de>
37 #include <asm/cache.h>
41 #if defined(CONFIG_440)
42 #define FREQ_EBC (sys_info.freqEPB)
44 #define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv)
47 #if defined(CONFIG_405GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
51 int pci_async_enabled(void)
53 #if defined(CONFIG_405GP)
54 return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
57 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
60 mfsdr(cpc0_strp1, val);
61 return (val & SDR0_SDSTP1_PAME_MASK);
66 #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405)
67 int pci_arbiter_enabled(void)
69 #if defined(CONFIG_405GP)
70 return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
73 #if defined(CONFIG_405EP)
74 return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
77 #if defined(CONFIG_440GP)
78 return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
81 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
84 mfsdr(sdr_sdstp1, val);
85 return (val & SDR0_SDSTP1_PAE_MASK);
90 #if defined(CONFIG_405EP)|| defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
91 defined(CONFIG_440GX) || defined(CONFIG_440SP)
95 int i2c_bootrom_enabled(void)
97 #if defined(CONFIG_405EP)
98 return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
101 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
104 mfsdr(sdr_sdcs, val);
105 return (val & SDR0_SDCS_SDD);
111 #if defined(CONFIG_440)
112 static int do_chip_reset(unsigned long sys0, unsigned long sys1);
118 #if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
119 DECLARE_GLOBAL_DATA_PTR;
120 uint pvr = get_pvr();
121 ulong clock = gd->cpu_clk;
124 #if !defined(CONFIG_IOP480)
129 get_sys_info(&sys_info);
131 puts("AMCC PowerPC 4");
133 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
136 #if defined(CONFIG_440)
154 case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
168 case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
181 #if defined(CONFIG_440)
184 /* See errata 1.12: CHIP_4 */
185 if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
186 (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
187 puts ( "\n\t CPC0_SYSx DCRs corrupted. "
188 "Resetting chip ...\n");
189 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
190 do_chip_reset ( mfdcr(cpc0_strp0),
220 case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
223 #endif /* CONFIG_440EP */
226 case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
229 #endif /* CONFIG_440GR */
230 #endif /* CONFIG_440 */
241 printf (" UNKNOWN (PVR=%08x)", pvr);
245 printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
246 sys_info.freqPLB / 1000000,
247 sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
250 #if defined(I2C_BOOTROM)
251 printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
254 #if defined(CONFIG_PCI)
255 printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
258 #if defined(PCI_ASYNC)
259 if (pci_async_enabled()) {
260 printf (", PCI async ext clock used");
262 printf (", PCI sync clock at %lu MHz",
263 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
267 #if defined(CONFIG_PCI)
271 #if defined(CONFIG_405EP)
272 printf (" 16 kB I-Cache 16 kB D-Cache");
273 #elif defined(CONFIG_440)
274 printf (" 32 kB I-Cache 32 kB D-Cache");
276 printf (" 16 kB I-Cache %d kB D-Cache",
277 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
279 #endif /* !defined(CONFIG_IOP480) */
281 #if defined(CONFIG_IOP480)
282 printf ("PLX IOP480 (PVR=%08x)", pvr);
283 printf (" at %s MHz:", strmhz(buf, clock));
284 printf (" %u kB I-Cache", 4);
285 printf (" %u kB D-Cache", 2);
288 #endif /* !defined(CONFIG_405) */
296 /* ------------------------------------------------------------------------- */
298 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
300 #if defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)
301 /*give reset to BCSR*/
302 *(unsigned char*)(CFG_BCSR_BASE | 0x06) = 0x09;
307 * Initiate system reset in debug control register DBCR
309 __asm__ __volatile__("lis 3, 0x3000" ::: "r3");
310 #if defined(CONFIG_440)
311 __asm__ __volatile__("mtspr 0x134, 3");
313 __asm__ __volatile__("mtspr 0x3f2, 3");
316 #endif/* defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)*/
320 #if defined(CONFIG_440)
321 static int do_chip_reset (unsigned long sys0, unsigned long sys1)
323 /* Changes to cpc0_sys0 and cpc0_sys1 require chip
326 mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
327 mtdcr (cpc0_sys0, sys0);
328 mtdcr (cpc0_sys1, sys1);
329 mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
330 mtspr (dbcr0, 0x20000000); /* Reset the chip */
338 * Get timebase clock frequency
340 unsigned long get_tbclk (void)
342 #if !defined(CONFIG_IOP480)
345 get_sys_info(&sys_info);
346 return (sys_info.freqProcessor);
354 #if defined(CONFIG_WATCHDOG)
358 int re_enable = disable_interrupts();
359 reset_4xx_watchdog();
360 if (re_enable) enable_interrupts();
364 reset_4xx_watchdog(void)
369 mtspr(tsr, 0x40000000);
371 #endif /* CONFIG_WATCHDOG */