2 * (C) Copyright 2000-2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
30 * minor modifications by
31 * Wolfgang Denk <wd@denx.de>
37 #include <asm/cache.h>
40 DECLARE_GLOBAL_DATA_PTR;
42 void board_reset(void);
44 #if defined(CONFIG_405GP) || \
45 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
46 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
50 static int pci_async_enabled(void)
52 #if defined(CONFIG_405GP)
53 return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
56 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
57 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
60 mfsdr(sdr_sdstp1, val);
61 return (val & SDR0_SDSTP1_PAME_MASK);
66 #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
67 !defined(CONFIG_405) && !defined(CONFIG_405EX)
68 static int pci_arbiter_enabled(void)
70 #if defined(CONFIG_405GP)
71 return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
74 #if defined(CONFIG_405EP)
75 return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
78 #if defined(CONFIG_440GP)
79 return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
82 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
86 return (val & 0x80000000);
88 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
89 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
93 return (val & 0x80000000);
98 #if defined(CONFIG_405EP)
101 static int i2c_bootrom_enabled(void)
103 #if defined(CONFIG_405EP)
104 return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
108 mfsdr(sdr_sdcs, val);
109 return (val & SDR0_SDCS_SDD);
114 #if defined(CONFIG_440GX)
115 #define SDR0_PINSTP_SHIFT 29
116 static char *bootstrap_str[] = {
126 static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
129 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
130 #define SDR0_PINSTP_SHIFT 30
131 static char *bootstrap_str[] = {
137 static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
140 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
141 #define SDR0_PINSTP_SHIFT 29
142 static char *bootstrap_str[] = {
152 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
155 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
156 #define SDR0_PINSTP_SHIFT 29
157 static char *bootstrap_str[] = {
167 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
170 #if defined(CONFIG_405EZ)
171 #define SDR0_PINSTP_SHIFT 28
172 static char *bootstrap_str[] = {
175 "NAND (512 page, 4 addr cycle)",
179 "NAND (2K page, 5 addr cycle)",
183 "NAND (2K page, 4 addr cycle)",
185 "NAND (512 page, 3 addr cycle)",
190 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
191 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
194 #if defined(CONFIG_405EX)
195 #define SDR0_PINSTP_SHIFT 29
196 static char *bootstrap_str[] = {
206 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
209 #if defined(SDR0_PINSTP_SHIFT)
210 static int bootstrap_option(void)
214 mfsdr(SDR_PINSTP, val);
215 return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
217 #endif /* SDR0_PINSTP_SHIFT */
220 #if defined(CONFIG_440)
221 static int do_chip_reset (unsigned long sys0, unsigned long sys1)
223 /* Changes to cpc0_sys0 and cpc0_sys1 require chip
226 mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
227 mtdcr (cpc0_sys0, sys0);
228 mtdcr (cpc0_sys1, sys1);
229 mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
230 mtspr (dbcr0, 0x20000000); /* Reset the chip */
239 #if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
240 uint pvr = get_pvr();
241 ulong clock = gd->cpu_clk;
244 #if !defined(CONFIG_IOP480)
245 char addstr[64] = "";
250 get_sys_info(&sys_info);
252 puts("AMCC PowerPC 4");
254 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
255 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
256 defined(CONFIG_405EX)
259 #if defined(CONFIG_440)
277 case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
291 case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
310 strcpy(addstr, "Security support");
315 strcpy(addstr, "No Security support");
320 strcpy(addstr, "Security support");
325 strcpy(addstr, "No Security support");
328 #if defined(CONFIG_440)
331 /* See errata 1.12: CHIP_4 */
332 if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
333 (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
334 puts ( "\n\t CPC0_SYSx DCRs corrupted. "
335 "Resetting chip ...\n");
336 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
337 do_chip_reset ( mfdcr(cpc0_strp0),
367 case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
371 case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
374 #endif /* CONFIG_440EP */
377 case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
381 case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
384 #endif /* CONFIG_440GR */
385 #endif /* CONFIG_440 */
388 case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
390 strcpy(addstr, "Security/Kasumi support");
393 case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
395 strcpy(addstr, "No Security/Kasumi support");
397 #endif /* CONFIG_440EPX */
400 case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
402 strcpy(addstr, "Security/Kasumi support");
405 case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
407 strcpy(addstr, "No Security/Kasumi support");
409 #endif /* CONFIG_440GRX */
411 case PVR_440SP_6_RAB:
413 strcpy(addstr, "RAID 6 support");
418 strcpy(addstr, "No RAID 6 support");
423 strcpy(addstr, "RAID 6 support");
428 strcpy(addstr, "No RAID 6 support");
431 case PVR_440SPe_6_RA:
433 strcpy(addstr, "RAID 6 support");
438 strcpy(addstr, "No RAID 6 support");
441 case PVR_440SPe_6_RB:
443 strcpy(addstr, "RAID 6 support");
448 strcpy(addstr, "No RAID 6 support");
452 printf (" UNKNOWN (PVR=%08x)", pvr);
456 printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
457 sys_info.freqPLB / 1000000,
458 get_OPB_freq() / 1000000,
459 sys_info.freqEBC / 1000000);
462 printf(" %s\n", addstr);
464 #if defined(I2C_BOOTROM)
465 printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
466 #endif /* I2C_BOOTROM */
467 #if defined(SDR0_PINSTP_SHIFT)
468 printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
469 printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
470 #endif /* SDR0_PINSTP_SHIFT */
472 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
473 printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
476 #if defined(PCI_ASYNC)
477 if (pci_async_enabled()) {
478 printf (", PCI async ext clock used");
480 printf (", PCI sync clock at %lu MHz",
481 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
485 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
489 #if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
490 printf (" 16 kB I-Cache 16 kB D-Cache");
491 #elif defined(CONFIG_440)
492 printf (" 32 kB I-Cache 32 kB D-Cache");
494 printf (" 16 kB I-Cache %d kB D-Cache",
495 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
497 #endif /* !defined(CONFIG_IOP480) */
499 #if defined(CONFIG_IOP480)
500 printf ("PLX IOP480 (PVR=%08x)", pvr);
501 printf (" at %s MHz:", strmhz(buf, clock));
502 printf (" %u kB I-Cache", 4);
503 printf (" %u kB D-Cache", 2);
506 #endif /* !defined(CONFIG_405) */
513 int ppc440spe_revB() {
517 if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
523 /* ------------------------------------------------------------------------- */
525 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
527 #if defined(CONFIG_BOARD_RESET)
530 #if defined(CFG_4xx_RESET_TYPE)
531 mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28);
534 * Initiate system reset in debug control register DBCR
536 mtspr(dbcr0, 0x30000000);
537 #endif /* defined(CFG_4xx_RESET_TYPE) */
538 #endif /* defined(CONFIG_BOARD_RESET) */
545 * Get timebase clock frequency
547 unsigned long get_tbclk (void)
549 #if !defined(CONFIG_IOP480)
552 get_sys_info(&sys_info);
553 return (sys_info.freqProcessor);
561 #if defined(CONFIG_WATCHDOG)
562 void watchdog_reset(void)
564 int re_enable = disable_interrupts();
565 reset_4xx_watchdog();
566 if (re_enable) enable_interrupts();
569 void reset_4xx_watchdog(void)
574 mtspr(tsr, 0x40000000);
576 #endif /* CONFIG_WATCHDOG */