2 * (C) Copyright 2000-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
30 * minor modifications by
31 * Wolfgang Denk <wd@denx.de>
37 #include <asm/cache.h>
40 #if !defined(CONFIG_405)
41 DECLARE_GLOBAL_DATA_PTR;
44 #if defined(CONFIG_BOARD_RESET)
45 void board_reset(void);
48 #if defined(CONFIG_440)
49 #define FREQ_EBC (sys_info.freqEPB)
50 #elif defined(CONFIG_405EZ)
51 #define FREQ_EBC ((CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / \
52 sys_info.pllExtBusDiv)
54 #define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv)
57 #if defined(CONFIG_405GP) || \
58 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
59 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
63 int pci_async_enabled(void)
65 #if defined(CONFIG_405GP)
66 return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
69 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
70 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
73 mfsdr(sdr_sdstp1, val);
74 return (val & SDR0_SDSTP1_PAME_MASK);
79 #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405)
80 int pci_arbiter_enabled(void)
82 #if defined(CONFIG_405GP)
83 return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
86 #if defined(CONFIG_405EP)
87 return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
90 #if defined(CONFIG_440GP)
91 return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
94 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
98 return (val & 0x80000000);
100 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
101 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
104 mfsdr(sdr_pci0, val);
105 return (val & 0x80000000);
110 #if defined(CONFIG_405EP) || defined(CONFIG_440GX) || \
111 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
112 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
113 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
117 int i2c_bootrom_enabled(void)
119 #if defined(CONFIG_405EP)
120 return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
124 mfsdr(sdr_sdcs, val);
125 return (val & SDR0_SDCS_SDD);
130 #if defined(CONFIG_440GX)
131 #define SDR0_PINSTP_SHIFT 29
132 static char *bootstrap_str[] = {
144 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
145 #define SDR0_PINSTP_SHIFT 30
146 static char *bootstrap_str[] = {
154 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
155 #define SDR0_PINSTP_SHIFT 29
156 static char *bootstrap_str[] = {
168 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
169 #define SDR0_PINSTP_SHIFT 29
170 static char *bootstrap_str[] = {
182 #if defined(CONFIG_405EZ)
183 #define SDR0_PINSTP_SHIFT 28
184 static char *bootstrap_str[] = {
187 "NAND (512 page, 4 addr cycle)",
191 "NAND (2K page, 5 addr cycle)",
195 "NAND (2K page, 4 addr cycle)",
197 "NAND (512 page, 3 addr cycle)",
204 #if defined(SDR0_PINSTP_SHIFT)
205 static int bootstrap_option(void)
209 mfsdr(SDR_PINSTP, val);
210 return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
212 #endif /* SDR0_PINSTP_SHIFT */
215 #if defined(CONFIG_440)
216 static int do_chip_reset(unsigned long sys0, unsigned long sys1);
222 #if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
223 uint pvr = get_pvr();
224 ulong clock = gd->cpu_clk;
227 #if !defined(CONFIG_IOP480)
228 char addstr[64] = "";
233 get_sys_info(&sys_info);
235 puts("AMCC PowerPC 4");
237 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
238 defined(CONFIG_405EP) || defined(CONFIG_405EZ)
241 #if defined(CONFIG_440)
259 case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
273 case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
290 #if defined(CONFIG_440)
293 /* See errata 1.12: CHIP_4 */
294 if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
295 (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
296 puts ( "\n\t CPC0_SYSx DCRs corrupted. "
297 "Resetting chip ...\n");
298 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
299 do_chip_reset ( mfdcr(cpc0_strp0),
329 case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
333 case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
336 #endif /* CONFIG_440EP */
339 case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
343 case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
346 #endif /* CONFIG_440GR */
347 #endif /* CONFIG_440 */
350 case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
352 strcpy(addstr, "Security/Kasumi support");
355 case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
357 strcpy(addstr, "No Security/Kasumi support");
359 #endif /* CONFIG_440EPX */
362 case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
364 strcpy(addstr, "Security/Kasumi support");
367 case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
369 strcpy(addstr, "No Security/Kasumi support");
371 #endif /* CONFIG_440GRX */
373 case PVR_440SP_6_RAB:
375 strcpy(addstr, "RAID 6 support");
380 strcpy(addstr, "No RAID 6 support");
385 strcpy(addstr, "RAID 6 support");
390 strcpy(addstr, "No RAID 6 support");
393 case PVR_440SPe_6_RA:
395 strcpy(addstr, "RAID 6 support");
400 strcpy(addstr, "No RAID 6 support");
403 case PVR_440SPe_6_RB:
405 strcpy(addstr, "RAID 6 support");
410 strcpy(addstr, "No RAID 6 support");
414 printf (" UNKNOWN (PVR=%08x)", pvr);
418 printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
419 sys_info.freqPLB / 1000000,
420 get_OPB_freq() / 1000000,
424 printf(" %s\n", addstr);
426 #if defined(I2C_BOOTROM)
427 printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
428 #endif /* I2C_BOOTROM */
429 #if defined(SDR0_PINSTP_SHIFT)
430 printf (" Bootstrap Option %c - ", (char)bootstrap_option() + 'A');
431 printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
432 #endif /* SDR0_PINSTP_SHIFT */
434 #if defined(CONFIG_PCI)
435 printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
438 #if defined(PCI_ASYNC)
439 if (pci_async_enabled()) {
440 printf (", PCI async ext clock used");
442 printf (", PCI sync clock at %lu MHz",
443 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
447 #if defined(CONFIG_PCI)
451 #if defined(CONFIG_405EP) || defined(CONFIG_405EZ)
452 printf (" 16 kB I-Cache 16 kB D-Cache");
453 #elif defined(CONFIG_440)
454 printf (" 32 kB I-Cache 32 kB D-Cache");
456 printf (" 16 kB I-Cache %d kB D-Cache",
457 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
459 #endif /* !defined(CONFIG_IOP480) */
461 #if defined(CONFIG_IOP480)
462 printf ("PLX IOP480 (PVR=%08x)", pvr);
463 printf (" at %s MHz:", strmhz(buf, clock));
464 printf (" %u kB I-Cache", 4);
465 printf (" %u kB D-Cache", 2);
468 #endif /* !defined(CONFIG_405) */
475 #if defined (CONFIG_440SPE)
476 int ppc440spe_revB() {
480 if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
487 /* ------------------------------------------------------------------------- */
489 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
491 #if defined(CONFIG_BOARD_RESET)
494 #if defined(CFG_4xx_RESET_TYPE)
495 mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28);
498 * Initiate system reset in debug control register DBCR
500 mtspr(dbcr0, 0x30000000);
501 #endif /* defined(CFG_4xx_RESET_TYPE) */
502 #endif /* defined(CONFIG_BOARD_RESET) */
507 #if defined(CONFIG_440)
508 static int do_chip_reset (unsigned long sys0, unsigned long sys1)
510 /* Changes to cpc0_sys0 and cpc0_sys1 require chip
513 mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
514 mtdcr (cpc0_sys0, sys0);
515 mtdcr (cpc0_sys1, sys1);
516 mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
517 mtspr (dbcr0, 0x20000000); /* Reset the chip */
525 * Get timebase clock frequency
527 unsigned long get_tbclk (void)
529 #if !defined(CONFIG_IOP480)
532 get_sys_info(&sys_info);
533 return (sys_info.freqProcessor);
541 #if defined(CONFIG_WATCHDOG)
545 int re_enable = disable_interrupts();
546 reset_4xx_watchdog();
547 if (re_enable) enable_interrupts();
551 reset_4xx_watchdog(void)
556 mtspr(tsr, 0x40000000);
558 #endif /* CONFIG_WATCHDOG */