3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * written or collected and sometimes rewritten by
30 * Magnus Damm <damm@bitsmart.com>
32 * minor modifications by
33 * Wolfgang Denk <wd@denx.de>
39 #include <asm/cache.h>
43 #if defined(CONFIG_440)
44 static int do_chip_reset( unsigned long sys0, unsigned long sys1 );
47 /* ------------------------------------------------------------------------- */
51 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_IOP480) || defined(CONFIG_440)
54 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_IOP480)
55 DECLARE_GLOBAL_DATA_PTR;
57 ulong clock = gd->cpu_clk;
61 #if defined(CONFIG_405GP) || defined(CONFIG_405CR)
62 PPC405_SYS_INFO sys_info;
66 get_sys_info(&sys_info);
69 puts("IBM PowerPC 405GP");
70 if (pvr == PVR_405GPR_RA) {
76 puts("IBM PowerPC 405CR Rev. ");
104 printf("? (PVR=%08x)", pvr);
108 printf(" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
109 sys_info.freqPLB / 1000000,
110 sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
111 sys_info.freqPLB / sys_info.pllExtBusDiv / 1000000);
114 if (mfdcr(strap) & PSR_PCI_ASYNC_EN)
115 printf(" PCI async ext clock used, ");
117 printf(" PCI sync clock at %lu MHz, ",
118 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
119 if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
120 printf("internal PCI arbiter enabled\n");
122 printf("external PCI arbiter enabled\n");
125 if ((pvr | 0x00000001) == PVR_405GPR_RA) {
126 printf(" 16 kB I-Cache 16 kB D-Cache");
128 printf(" 16 kB I-Cache 8 kB D-Cache");
132 #endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */
135 printf("PLX IOP480 (PVR=%08x)", pvr);
136 printf(" at %s MHz:", strmhz(buf, clock));
137 printf(" %u kB I-Cache", 4);
138 printf(" %u kB D-Cache", 2);
141 #if defined(CONFIG_440)
142 puts("IBM PowerPC 440 Rev. ");
147 /* See errata 1.12: CHIP_4 */
148 if( ( mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0) )
149 ||( mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1) ) ){
150 puts("\n\t CPC0_SYSx DCRs corrupted. Resetting chip ...\n");
151 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
152 do_chip_reset( mfdcr(cpc0_strp0), mfdcr(cpc0_strp1) );
159 printf("UNKNOWN (PVR=%08x)", pvr);
170 /* ------------------------------------------------------------------------- */
172 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
175 * Initiate system reset in debug control register DBCR
177 __asm__ __volatile__("lis 3, 0x3000" ::: "r3");
178 #if defined(CONFIG_440)
179 __asm__ __volatile__("mtspr 0x134, 3");
181 __asm__ __volatile__("mtspr 0x3f2, 3");
186 #if defined(CONFIG_440)
188 int do_chip_reset( unsigned long sys0, unsigned long sys1 )
190 /* Changes to cpc0_sys0 and cpc0_sys1 require chip
193 mtdcr( cntrl0, mfdcr(cntrl0) | 0x80000000 ); /* Set SWE */
194 mtdcr( cpc0_sys0, sys0 );
195 mtdcr( cpc0_sys1, sys1 );
196 mtdcr( cntrl0, mfdcr(cntrl0) & ~0x80000000 ); /* Clr SWE */
197 mtspr( dbcr0, 0x20000000); /* Reset the chip */
205 * Get timebase clock frequency
207 unsigned long get_tbclk (void)
209 #if defined(CONFIG_440)
213 get_sys_info(&sys_info);
214 return (sys_info.freqProcessor);
216 #elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405)
218 PPC405_SYS_INFO sys_info;
220 get_sys_info(&sys_info);
221 return (sys_info.freqProcessor);
223 #elif defined(CONFIG_IOP480)
229 # error get_tbclk() not implemented
236 #if defined(CONFIG_WATCHDOG)
240 int re_enable = disable_interrupts();
241 reset_4xx_watchdog();
242 if (re_enable) enable_interrupts();
246 reset_4xx_watchdog(void)
251 mtspr(tsr, 0x40000000);
253 #endif /* CONFIG_WATCHDOG */