2 * (C) Copyright 2000-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
30 * minor modifications by
31 * Wolfgang Denk <wd@denx.de>
37 #include <asm/cache.h>
40 #if !defined(CONFIG_405)
41 DECLARE_GLOBAL_DATA_PTR;
44 #if defined(CONFIG_440)
45 #define FREQ_EBC (sys_info.freqEPB)
47 #define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv)
50 #if defined(CONFIG_405GP) || \
51 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
52 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
56 int pci_async_enabled(void)
58 #if defined(CONFIG_405GP)
59 return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
62 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
63 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
66 mfsdr(sdr_sdstp1, val);
67 return (val & SDR0_SDSTP1_PAME_MASK);
72 #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405)
73 int pci_arbiter_enabled(void)
75 #if defined(CONFIG_405GP)
76 return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
79 #if defined(CONFIG_405EP)
80 return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
83 #if defined(CONFIG_440GP)
84 return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
87 #if defined(CONFIG_440GX) || \
88 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
89 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
90 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
93 mfsdr(sdr_sdstp1, val);
94 return (val & SDR0_SDSTP1_PAE_MASK);
99 #if defined(CONFIG_405EP) || defined(CONFIG_440GX) || \
100 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
101 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
102 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
106 int i2c_bootrom_enabled(void)
108 #if defined(CONFIG_405EP)
109 return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
113 mfsdr(sdr_sdcs, val);
114 return (val & SDR0_SDCS_SDD);
118 #if defined(CONFIG_440GX)
119 #define SDR0_PINSTP_SHIFT 29
120 static char *bootstrap_str[] = {
132 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
133 #define SDR0_PINSTP_SHIFT 30
134 static char *bootstrap_str[] = {
142 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
143 #define SDR0_PINSTP_SHIFT 29
144 static char *bootstrap_str[] = {
156 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
157 #define SDR0_PINSTP_SHIFT 29
158 static char *bootstrap_str[] = {
170 #if defined(SDR0_PINSTP_SHIFT)
171 static int bootstrap_option(void)
175 mfsdr(sdr_pinstp, val);
176 return ((val & 0xe0000000) >> SDR0_PINSTP_SHIFT);
178 #endif /* SDR0_PINSTP_SHIFT */
182 #if defined(CONFIG_440)
183 static int do_chip_reset(unsigned long sys0, unsigned long sys1);
189 #if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
190 uint pvr = get_pvr();
191 ulong clock = gd->cpu_clk;
193 char addstr[64] = "";
195 #if !defined(CONFIG_IOP480)
200 get_sys_info(&sys_info);
202 puts("AMCC PowerPC 4");
204 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
207 #if defined(CONFIG_440)
225 case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
239 case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
252 #if defined(CONFIG_440)
255 /* See errata 1.12: CHIP_4 */
256 if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
257 (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
258 puts ( "\n\t CPC0_SYSx DCRs corrupted. "
259 "Resetting chip ...\n");
260 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
261 do_chip_reset ( mfdcr(cpc0_strp0),
291 case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
295 case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
298 #endif /* CONFIG_440EP */
301 case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
305 case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
308 #endif /* CONFIG_440GR */
309 #endif /* CONFIG_440 */
313 strcpy(addstr, "Security/Kasumi support");
318 strcpy(addstr, "No Security/Kasumi support");
323 strcpy(addstr, "Security/Kasumi support");
328 strcpy(addstr, "No Security/Kasumi support");
348 printf (" UNKNOWN (PVR=%08x)", pvr);
352 printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
353 sys_info.freqPLB / 1000000,
354 sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
358 printf(" %s\n", addstr);
360 #if defined(I2C_BOOTROM)
361 printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
362 #if defined(SDR0_PINSTP_SHIFT)
363 printf (" Bootstrap Option %c - ", (char)bootstrap_option() + 'A');
364 printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
368 #if defined(CONFIG_PCI)
369 printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
372 #if defined(PCI_ASYNC)
373 if (pci_async_enabled()) {
374 printf (", PCI async ext clock used");
376 printf (", PCI sync clock at %lu MHz",
377 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
381 #if defined(CONFIG_PCI)
385 #if defined(CONFIG_405EP)
386 printf (" 16 kB I-Cache 16 kB D-Cache");
387 #elif defined(CONFIG_440)
388 printf (" 32 kB I-Cache 32 kB D-Cache");
390 printf (" 16 kB I-Cache %d kB D-Cache",
391 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
393 #endif /* !defined(CONFIG_IOP480) */
395 #if defined(CONFIG_IOP480)
396 printf ("PLX IOP480 (PVR=%08x)", pvr);
397 printf (" at %s MHz:", strmhz(buf, clock));
398 printf (" %u kB I-Cache", 4);
399 printf (" %u kB D-Cache", 2);
402 #endif /* !defined(CONFIG_405) */
409 #if defined (CONFIG_440SPE)
410 int ppc440spe_revB() {
414 if (pvr == PVR_440SPe_RB)
421 /* ------------------------------------------------------------------------- */
423 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
425 #if defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)
426 /*give reset to BCSR*/
427 *(unsigned char*)(CFG_BCSR_BASE | 0x06) = 0x09;
432 * Initiate system reset in debug control register DBCR
434 __asm__ __volatile__("lis 3, 0x3000" ::: "r3");
435 #if defined(CONFIG_440)
436 __asm__ __volatile__("mtspr 0x134, 3");
438 __asm__ __volatile__("mtspr 0x3f2, 3");
441 #endif/* defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)*/
445 #if defined(CONFIG_440)
446 static int do_chip_reset (unsigned long sys0, unsigned long sys1)
448 /* Changes to cpc0_sys0 and cpc0_sys1 require chip
451 mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
452 mtdcr (cpc0_sys0, sys0);
453 mtdcr (cpc0_sys1, sys1);
454 mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
455 mtspr (dbcr0, 0x20000000); /* Reset the chip */
463 * Get timebase clock frequency
465 unsigned long get_tbclk (void)
467 #if !defined(CONFIG_IOP480)
470 get_sys_info(&sys_info);
471 return (sys_info.freqProcessor);
479 #if defined(CONFIG_WATCHDOG)
483 int re_enable = disable_interrupts();
484 reset_4xx_watchdog();
485 if (re_enable) enable_interrupts();
489 reset_4xx_watchdog(void)
494 mtspr(tsr, 0x40000000);
496 #endif /* CONFIG_WATCHDOG */